65 #include <drivers/hw_include/cslr_sdfm.h>
66 #include <drivers/hw_include/cslr_soc.h>
67 #include <drivers/hw_include/hw_types.h>
76 #define SDFM_GET_LOW_THRESHOLD(C) ((uint16_t)(C))
79 #define SDFM_GET_HIGH_THRESHOLD(C) ((uint16_t)((uint32_t)(C) >> 16U))
83 #define SDFM_GET_LOW_THRESHOLD_BOTH(C1, C2) \
84 ((((uint32_t)(SDFM_GET_LOW_THRESHOLD(C2))) << 16U) | \
85 ((uint32_t)(SDFM_GET_LOW_THRESHOLD(C1))))
89 #define SDFM_GET_HIGH_THRESHOLD_BOTH(C1, C2) \
90 ((((uint32_t)(SDFM_GET_HIGH_THRESHOLD(C2))) << 16U) | \
91 ((uint32_t)(SDFM_GET_HIGH_THRESHOLD(C1))))
94 #define SDFM_SET_OSR(X) (((X) - 1) << 8U)
97 #define SDFM_SHIFT_VALUE(X) ((X) << 2U)
100 #define SDFM_THRESHOLD(H, L) ((((uint32_t)(H)) << 16U) | (L))
103 #define SDFM_SET_FIFO_LEVEL(X) ((X) << 7U)
106 #define SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) (0x8000 | (X))
109 #define SDFM_FILTER_DISABLE (0x0U)
110 #define SDFM_FILTER_ENABLE (0x2U)
119 #define SDFM_SDFIL_OFFSET (CSL_SDFM_SDCTLPARM2 - CSL_SDFM_SDCTLPARM1)
122 #define SDFM_DIGFIL_OFFSET (CSL_SDFM_SDCOMP2CTL - CSL_SDFM_SDCOMP1CTL)
125 #define SDFM_SDFLT1CMPHx_OFFSET (CSL_SDFM_SDFLT1CMPH2 - CSL_SDFM_SDFLT1CMPH1)
128 #define SDFM_SDFLT1CMPLx_OFFSET (CSL_SDFM_SDFLT1CMPL2 - CSL_SDFM_SDFLT1CMPL1)
137 #define SDFM_COMPEVT_FILTER_CONFIG_M (CSL_SDFM_SDCOMP1EVT1FLTCTL_SAMPWIN_MASK | \
138 CSL_SDFM_SDCOMP1EVT1FLTCTL_THRESH_MASK)
147 #define SDFM_COMPEVT_FILTER_LOCK_M (SDFM_SDCOMPLOCK_SDCOMPCTL | \
148 SDFM_SDCOMPLOCK_COMP)
157 #define SDFM_CLOCK_SYNCHRONIZER CSL_SDFM_SDCTLPARM1_SDCLKSYNC_MASK
158 #define SDFM_DATA_SYNCHRONIZER CSL_SDFM_SDCTLPARM1_SDDATASYNC_MASK
166 #define SDFM_OUTPUT_WITHIN_THRESHOLD (0)
167 #define SDFM_OUTPUT_ABOVE_THRESHOLD (1)
168 #define SDFM_OUTPUT_BELOW_THRESHOLD (2)
176 #define SDFM_FILTER_1 (0)
177 #define SDFM_FILTER_2 (1)
178 #define SDFM_FILTER_3 (2)
179 #define SDFM_FILTER_4 (3)
188 #define SDFM_FILTER_SINC_FAST (0x00)
189 #define SDFM_FILTER_SINC_1 (0x10)
191 #define SDFM_FILTER_SINC_2 (0x20)
193 #define SDFM_FILTER_SINC_3 (0x30)
203 #define SDFM_MODULATOR_CLK_EQUAL_DATA_RATE (0)
212 #define SDFM_DATA_FORMAT_16_BIT (0)
213 #define SDFM_DATA_FORMAT_32_BIT (1)
223 #define SDFM_DATA_READY_SOURCE_DIRECT (0)
224 #define SDFM_DATA_READY_SOURCE_FIFO (1)
233 #define SDFM_SYNC_PWM0_SOCA (0)
234 #define SDFM_SYNC_PWM0_SOCB (1)
235 #define SDFM_SYNC_PWM1_SOCA (2)
236 #define SDFM_SYNC_PWM1_SOCB (3)
237 #define SDFM_SYNC_PWM2_SOCA (4)
238 #define SDFM_SYNC_PWM2_SOCB (5)
239 #define SDFM_SYNC_PWM3_SOCA (6)
240 #define SDFM_SYNC_PWM3_SOCB (7)
241 #define SDFM_SYNC_PWM4_SOCA (8)
242 #define SDFM_SYNC_PWM4_SOCB (9)
243 #define SDFM_SYNC_PWM5_SOCA (10)
244 #define SDFM_SYNC_PWM5_SOCB (11)
245 #define SDFM_SYNC_PWM6_SOCA (12)
246 #define SDFM_SYNC_PWM6_SOCB (13)
247 #define SDFM_SYNC_PWM7_SOCA (14)
248 #define SDFM_SYNC_PWM7_SOCB (15)
249 #define SDFM_SYNC_PWM8_SOCA (16)
250 #define SDFM_SYNC_PWM8_SOCB (17)
251 #define SDFM_SYNC_PWM9_SOCA (18)
252 #define SDFM_SYNC_PWM9_SOCB (19)
253 #define SDFM_SYNC_PWM10_SOCA (20)
254 #define SDFM_SYNC_PWM10_SOCB (21)
255 #define SDFM_SYNC_PWM11_SOCA (22)
256 #define SDFM_SYNC_PWM11_SOCB (23)
257 #define SDFM_SYNC_PWM12_SOCA (24)
258 #define SDFM_SYNC_PWM12_SOCB (25)
259 #define SDFM_SYNC_PWM13_SOCA (26)
260 #define SDFM_SYNC_PWM13_SOCB (27)
261 #define SDFM_SYNC_PWM14_SOCA (28)
262 #define SDFM_SYNC_PWM14_SOCB (29)
263 #define SDFM_SYNC_PWM15_SOCA (30)
264 #define SDFM_SYNC_PWM15_SOCB (31)
265 #define SDFM_SYNC_PWM16_SOCA (32)
266 #define SDFM_SYNC_PWM16_SOCB (33)
267 #define SDFM_SYNC_PWM17_SOCA (34)
268 #define SDFM_SYNC_PWM17_SOCB (35)
269 #define SDFM_SYNC_PWM18_SOCA (36)
270 #define SDFM_SYNC_PWM18_SOCB (37)
271 #define SDFM_SYNC_PWM19_SOCA (38)
272 #define SDFM_SYNC_PWM19_SOCB (39)
273 #define SDFM_SYNC_PWM20_SOCA (40)
274 #define SDFM_SYNC_PWM20_SOCB (41)
275 #define SDFM_SYNC_PWM21_SOCA (42)
276 #define SDFM_SYNC_PWM21_SOCB (43)
277 #define SDFM_SYNC_PWM22_SOCA (44)
278 #define SDFM_SYNC_PWM22_SOCB (45)
279 #define SDFM_SYNC_PWM23_SOCA (46)
280 #define SDFM_SYNC_PWM23_SOCB (47)
281 #define SDFM_SYNC_PWM24_SOCA (48)
282 #define SDFM_SYNC_PWM24_SOCB (49)
283 #define SDFM_SYNC_PWM25_SOCA (50)
284 #define SDFM_SYNC_PWM25_SOCB (51)
285 #define SDFM_SYNC_PWM26_SOCA (52)
286 #define SDFM_SYNC_PWM26_SOCB (53)
287 #define SDFM_SYNC_PWM27_SOCA (54)
288 #define SDFM_SYNC_PWM27_SOCB (55)
289 #define SDFM_SYNC_PWM28_SOCA (56)
290 #define SDFM_SYNC_PWM28_SOCB (57)
291 #define SDFM_SYNC_PWM29_SOCA (58)
292 #define SDFM_SYNC_PWM29_SOCB (59)
293 #define SDFM_SYNC_PWM30_SOCA (60)
294 #define SDFM_SYNC_PWM30_SOCB (61)
295 #define SDFM_SYNC_PWM31_SOCA (62)
296 #define SDFM_SYNC_PWM31_SOCB (63)
305 #define SDFM_FIFO_NOT_CLEARED_ON_SYNC (0)
306 #define SDFM_FIFO_CLEARED_ON_SYNC (1)
316 #define SDFM_MANUAL_CLEAR_WAIT_FOR_SYNC (0)
317 #define SDFM_AUTO_CLEAR_WAIT_FOR_SYNC (1)
326 #define SDFM_COMP_EVENT_1 CSL_SDFM_SDCPARM1_CEVT1SEL_SHIFT
327 #define SDFM_COMP_EVENT_2 CSL_SDFM_SDCPARM1_CEVT2SEL_SHIFT
336 #define SDFM_COMP_EVENT_SRC_COMPH1 (0)
337 #define SDFM_COMP_EVENT_SRC_COMPH1_L1 (1)
339 #define SDFM_COMP_EVENT_SRC_COMPH2 (2)
341 #define SDFM_COMP_EVENT_SRC_COMPH2_L2 (3)
343 #define SDFM_COMP_EVENT_SRC_COMPL1 (0)
345 #define SDFM_COMP_EVENT_SRC_COMPL2 (2)
355 #define SDFM_CLK_SOURCE_CHANNEL_CLK (0x0)
356 #define SDFM_CLK_SOURCE_SD1_CLK CSL_SDFM_SDCTLPARM1_SDCLKSEL_MASK
366 #define SDFM_COMPHOUT_SOURCE_COMPHIN (0x0)
367 #define SDFM_COMPHOUT_SOURCE_FILTER (0x8)
377 #define SDFM_COMPLOUT_SOURCE_COMPLIN (0x000)
378 #define SDFM_COMPLOUT_SOURCE_FILTER (0x800)
401 #define SDFM_MODULATOR_FAILURE_INTERRUPT (0x200U)
402 #define SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT (0x40U)
404 #define SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT (0x20U)
406 #define SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT (0x1U)
408 #define SDFM_FIFO_INTERRUPT (0x1000U)
410 #define SDFM_FIFO_OVERFLOW_INTERRUPT (0x8000U)
419 #define SDFM_MASTER_INTERRUPT_FLAG (0x80000000U)
420 #define SDFM_FILTER_1_HIGH_THRESHOLD_FLAG (0x1U)
422 #define SDFM_FILTER_1_LOW_THRESHOLD_FLAG (0x2U)
424 #define SDFM_FILTER_2_HIGH_THRESHOLD_FLAG (0x4U)
426 #define SDFM_FILTER_2_LOW_THRESHOLD_FLAG (0x8U)
428 #define SDFM_FILTER_3_HIGH_THRESHOLD_FLAG (0x10U)
430 #define SDFM_FILTER_3_LOW_THRESHOLD_FLAG (0x20U)
432 #define SDFM_FILTER_4_HIGH_THRESHOLD_FLAG (0x40U)
434 #define SDFM_FILTER_4_LOW_THRESHOLD_FLAG (0x80U)
436 #define SDFM_FILTER_1_MOD_FAILED_FLAG (0x100U)
438 #define SDFM_FILTER_2_MOD_FAILED_FLAG (0x200U)
440 #define SDFM_FILTER_3_MOD_FAILED_FLAG (0x400U)
442 #define SDFM_FILTER_4_MOD_FAILED_FLAG (0x800U)
444 #define SDFM_FILTER_1_NEW_DATA_FLAG (0x1000U)
446 #define SDFM_FILTER_2_NEW_DATA_FLAG (0x2000U)
448 #define SDFM_FILTER_3_NEW_DATA_FLAG (0x4000U)
450 #define SDFM_FILTER_4_NEW_DATA_FLAG (0x8000U)
452 #define SDFM_FILTER_1_FIFO_OVERFLOW_FLAG (0x10000U)
454 #define SDFM_FILTER_2_FIFO_OVERFLOW_FLAG (0x20000U)
456 #define SDFM_FILTER_3_FIFO_OVERFLOW_FLAG (0x40000U)
458 #define SDFM_FILTER_4_FIFO_OVERFLOW_FLAG (0x80000U)
460 #define SDFM_FILTER_1_FIFO_INTERRUPT_FLAG (0x100000U)
462 #define SDFM_FILTER_2_FIFO_INTERRUPT_FLAG (0x200000U)
464 #define SDFM_FILTER_3_FIFO_INTERRUPT_FLAG (0x400000U)
466 #define SDFM_FILTER_4_FIFO_INTERRUPT_FLAG (0x800000U)
488 HW_WR_REG16((base + CSL_SDFM_SDDFPARM1 +
490 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
492 CSL_SDFM_SDDFPARM1_SDSYNCEN_MASK);
513 HW_WR_REG16((base + CSL_SDFM_SDDFPARM1 +
515 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
517 ~CSL_SDFM_SDDFPARM1_SDSYNCEN_MASK);
538 HW_WR_REG16((base + CSL_SDFM_SDDFPARM1 +
540 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
542 CSL_SDFM_SDDFPARM1_FEN_MASK);
563 HW_WR_REG16(base + CSL_SDFM_SDDFPARM1 +
565 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
567 ~CSL_SDFM_SDDFPARM1_FEN_MASK);
589 HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 +
591 HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 +
593 CSL_SDFM_SDFIFOCTL1_FFEN_MASK);
615 HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 +
617 HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 +
619 ~CSL_SDFM_SDFIFOCTL1_FFEN_MASK);
639 return(((HW_RD_REG16(base + CSL_SDFM_SDSTATUS) >> (uint16_t)filterNumber) &
662 HW_WR_REG16((base + CSL_SDFM_SDCTL),
663 HW_RD_REG16(base + CSL_SDFM_SDCTL) | (1U << filterNumber));
684 HW_WR_REG16((base + CSL_SDFM_SDCPARM1 +
686 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
688 CSL_SDFM_SDCPARM1_CEN_MASK);
709 HW_WR_REG16((base + CSL_SDFM_SDCPARM1 +
711 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
713 ~CSL_SDFM_SDCPARM1_CEN_MASK);
750 uint32_t compEventNum,
751 uint32_t compEventSource)
754 address = base + CSL_SDFM_SDCPARM1 + ((uint32_t)filterNumber *
761 (HW_RD_REG16(address) & ~((uint16_t)0x2U << compEventNum)) |
762 ((uint16_t)compEventSource << compEventNum) );
784 address = base + CSL_SDFM_SDDFPARM1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
790 (HW_RD_REG16(address) & (~CSL_SDFM_SDDFPARM1_SST_MASK)) |
791 ((uint16_t)filterType << 6U));
811 uint16_t overSamplingRatio)
817 address = base + CSL_SDFM_SDDFPARM1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
823 (HW_RD_REG16(address) & (~CSL_SDFM_SDDFPARM1_DOSR_MASK)) | overSamplingRatio);
848 address = base + CSL_SDFM_SDCTLPARM1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
853 HW_WR_REG16(address, (HW_RD_REG16(address) & (~CSL_SDFM_SDCTLPARM1_MOD_MASK)) |
854 (uint16_t)clockMode);
859 HW_WR_REG16(base + CSL_SDFM_SDCTLPARM1 +
861 HW_RD_REG16(base + CSL_SDFM_SDCTLPARM1 +
886 address = base + CSL_SDFM_SDDPARM1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
891 HW_WR_REG16(address, (HW_RD_REG16(address) & (~CSL_SDFM_SDDPARM1_DR_MASK)) |
892 ((uint16_t)dataFormat << 10U));
919 address = base + CSL_SDFM_SDDPARM1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
924 HW_WR_REG16(address, (HW_RD_REG16(address) & (~CSL_SDFM_SDDPARM1_SH_MASK)) |
925 (shiftValue << CSL_SDFM_SDDPARM1_SH_SHIFT));
949 uint32_t highThreshold)
953 DebugP_assert((uint16_t)highThreshold <= CSL_SDFM_SDFLT1CMPH1_HLT_MASK);
954 DebugP_assert((uint16_t)(highThreshold >> 16U) <= CSL_SDFM_SDFLT1CMPH2_HLT2_MASK);
956 address = base + CSL_SDFM_SDFLT1CMPH1 +
963 (HW_RD_REG16(address) & ~CSL_SDFM_SDFLT1CMPH1_HLT_MASK) |
964 (uint16_t)highThreshold);
967 ~CSL_SDFM_SDFLT1CMPH2_HLT2_MASK) | (uint16_t)(highThreshold >> 16U));
990 uint32_t lowThreshold)
994 DebugP_assert((uint16_t)lowThreshold <= CSL_SDFM_SDFLT1CMPL1_LLT_MASK);
995 DebugP_assert((uint16_t)(lowThreshold >> 16U) <= CSL_SDFM_SDFLT1CMPL2_LLT2_MASK);
997 address = base + CSL_SDFM_SDFLT1CMPL1 +
1003 HW_WR_REG16(address, (HW_RD_REG16(address) & ~CSL_SDFM_SDFLT1CMPL1_LLT_MASK) |
1004 (uint16_t)lowThreshold);
1007 ~CSL_SDFM_SDFLT1CMPL2_LLT2_MASK) | (uint16_t)(lowThreshold >> 16U));
1025 uint32_t filterNumber,
1026 uint16_t zeroCrossThreshold)
1032 address = base + CSL_SDFM_SDFLT1CMPHZ + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
1037 HW_WR_REG16(address,
1038 (HW_RD_REG16(address) & ~CSL_SDFM_SDFLT1CMPHZ_HLTZ_MASK) | zeroCrossThreshold);
1060 HW_WR_REG16(base + CSL_SDFM_SDCPARM1 +
1062 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
1064 CSL_SDFM_SDCPARM1_HZEN_MASK);
1085 HW_WR_REG16(base + CSL_SDFM_SDCPARM1 +
1087 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
1089 ~CSL_SDFM_SDCPARM1_HZEN_MASK);
1129 HW_WR_REG16(base + CSL_SDFM_SDCPARM1 + offset,
1130 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 + offset) |
1141 HW_WR_REG16(base + CSL_SDFM_SDDFPARM1 + offset,
1142 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 + offset) |
1143 CSL_SDFM_SDDFPARM1_AE_MASK);
1154 HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset,
1155 HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset) |
1197 HW_WR_REG16(base + CSL_SDFM_SDCPARM1 + offset,
1198 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 + offset) &
1209 HW_WR_REG16(base + CSL_SDFM_SDDFPARM1 + offset,
1210 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 + offset) &
1211 ~CSL_SDFM_SDDFPARM1_AE_MASK);
1222 HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset,
1223 HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset) &
1244 uint32_t filterType)
1248 address = base + CSL_SDFM_SDCPARM1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
1253 HW_WR_REG16(address,
1254 (HW_RD_REG16(address) & (~CSL_SDFM_SDCPARM1_CS1_CS0_MASK)) |
1255 ((uint16_t)filterType << 3U));
1275 uint32_t filterNumber,
1276 uint16_t overSamplingRatio)
1282 address = base + CSL_SDFM_SDCPARM1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
1287 HW_WR_REG16(address,
1288 (HW_RD_REG16(address) & (~CSL_SDFM_SDCPARM1_COSR_MASK)) |
1305 static inline uint32_t
1311 return(HW_RD_REG32(base + CSL_SDFM_SDDATA1 +
1334 static inline uint32_t
1340 return((uint32_t)((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
1341 (2U * (uint16_t)filterNumber)) & 0x3U));
1363 return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
1364 ((uint16_t)filterNumber + 8U)) & 0x1U) != 0x1U);
1386 return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
1387 ((uint16_t)filterNumber + 12U)) & 0x1U) == 0x1U);
1410 return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
1411 ((uint16_t)filterNumber + 16U)) & 0x1U) == 0x1U);
1434 return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
1435 ((uint16_t)filterNumber + 20U)) & 0x1U) == 0x1U);
1456 return((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >> 31U) == 0x1U);
1493 HW_WR_REG32((base + CSL_SDFM_SDIFLGCLR),
1494 HW_RD_REG32(base + CSL_SDFM_SDIFLGCLR) | flag);
1514 HW_WR_REG16(base + CSL_SDFM_SDCTL,
1515 HW_RD_REG16(base + CSL_SDFM_SDCTL) | CSL_SDFM_SDCTL_MIE_MASK);
1535 HW_WR_REG16(base + CSL_SDFM_SDCTL,
1536 HW_RD_REG16(base + CSL_SDFM_SDCTL) & ~CSL_SDFM_SDCTL_MIE_MASK);
1556 HW_WR_REG16(base + CSL_SDFM_SDMFILEN,
1557 HW_RD_REG16(base + CSL_SDFM_SDMFILEN) | CSL_SDFM_SDMFILEN_MFE_MASK);
1577 HW_WR_REG16(base + CSL_SDFM_SDMFILEN,
1578 HW_RD_REG16(base + CSL_SDFM_SDMFILEN) & ~CSL_SDFM_SDMFILEN_MFE_MASK);
1593 static inline uint16_t
1599 return((HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 +
1601 CSL_SDFM_SDFIFOCTL1_SDFFST_MASK) >> CSL_SDFM_SDFIFOCTL1_SDFFST_SHIFT);
1617 static inline uint16_t
1623 return(HW_RD_REG16(base + CSL_SDFM_SDCDATA1 +
1641 static inline uint32_t
1647 return(HW_RD_REG32(base + CSL_SDFM_SDDATFIFO1 +
1674 address = base + CSL_SDFM_SDFIFOCTL1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
1679 HW_WR_REG16(address,
1680 ((HW_RD_REG16(address) & (~CSL_SDFM_SDFIFOCTL1_SDFFIL_MASK)) | fifoLevel));
1701 uint32_t dataReadySource)
1705 address = base + CSL_SDFM_SDFIFOCTL1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
1710 HW_WR_REG16(address,
1711 (HW_RD_REG16(address) & ~CSL_SDFM_SDFIFOCTL1_DRINTSEL_MASK) |
1712 ((uint16_t)dataReadySource << 14U));
1734 return(((HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
1736 CSL_SDFM_SDSYNC1_WTSYNFLG_MASK) >> 7U) == 0x1U);
1757 HW_WR_REG16(base + CSL_SDFM_SDSYNC1 +
1759 HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
1761 CSL_SDFM_SDSYNC1_WTSYNCLR_MASK);
1783 HW_WR_REG16(base + CSL_SDFM_SDSYNC1 +
1785 HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
1787 CSL_SDFM_SDSYNC1_WTSYNCEN_MASK);
1809 HW_WR_REG16(base + CSL_SDFM_SDSYNC1 +
1811 HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
1813 ~CSL_SDFM_SDSYNC1_WTSYNCEN_MASK);
1834 uint32_t syncSource)
1838 address = base + CSL_SDFM_SDSYNC1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
1843 HW_WR_REG16(address,
1844 (HW_RD_REG16(address) & ~CSL_SDFM_SDSYNC1_SYNCSEL_MASK) |
1845 (uint16_t)syncSource);
1867 uint32_t fifoClearSyncMode)
1871 address = base + CSL_SDFM_SDSYNC1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
1876 HW_WR_REG16(address,
1877 (HW_RD_REG16(address) & ~CSL_SDFM_SDSYNC1_FFSYNCCLREN_MASK) |
1878 ((uint16_t)fifoClearSyncMode << 9U));
1902 uint32_t syncClearMode)
1906 address = base + CSL_SDFM_SDSYNC1 + ((uint32_t)filterNumber *
SDFM_SDFIL_OFFSET);
1911 HW_WR_REG16(address,
1912 (HW_RD_REG16(address) & ~CSL_SDFM_SDSYNC1_WTSCLREN_MASK) |
1913 ((uint16_t)syncClearMode << 10U));
1938 address = base + CSL_SDFM_SDCTLPARM1 +
1944 HW_WR_REG16(address,
1945 (HW_RD_REG16(address) & ~(CSL_SDFM_SDCTLPARM1_SDCLKSEL_MASK)) |
1946 (uint16_t)clkSource);
1967 uint16_t syncConfig)
1972 HW_WR_REG16(base + CSL_SDFM_SDCTLPARM1 +
1974 HW_RD_REG16(base + CSL_SDFM_SDCTLPARM1 +
1996 uint16_t syncConfig)
2001 HW_WR_REG16(base + CSL_SDFM_SDCTLPARM1 +
2003 HW_RD_REG16(base + CSL_SDFM_SDCTLPARM1 +
2028 address = base + CSL_SDFM_SDCOMP1CTL +
2034 HW_WR_REG16(address,
2035 (HW_RD_REG16(address) & ~CSL_SDFM_SDCOMP1CTL_CEVT1DIGFILTSEL_MASK) |
2060 address = base + CSL_SDFM_SDCOMP1CTL +
2066 HW_WR_REG16(address,
2067 (HW_RD_REG16(address) & ~CSL_SDFM_SDCOMP1CTL_CEVT2DIGFILTSEL_MASK) |
2089 HW_WR_REG16(base + CSL_SDFM_SDCOMP1EVT2FLTCTL +
2091 HW_RD_REG16(base + CSL_SDFM_SDCOMP1EVT2FLTCTL +
2093 (uint16_t)CSL_SDFM_SDCOMP1EVT2FLTCTL_FILINIT_MASK);
2114 HW_WR_REG16(base + CSL_SDFM_SDCOMP1EVT1FLTCTL +
2116 HW_RD_REG16(base + CSL_SDFM_SDCOMP1EVT1FLTCTL +
2118 (uint16_t)CSL_SDFM_SDCOMP1EVT1FLTCTL_FILINIT_MASK);
2140 uint16_t lockConfig)
2145 HW_WR_REG16(base + CSL_SDFM_SDCOMP1LOCK +
2147 HW_RD_REG16(base + CSL_SDFM_SDCOMP1LOCK +
2205 uint32_t config2, uint16_t config3);
2267 uint32_t highLowThreshold1,
2268 uint32_t highLowThreshold2,
2269 uint16_t zeroCrossThreshold);
2452 #endif // SDFM_V0_H_