AM263x MCU+ SDK  08.02.00
cslr_soc_defines.h
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33 
34 #ifndef CSLR_SOC_DEFINES_H_
35 #define CSLR_SOC_DEFINES_H_
36 
37 /* ========================================================================== */
38 /* Include Files */
39 /* ========================================================================== */
40 
41 /* None */
42 
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46 
47 /* ========================================================================== */
48 /* Macros & Typedefs */
49 /* ========================================================================== */
51 #define CSL_UART_PER_CNT (6U)
52 
54 #define CSL_SPI_PER_CNT (5U)
55 
57 #define CSL_LIN_PER_CNT (5U)
58 
60 #define CSL_I2C_PER_CNT (4U)
61 
63 #define CSL_MCAN_PER_CNT (4U)
64 
66 #define CSL_ETPWM_PER_CNT (32U)
67 
69 #define CSL_ECAP_PER_CNT (10U)
70 
72 #define CSL_EQEP_PER_CNT (3U)
73 
75 #define CSL_SDFM_PER_CNT (2U)
76 
78 #define CSL_ADC_PER_CNT (5U)
79 
81 #define CSL_CMPSSA_PER_CNT (10U)
82 
84 #define CSL_CMPSSB_PER_CNT (10U)
85 
87 #define SOC_EDMA_NUM_DMACH (64U)
88 
89 #define SOC_EDMA_NUM_QDMACH (8U)
90 
91 #define SOC_EDMA_NUM_PARAMSETS (256U)
92 
93 #define SOC_EDMA_NUM_EVQUE (2U)
94 
95 #define SOC_EDMA_CHMAPEXIST (1U)
96 
97 #define SOC_EDMA_NUM_REGIONS (8U)
98 
99 #define SOC_EDMA_MEMPROTECT (1U)
100 
101 #define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)
102 
103 /*FIXME: Is below valid for AM263?*/
110 #define CSL_CORE_ID_R5FSS0_0 (0U)
111 #define CSL_CORE_ID_R5FSS0_1 (1U)
112 #define CSL_CORE_ID_R5FSS1_0 (2U)
113 #define CSL_CORE_ID_R5FSS1_1 (3U)
114 #define CSL_CORE_ID_MAX (4U)
115 
123 #define PRIV_ID_M4FSS0_0 (1U)
124 #define PRIV_ID_R5FSS0_0 (4U)
125 #define PRIV_ID_R5FSS0_1 (5U)
126 #define PRIV_ID_R5FSS1_0 (6U)
127 #define PRIV_ID_R5FSS1_1 (7U)
128 #define PRIV_ID_ICSSM (9U)
129 #define PRIV_ID_CPSW (10U)
130 
133 /***********************************************************************
134  * MSS - CLOCK setting
135  ***********************************************************************/
136  /* Sys_vclk : 200MHz */
137 #define MSS_SYS_VCLK 200000000U
138 #define R5F_CLOCK_MHZ 400U
139 
140 /***********************************************************************
141  * Cache line size definitions
142  ***********************************************************************/
143 /* Cache line size definitions */
144 #if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
145 #define CSL_CACHE_L1P_LINESIZE (32U)
146 #define CSL_CACHE_L1D_LINESIZE (32U)
147 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M') /* M4F */
148 /* No cache support */
149 #endif
150 
151 /* ========================================================================== */
152 /* Structures and Enums */
153 /* ========================================================================== */
154 
155 /* None */
156 
157 /* ========================================================================== */
158 /* Global Variables */
159 /* ========================================================================== */
160 
161 /* None */
162 
163 /* ========================================================================== */
164 /* Function Declarations */
165 /* ========================================================================== */
166 
167 /* None */
168 
169 #ifdef __cplusplus
170 }
171 #endif
172 
173 #endif /* CSLR_SOC_DEFINES_H_ */