AM263Px MCU+ SDK  10.01.00
sdlr_vtm.h
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1 /*
2  * Copyright (C) 2024 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 
34 #ifndef SDLR_VTM_H_
35 #define SDLR_VTM_H_
36 
37 #ifdef __cplusplus
38 extern "C"
39 {
40 #endif
41 
42 
43 #include <stdint.h>
44 /**************************************************************************
45 * Module Base Offset Values
46 **************************************************************************/
47 
48 #define SDL_VTM_CFG1_BASE (0x50D80D00U)
49 
50 #define SDL_VTM_TS_MAX_NUM (4U)
51 
52 /**************************************************************************
53 * Hardware Region : MMRs in TOP_CTRL
54 **************************************************************************/
55 
56 
57 /**************************************************************************
58 * Register Overlay Structure
59 **************************************************************************/
60 
61 typedef struct {
62  volatile uint32_t TSENSE_CFG;
63  volatile uint32_t TSENSE_STATUS;
64  volatile uint32_t TSENSE_STATUS_RAW;
65  volatile uint32_t RSVD0[4];
66  volatile uint32_t TSENSE0_TSHUT;
67  volatile uint32_t TSENSE0_ALERT;
68  volatile uint32_t TSENSE0_CNTL;
69  volatile uint32_t TSENSE0_RESULT;
70  volatile uint32_t TSENSE0_DATA0;
71  volatile uint32_t TSENSE0_DATA1;
72  volatile uint32_t TSENSE0_DATA2;
73  volatile uint32_t TSENSE0_DATA3;
74  volatile uint32_t TSENSE0_ACCU;
75  volatile uint32_t RSVD1[12];
76  volatile uint32_t TSENSE1_TSHUT;
77  volatile uint32_t TSENSE1_ALERT;
78  volatile uint32_t TSENSE1_CNTL;
79  volatile uint32_t TSENSE1_RESULT;
80  volatile uint32_t TSENSE1_DATA0;
81  volatile uint32_t TSENSE1_DATA1;
82  volatile uint32_t TSENSE1_DATA2;
83  volatile uint32_t TSENSE1_DATA3;
84  volatile uint32_t TSENSE1_ACCU;
85  volatile uint32_t RSVD3[24];
86  volatile uint32_t TSENSE2_RESULT;
87  volatile uint32_t RSVD4[44];
88  volatile uint32_t TSENSE3_RESULT;
90 
91 
92 /**************************************************************************
93 * Register Macros
94 **************************************************************************/
95 
96 #define SDL_VTM_TSENSE_CFG (0x00000D00U)
97 #define SDL_VTM_TSENSE_STATUS (0x00000D04U)
98 #define SDL_VTM_TSENSE_STATUS_RAW (0x00000D08U)
99 #define SDL_VTM_TSENSE0_TSHUT (0x00000D10U)
100 #define SDL_VTM_TSENSE0_ALERT (0x00000D14U)
101 #define SDL_VTM_TSENSE0_CNTL (0x00000D18U)
102 #define SDL_VTM_TSENSE0_RESULT (0x00000D1CU)
103 #define SDL_VTM_TSENSE0_DATA0 (0x00000D20U)
104 #define SDL_VTM_TSENSE0_DATA1 (0x00000D24U)
105 #define SDL_VTM_TSENSE0_DATA2 (0x00000D28U)
106 #define SDL_VTM_TSENSE0_DATA3 (0x00000D2CU)
107 #define SDL_VTM_TSENSE0_ACCU (0x00000D30U)
108 #define SDL_VTM_TSENSE1_TSHUT (0x00000D40U)
109 #define SDL_VTM_TSENSE1_ALERT (0x00000D44U)
110 #define SDL_VTM_TSENSE1_CNTL (0x00000D48U)
111 #define SDL_VTM_TSENSE1_RESULT (0x00000D4CU)
112 #define SDL_VTM_TSENSE1_DATA0 (0x00000D50U)
113 #define SDL_VTM_TSENSE1_DATA1 (0x00000D54U)
114 #define SDL_VTM_TSENSE1_DATA2 (0x00000D58U)
115 #define SDL_VTM_TSENSE1_DATA3 (0x00000D5CU)
116 #define SDL_VTM_TSENSE1_ACCU (0x00000D60U)
117 #define SDL_VTM_TSENSE2_RESULT (0x00000D7CU)
118 #define SDL_VTM_TSENSE3_RESULT (0x00000DACU)
119 
120 /**************************************************************************
121 * Field Definition Macros
122 **************************************************************************/
123 
124 /* TSENSE_CFG */
125 
126 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_ENABLE_MASK (0x00000001U)
127 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_ENABLE_SHIFT (0x00000000U)
128 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_ENABLE_RESETVAL (0x00000000U)
129 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_ENABLE_MAX (0x00000001U)
130 
131 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_SENSOR_SEL_MASK (0x000000F0U)
132 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_SENSOR_SEL_SHIFT (0x00000004U)
133 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_SENSOR_SEL_RESETVAL (0x00000000U)
134 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_SENSOR_SEL_MAX (0x0000000FU)
135 
136 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_DELAY_MASK (0x00003F00U)
137 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_DELAY_SHIFT (0x00000008U)
138 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_DELAY_RESETVAL (0x00000000U)
139 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_DELAY_MAX (0x0000003FU)
140 
141 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_SNSR_MX_HIZ_MASK (0x00010000U)
142 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_SNSR_MX_HIZ_SHIFT (0x00000010U)
143 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_SNSR_MX_HIZ_RESETVAL (0x00000001U)
144 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_SNSR_MX_HIZ_MAX (0x00000001U)
145 
146 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_AIPOFF_MASK (0x00100000U)
147 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_AIPOFF_SHIFT (0x00000014U)
148 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_AIPOFF_RESETVAL (0x00000001U)
149 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_AIPOFF_MAX (0x00000001U)
150 
151 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_BGROFF_MASK (0x01000000U)
152 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_BGROFF_SHIFT (0x00000018U)
153 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_BGROFF_RESETVAL (0x00000001U)
154 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_BGROFF_MAX (0x00000001U)
155 
156 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_TMPSOFF_MASK (0x10000000U)
157 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_TMPSOFF_SHIFT (0x0000001CU)
158 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_TMPSOFF_RESETVAL (0x00000001U)
159 #define SDL_TOP_CTRL_TSENSE_CFG_TSENSE_CFG_TMPSOFF_MAX (0x00000001U)
160 
161 #define SDL_TOP_CTRL_TSENSE_CFG_RESETVAL (0x11110000U)
162 
163 /* TSENSE_STATUS */
164 
165 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_LOW_THRHLD_MASK (0x00000001U)
166 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_LOW_THRHLD_SHIFT (0x00000000U)
167 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_LOW_THRHLD_RESETVAL (0x00000000U)
168 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_LOW_THRHLD_MAX (0x00000001U)
169 
170 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_COLD_MASK (0x00000002U)
171 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_COLD_SHIFT (0x00000001U)
172 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_COLD_RESETVAL (0x00000000U)
173 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_COLD_MAX (0x00000001U)
174 
175 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_HOT_MASK (0x00000004U)
176 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_HOT_SHIFT (0x00000002U)
177 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_HOT_RESETVAL (0x00000000U)
178 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S0_HOT_MAX (0x00000001U)
179 
180 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_LOW_THRHLD_MASK (0x00000010U)
181 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_LOW_THRHLD_SHIFT (0x00000004U)
182 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_LOW_THRHLD_RESETVAL (0x00000000U)
183 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_LOW_THRHLD_MAX (0x00000001U)
184 
185 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_COLD_MASK (0x00000020U)
186 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_COLD_SHIFT (0x00000005U)
187 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_COLD_RESETVAL (0x00000000U)
188 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_COLD_MAX (0x00000001U)
189 
190 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_HOT_MASK (0x00000040U)
191 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_HOT_SHIFT (0x00000006U)
192 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_HOT_RESETVAL (0x00000000U)
193 #define SDL_TOP_CTRL_TSENSE_STATUS_TSENSE_STATUS_S1_HOT_MAX (0x00000001U)
194 
195 #define SDL_TOP_CTRL_TSENSE_STATUS_RESETVAL (0x00000000U)
196 
197 /* TSENSE_STATUS_RAW */
198 
199 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_LOW_THRHLD_MASK (0x00000001U)
200 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_LOW_THRHLD_SHIFT (0x00000000U)
201 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_LOW_THRHLD_RESETVAL (0x00000000U)
202 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_LOW_THRHLD_MAX (0x00000001U)
203 
204 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_COLD_MASK (0x00000002U)
205 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_COLD_SHIFT (0x00000001U)
206 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_COLD_RESETVAL (0x00000000U)
207 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_COLD_MAX (0x00000001U)
208 
209 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_HOT_MASK (0x00000004U)
210 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_HOT_SHIFT (0x00000002U)
211 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_HOT_RESETVAL (0x00000000U)
212 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S0_HOT_MAX (0x00000001U)
213 
214 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_LOW_THRHLD_MASK (0x00000010U)
215 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_LOW_THRHLD_SHIFT (0x00000004U)
216 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_LOW_THRHLD_RESETVAL (0x00000000U)
217 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_LOW_THRHLD_MAX (0x00000001U)
218 
219 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_COLD_MASK (0x00000020U)
220 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_COLD_SHIFT (0x00000005U)
221 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_COLD_RESETVAL (0x00000000U)
222 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_COLD_MAX (0x00000001U)
223 
224 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_HOT_MASK (0x00000040U)
225 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_HOT_SHIFT (0x00000006U)
226 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_HOT_RESETVAL (0x00000000U)
227 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_TSENSE_STATUS_RAW_S1_HOT_MAX (0x00000001U)
228 
229 #define SDL_TOP_CTRL_TSENSE_STATUS_RAW_RESETVAL (0x00000000U)
230 
231 /* TSENSE0_TSHUT */
232 
233 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_TSHUT_THRSHLD_COLD_MASK (0x000000FFU)
234 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_TSHUT_THRSHLD_COLD_SHIFT (0x00000000U)
235 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_TSHUT_THRSHLD_COLD_RESETVAL (0x00000000U)
236 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_TSHUT_THRSHLD_COLD_MAX (0x000000FFU)
237 
238 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_TSHUT_THRHLD_HOT_MASK (0x00FF0000U)
239 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_TSHUT_THRHLD_HOT_SHIFT (0x00000010U)
240 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_TSHUT_THRHLD_HOT_RESETVAL (0x00000000U)
241 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_TSHUT_THRHLD_HOT_MAX (0x000000FFU)
242 
243 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_EFUSE_OVERRIDE_MASK (0xE0000000U)
244 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_EFUSE_OVERRIDE_SHIFT (0x0000001DU)
245 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_EFUSE_OVERRIDE_RESETVAL (0x00000000U)
246 #define SDL_TOP_CTRL_TSENSE0_TSHUT_TSENSE0_TSHUT_EFUSE_OVERRIDE_MAX (0x00000007U)
247 
248 #define SDL_TOP_CTRL_TSENSE0_TSHUT_RESETVAL (0x00000000U)
249 
250 /* TSENSE0_ALERT */
251 
252 #define SDL_TOP_CTRL_TSENSE0_ALERT_TSENSE0_ALERT_ALERT_THRHLD_HOT_MASK (0x000000FFU)
253 #define SDL_TOP_CTRL_TSENSE0_ALERT_TSENSE0_ALERT_ALERT_THRHLD_HOT_SHIFT (0x00000000U)
254 #define SDL_TOP_CTRL_TSENSE0_ALERT_TSENSE0_ALERT_ALERT_THRHLD_HOT_RESETVAL (0x00000000U)
255 #define SDL_TOP_CTRL_TSENSE0_ALERT_TSENSE0_ALERT_ALERT_THRHLD_HOT_MAX (0x000000FFU)
256 
257 #define SDL_TOP_CTRL_TSENSE0_ALERT_TSENSE0_ALERT_ALERT_THRHLD_COLD_MASK (0x00FF0000U)
258 #define SDL_TOP_CTRL_TSENSE0_ALERT_TSENSE0_ALERT_ALERT_THRHLD_COLD_SHIFT (0x00000010U)
259 #define SDL_TOP_CTRL_TSENSE0_ALERT_TSENSE0_ALERT_ALERT_THRHLD_COLD_RESETVAL (0x00000000U)
260 #define SDL_TOP_CTRL_TSENSE0_ALERT_TSENSE0_ALERT_ALERT_THRHLD_COLD_MAX (0x000000FFU)
261 
262 #define SDL_TOP_CTRL_TSENSE0_ALERT_RESETVAL (0x00000000U)
263 
264 /* TSENSE0_CNTL */
265 
266 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_FIFO_CLEAR_MASK (0x00000001U)
267 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_FIFO_CLEAR_SHIFT (0x00000000U)
268 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_FIFO_CLEAR_RESETVAL (0x00000000U)
269 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_FIFO_CLEAR_MAX (0x00000001U)
270 
271 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_FIFO_FREEZE_MASK (0x00000010U)
272 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_FIFO_FREEZE_SHIFT (0x00000004U)
273 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_FIFO_FREEZE_RESETVAL (0x00000000U)
274 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_FIFO_FREEZE_MAX (0x00000001U)
275 
276 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_ACCU_CLEAR_MASK (0x00000100U)
277 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_ACCU_CLEAR_SHIFT (0x00000008U)
278 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_ACCU_CLEAR_RESETVAL (0x00000000U)
279 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_ACCU_CLEAR_MAX (0x00000001U)
280 
281 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_COLD_MASK (0x00010000U)
282 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_COLD_SHIFT (0x00000010U)
283 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_COLD_RESETVAL (0x00000000U)
284 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_COLD_MAX (0x00000001U)
285 
286 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_HOT_MASK (0x00100000U)
287 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_HOT_SHIFT (0x00000014U)
288 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_HOT_RESETVAL (0x00000001U)
289 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_HOT_MAX (0x00000001U)
290 
291 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_LOW_THRHLD_MASK (0x01000000U)
292 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_LOW_THRHLD_SHIFT (0x00000018U)
293 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_LOW_THRHLD_RESETVAL (0x00000000U)
294 #define SDL_TOP_CTRL_TSENSE0_CNTL_TSENSE0_CNTL_MASK_LOW_THRHLD_MAX (0x00000001U)
295 
296 #define SDL_TOP_CTRL_TSENSE0_CNTL_RESETVAL (0x00100000U)
297 
298 /* TSENSE0_RESULT */
299 
300 #define SDL_TOP_CTRL_TSENSE0_RESULT_TSENSE0_RESULT_DTEMP_MASK (0x000000FFU)
301 #define SDL_TOP_CTRL_TSENSE0_RESULT_TSENSE0_RESULT_DTEMP_SHIFT (0x00000000U)
302 #define SDL_TOP_CTRL_TSENSE0_RESULT_TSENSE0_RESULT_DTEMP_RESETVAL (0x000000FFU)
303 #define SDL_TOP_CTRL_TSENSE0_RESULT_TSENSE0_RESULT_DTEMP_MAX (0x000000FFU)
304 
305 #define SDL_TOP_CTRL_TSENSE0_RESULT_TSENSE0_RESULT_ECOZ_MASK (0x00010000U)
306 #define SDL_TOP_CTRL_TSENSE0_RESULT_TSENSE0_RESULT_ECOZ_SHIFT (0x00000010U)
307 #define SDL_TOP_CTRL_TSENSE0_RESULT_TSENSE0_RESULT_ECOZ_RESETVAL (0x00000000U)
308 #define SDL_TOP_CTRL_TSENSE0_RESULT_TSENSE0_RESULT_ECOZ_MAX (0x00000001U)
309 
310 #define SDL_TOP_CTRL_TSENSE0_RESULT_RESETVAL (0x000000FFU)
311 
312 /* TSENSE0_DATA0 */
313 
314 #define SDL_TOP_CTRL_TSENSE0_DATA0_TSENSE0_DATA0_DATA_MASK (0x000000FFU)
315 #define SDL_TOP_CTRL_TSENSE0_DATA0_TSENSE0_DATA0_DATA_SHIFT (0x00000000U)
316 #define SDL_TOP_CTRL_TSENSE0_DATA0_TSENSE0_DATA0_DATA_RESETVAL (0x000000FFU)
317 #define SDL_TOP_CTRL_TSENSE0_DATA0_TSENSE0_DATA0_DATA_MAX (0x000000FFU)
318 
319 #define SDL_TOP_CTRL_TSENSE0_DATA0_TSENSE0_DATA0_TAG_MASK (0xFFFFFF00U)
320 #define SDL_TOP_CTRL_TSENSE0_DATA0_TSENSE0_DATA0_TAG_SHIFT (0x00000008U)
321 #define SDL_TOP_CTRL_TSENSE0_DATA0_TSENSE0_DATA0_TAG_RESETVAL (0x00000000U)
322 #define SDL_TOP_CTRL_TSENSE0_DATA0_TSENSE0_DATA0_TAG_MAX (0x00FFFFFFU)
323 
324 #define SDL_TOP_CTRL_TSENSE0_DATA0_RESETVAL (0x000000FFU)
325 
326 /* TSENSE0_DATA1 */
327 
328 #define SDL_TOP_CTRL_TSENSE0_DATA1_TSENSE0_DATA1_DATA_MASK (0x000000FFU)
329 #define SDL_TOP_CTRL_TSENSE0_DATA1_TSENSE0_DATA1_DATA_SHIFT (0x00000000U)
330 #define SDL_TOP_CTRL_TSENSE0_DATA1_TSENSE0_DATA1_DATA_RESETVAL (0x00000000U)
331 #define SDL_TOP_CTRL_TSENSE0_DATA1_TSENSE0_DATA1_DATA_MAX (0x000000FFU)
332 
333 #define SDL_TOP_CTRL_TSENSE0_DATA1_TSENSE0_DATA1_TAG_MASK (0xFFFFFF00U)
334 #define SDL_TOP_CTRL_TSENSE0_DATA1_TSENSE0_DATA1_TAG_SHIFT (0x00000008U)
335 #define SDL_TOP_CTRL_TSENSE0_DATA1_TSENSE0_DATA1_TAG_RESETVAL (0x00000000U)
336 #define SDL_TOP_CTRL_TSENSE0_DATA1_TSENSE0_DATA1_TAG_MAX (0x00FFFFFFU)
337 
338 #define SDL_TOP_CTRL_TSENSE0_DATA1_RESETVAL (0x00000000U)
339 
340 /* TSENSE0_DATA2 */
341 
342 #define SDL_TOP_CTRL_TSENSE0_DATA2_TSENSE0_DATA2_DATA_MASK (0x000000FFU)
343 #define SDL_TOP_CTRL_TSENSE0_DATA2_TSENSE0_DATA2_DATA_SHIFT (0x00000000U)
344 #define SDL_TOP_CTRL_TSENSE0_DATA2_TSENSE0_DATA2_DATA_RESETVAL (0x00000000U)
345 #define SDL_TOP_CTRL_TSENSE0_DATA2_TSENSE0_DATA2_DATA_MAX (0x000000FFU)
346 
347 #define SDL_TOP_CTRL_TSENSE0_DATA2_TSENSE0_DATA2_TAG_MASK (0xFFFFFF00U)
348 #define SDL_TOP_CTRL_TSENSE0_DATA2_TSENSE0_DATA2_TAG_SHIFT (0x00000008U)
349 #define SDL_TOP_CTRL_TSENSE0_DATA2_TSENSE0_DATA2_TAG_RESETVAL (0x00000000U)
350 #define SDL_TOP_CTRL_TSENSE0_DATA2_TSENSE0_DATA2_TAG_MAX (0x00FFFFFFU)
351 
352 #define SDL_TOP_CTRL_TSENSE0_DATA2_RESETVAL (0x00000000U)
353 
354 /* TSENSE0_DATA3 */
355 
356 #define SDL_TOP_CTRL_TSENSE0_DATA3_TSENSE0_DATA3_DATA_MASK (0x000000FFU)
357 #define SDL_TOP_CTRL_TSENSE0_DATA3_TSENSE0_DATA3_DATA_SHIFT (0x00000000U)
358 #define SDL_TOP_CTRL_TSENSE0_DATA3_TSENSE0_DATA3_DATA_RESETVAL (0x00000000U)
359 #define SDL_TOP_CTRL_TSENSE0_DATA3_TSENSE0_DATA3_DATA_MAX (0x000000FFU)
360 
361 #define SDL_TOP_CTRL_TSENSE0_DATA3_TSENSE0_DATA3_TAG_MASK (0xFFFFFF00U)
362 #define SDL_TOP_CTRL_TSENSE0_DATA3_TSENSE0_DATA3_TAG_SHIFT (0x00000008U)
363 #define SDL_TOP_CTRL_TSENSE0_DATA3_TSENSE0_DATA3_TAG_RESETVAL (0x00000000U)
364 #define SDL_TOP_CTRL_TSENSE0_DATA3_TSENSE0_DATA3_TAG_MAX (0x00FFFFFFU)
365 
366 #define SDL_TOP_CTRL_TSENSE0_DATA3_RESETVAL (0x00000000U)
367 
368 /* TSENSE0_ACCU */
369 
370 #define SDL_TOP_CTRL_TSENSE0_ACCU_TSENSE0_ACCU_CUMUL_MASK (0xFFFFFFFFU)
371 #define SDL_TOP_CTRL_TSENSE0_ACCU_TSENSE0_ACCU_CUMUL_SHIFT (0x00000000U)
372 #define SDL_TOP_CTRL_TSENSE0_ACCU_TSENSE0_ACCU_CUMUL_RESETVAL (0x00000000U)
373 #define SDL_TOP_CTRL_TSENSE0_ACCU_TSENSE0_ACCU_CUMUL_MAX (0xFFFFFFFFU)
374 
375 #define SDL_TOP_CTRL_TSENSE0_ACCU_RESETVAL (0x00000000U)
376 
377 /* TSENSE1_TSHUT */
378 
379 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_TSHUT_THRSHLD_COLD_MASK (0x000000FFU)
380 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_TSHUT_THRSHLD_COLD_SHIFT (0x00000000U)
381 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_TSHUT_THRSHLD_COLD_RESETVAL (0x00000000U)
382 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_TSHUT_THRSHLD_COLD_MAX (0x000000FFU)
383 
384 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_TSHUT_THRHLD_HOT_MASK (0x00FF0000U)
385 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_TSHUT_THRHLD_HOT_SHIFT (0x00000010U)
386 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_TSHUT_THRHLD_HOT_RESETVAL (0x00000000U)
387 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_TSHUT_THRHLD_HOT_MAX (0x000000FFU)
388 
389 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_EFUSE_OVERRIDE_MASK (0xE0000000U)
390 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_EFUSE_OVERRIDE_SHIFT (0x0000001DU)
391 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_EFUSE_OVERRIDE_RESETVAL (0x00000000U)
392 #define SDL_TOP_CTRL_TSENSE1_TSHUT_TSENSE1_TSHUT_EFUSE_OVERRIDE_MAX (0x00000007U)
393 
394 #define SDL_TOP_CTRL_TSENSE1_TSHUT_RESETVAL (0x00000000U)
395 
396 /* TSENSE1_ALERT */
397 
398 #define SDL_TOP_CTRL_TSENSE1_ALERT_TSENSE1_ALERT_ALERT_THRHLD_HOT_MASK (0x000000FFU)
399 #define SDL_TOP_CTRL_TSENSE1_ALERT_TSENSE1_ALERT_ALERT_THRHLD_HOT_SHIFT (0x00000000U)
400 #define SDL_TOP_CTRL_TSENSE1_ALERT_TSENSE1_ALERT_ALERT_THRHLD_HOT_RESETVAL (0x00000000U)
401 #define SDL_TOP_CTRL_TSENSE1_ALERT_TSENSE1_ALERT_ALERT_THRHLD_HOT_MAX (0x000000FFU)
402 
403 #define SDL_TOP_CTRL_TSENSE1_ALERT_TSENSE1_ALERT_ALERT_THRHLD_COLD_MASK (0x00FF0000U)
404 #define SDL_TOP_CTRL_TSENSE1_ALERT_TSENSE1_ALERT_ALERT_THRHLD_COLD_SHIFT (0x00000010U)
405 #define SDL_TOP_CTRL_TSENSE1_ALERT_TSENSE1_ALERT_ALERT_THRHLD_COLD_RESETVAL (0x00000000U)
406 #define SDL_TOP_CTRL_TSENSE1_ALERT_TSENSE1_ALERT_ALERT_THRHLD_COLD_MAX (0x000000FFU)
407 
408 #define SDL_TOP_CTRL_TSENSE1_ALERT_RESETVAL (0x00000000U)
409 
410 /* TSENSE1_CNTL */
411 
412 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_FIFO_CLEAR_MASK (0x00000001U)
413 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_FIFO_CLEAR_SHIFT (0x00000000U)
414 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_FIFO_CLEAR_RESETVAL (0x00000000U)
415 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_FIFO_CLEAR_MAX (0x00000001U)
416 
417 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_FIFO_FREEZE_MASK (0x00000010U)
418 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_FIFO_FREEZE_SHIFT (0x00000004U)
419 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_FIFO_FREEZE_RESETVAL (0x00000000U)
420 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_FIFO_FREEZE_MAX (0x00000001U)
421 
422 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_ACCU_CLEAR_MASK (0x00000100U)
423 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_ACCU_CLEAR_SHIFT (0x00000008U)
424 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_ACCU_CLEAR_RESETVAL (0x00000000U)
425 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_ACCU_CLEAR_MAX (0x00000001U)
426 
427 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_COLD_MASK (0x00010000U)
428 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_COLD_SHIFT (0x00000010U)
429 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_COLD_RESETVAL (0x00000000U)
430 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_COLD_MAX (0x00000001U)
431 
432 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_HOT_MASK (0x00100000U)
433 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_HOT_SHIFT (0x00000014U)
434 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_HOT_RESETVAL (0x00000001U)
435 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_HOT_MAX (0x00000001U)
436 
437 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_LOW_THRHLD_MASK (0x01000000U)
438 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_LOW_THRHLD_SHIFT (0x00000018U)
439 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_LOW_THRHLD_RESETVAL (0x00000000U)
440 #define SDL_TOP_CTRL_TSENSE1_CNTL_TSENSE1_CNTL_MASK_LOW_THRHLD_MAX (0x00000001U)
441 
442 #define SDL_TOP_CTRL_TSENSE1_CNTL_RESETVAL (0x00100000U)
443 
444 /* TSENSE1_RESULT */
445 
446 #define SDL_TOP_CTRL_TSENSE1_RESULT_TSENSE1_RESULT_DTEMP_MASK (0x000000FFU)
447 #define SDL_TOP_CTRL_TSENSE1_RESULT_TSENSE1_RESULT_DTEMP_SHIFT (0x00000000U)
448 #define SDL_TOP_CTRL_TSENSE1_RESULT_TSENSE1_RESULT_DTEMP_RESETVAL (0x000000FFU)
449 #define SDL_TOP_CTRL_TSENSE1_RESULT_TSENSE1_RESULT_DTEMP_MAX (0x000000FFU)
450 
451 #define SDL_TOP_CTRL_TSENSE1_RESULT_TSENSE1_RESULT_ECOZ_MASK (0x00010000U)
452 #define SDL_TOP_CTRL_TSENSE1_RESULT_TSENSE1_RESULT_ECOZ_SHIFT (0x00000010U)
453 #define SDL_TOP_CTRL_TSENSE1_RESULT_TSENSE1_RESULT_ECOZ_RESETVAL (0x00000000U)
454 #define SDL_TOP_CTRL_TSENSE1_RESULT_TSENSE1_RESULT_ECOZ_MAX (0x00000001U)
455 
456 #define SDL_TOP_CTRL_TSENSE1_RESULT_RESETVAL (0x000000FFU)
457 
458 /* TSENSE1_DATA0 */
459 
460 #define SDL_TOP_CTRL_TSENSE1_DATA0_TSENSE1_DATA0_DATA_MASK (0x000000FFU)
461 #define SDL_TOP_CTRL_TSENSE1_DATA0_TSENSE1_DATA0_DATA_SHIFT (0x00000000U)
462 #define SDL_TOP_CTRL_TSENSE1_DATA0_TSENSE1_DATA0_DATA_RESETVAL (0x000000FFU)
463 #define SDL_TOP_CTRL_TSENSE1_DATA0_TSENSE1_DATA0_DATA_MAX (0x000000FFU)
464 
465 #define SDL_TOP_CTRL_TSENSE1_DATA0_TSENSE1_DATA0_TAG_MASK (0xFFFFFF00U)
466 #define SDL_TOP_CTRL_TSENSE1_DATA0_TSENSE1_DATA0_TAG_SHIFT (0x00000008U)
467 #define SDL_TOP_CTRL_TSENSE1_DATA0_TSENSE1_DATA0_TAG_RESETVAL (0x00000000U)
468 #define SDL_TOP_CTRL_TSENSE1_DATA0_TSENSE1_DATA0_TAG_MAX (0x00FFFFFFU)
469 
470 #define SDL_TOP_CTRL_TSENSE1_DATA0_RESETVAL (0x000000FFU)
471 
472 /* TSENSE1_DATA1 */
473 
474 #define SDL_TOP_CTRL_TSENSE1_DATA1_TSENSE1_DATA1_DATA_MASK (0x000000FFU)
475 #define SDL_TOP_CTRL_TSENSE1_DATA1_TSENSE1_DATA1_DATA_SHIFT (0x00000000U)
476 #define SDL_TOP_CTRL_TSENSE1_DATA1_TSENSE1_DATA1_DATA_RESETVAL (0x00000000U)
477 #define SDL_TOP_CTRL_TSENSE1_DATA1_TSENSE1_DATA1_DATA_MAX (0x000000FFU)
478 
479 #define SDL_TOP_CTRL_TSENSE1_DATA1_TSENSE1_DATA1_TAG_MASK (0xFFFFFF00U)
480 #define SDL_TOP_CTRL_TSENSE1_DATA1_TSENSE1_DATA1_TAG_SHIFT (0x00000008U)
481 #define SDL_TOP_CTRL_TSENSE1_DATA1_TSENSE1_DATA1_TAG_RESETVAL (0x00000000U)
482 #define SDL_TOP_CTRL_TSENSE1_DATA1_TSENSE1_DATA1_TAG_MAX (0x00FFFFFFU)
483 
484 #define SDL_TOP_CTRL_TSENSE1_DATA1_RESETVAL (0x00000000U)
485 
486 /* TSENSE1_DATA2 */
487 
488 #define SDL_TOP_CTRL_TSENSE1_DATA2_TSENSE1_DATA2_DATA_MASK (0x000000FFU)
489 #define SDL_TOP_CTRL_TSENSE1_DATA2_TSENSE1_DATA2_DATA_SHIFT (0x00000000U)
490 #define SDL_TOP_CTRL_TSENSE1_DATA2_TSENSE1_DATA2_DATA_RESETVAL (0x00000000U)
491 #define SDL_TOP_CTRL_TSENSE1_DATA2_TSENSE1_DATA2_DATA_MAX (0x000000FFU)
492 
493 #define SDL_TOP_CTRL_TSENSE1_DATA2_TSENSE1_DATA2_TAG_MASK (0xFFFFFF00U)
494 #define SDL_TOP_CTRL_TSENSE1_DATA2_TSENSE1_DATA2_TAG_SHIFT (0x00000008U)
495 #define SDL_TOP_CTRL_TSENSE1_DATA2_TSENSE1_DATA2_TAG_RESETVAL (0x00000000U)
496 #define SDL_TOP_CTRL_TSENSE1_DATA2_TSENSE1_DATA2_TAG_MAX (0x00FFFFFFU)
497 
498 #define SDL_TOP_CTRL_TSENSE1_DATA2_RESETVAL (0x00000000U)
499 
500 /* TSENSE1_DATA3 */
501 
502 #define SDL_TOP_CTRL_TSENSE1_DATA3_TSENSE1_DATA3_DATA_MASK (0x000000FFU)
503 #define SDL_TOP_CTRL_TSENSE1_DATA3_TSENSE1_DATA3_DATA_SHIFT (0x00000000U)
504 #define SDL_TOP_CTRL_TSENSE1_DATA3_TSENSE1_DATA3_DATA_RESETVAL (0x00000000U)
505 #define SDL_TOP_CTRL_TSENSE1_DATA3_TSENSE1_DATA3_DATA_MAX (0x000000FFU)
506 
507 #define SDL_TOP_CTRL_TSENSE1_DATA3_TSENSE1_DATA3_TAG_MASK (0xFFFFFF00U)
508 #define SDL_TOP_CTRL_TSENSE1_DATA3_TSENSE1_DATA3_TAG_SHIFT (0x00000008U)
509 #define SDL_TOP_CTRL_TSENSE1_DATA3_TSENSE1_DATA3_TAG_RESETVAL (0x00000000U)
510 #define SDL_TOP_CTRL_TSENSE1_DATA3_TSENSE1_DATA3_TAG_MAX (0x00FFFFFFU)
511 
512 #define SDL_TOP_CTRL_TSENSE1_DATA3_RESETVAL (0x00000000U)
513 
514 /* TSENSE1_ACCU */
515 
516 #define SDL_TOP_CTRL_TSENSE1_ACCU_TSENSE1_ACCU_CUMUL_MASK (0xFFFFFFFFU)
517 #define SDL_TOP_CTRL_TSENSE1_ACCU_TSENSE1_ACCU_CUMUL_SHIFT (0x00000000U)
518 #define SDL_TOP_CTRL_TSENSE1_ACCU_TSENSE1_ACCU_CUMUL_RESETVAL (0x00000000U)
519 #define SDL_TOP_CTRL_TSENSE1_ACCU_TSENSE1_ACCU_CUMUL_MAX (0xFFFFFFFFU)
520 
521 #define SDL_TOP_CTRL_TSENSE1_ACCU_RESETVAL (0x00000000U)
522 
523 /* TSENSE2_RESULT */
524 
525 #define SDL_TOP_CTRL_TSENSE2_RESULT_TSENSE2_RESULT_DTEMP_MASK (0x000000FFU)
526 #define SDL_TOP_CTRL_TSENSE2_RESULT_TSENSE2_RESULT_DTEMP_SHIFT (0x00000000U)
527 #define SDL_TOP_CTRL_TSENSE2_RESULT_TSENSE2_RESULT_DTEMP_RESETVAL (0x00000000U)
528 #define SDL_TOP_CTRL_TSENSE2_RESULT_TSENSE2_RESULT_DTEMP_MAX (0x000000FFU)
529 
530 #define SDL_TOP_CTRL_TSENSE2_RESULT_TSENSE2_RESULT_ECOZ_MASK (0x00010000U)
531 #define SDL_TOP_CTRL_TSENSE2_RESULT_TSENSE2_RESULT_ECOZ_SHIFT (0x00000010U)
532 #define SDL_TOP_CTRL_TSENSE2_RESULT_TSENSE2_RESULT_ECOZ_RESETVAL (0x00000000U)
533 #define SDL_TOP_CTRL_TSENSE2_RESULT_TSENSE2_RESULT_ECOZ_MAX (0x00000001U)
534 
535 #define SDL_TOP_CTRL_TSENSE2_RESULT_RESETVAL (0x00000000U)
536 
537 /* TSENSE3_RESULT */
538 
539 #define SDL_TOP_CTRL_TSENSE3_RESULT_TSENSE3_RESULT_DTEMP_MASK (0x000000FFU)
540 #define SDL_TOP_CTRL_TSENSE3_RESULT_TSENSE3_RESULT_DTEMP_SHIFT (0x00000000U)
541 #define SDL_TOP_CTRL_TSENSE3_RESULT_TSENSE3_RESULT_DTEMP_RESETVAL (0x00000000U)
542 #define SDL_TOP_CTRL_TSENSE3_RESULT_TSENSE3_RESULT_DTEMP_MAX (0x000000FFU)
543 
544 #define SDL_TOP_CTRL_TSENSE3_RESULT_TSENSE3_RESULT_ECOZ_MASK (0x00010000U)
545 #define SDL_TOP_CTRL_TSENSE3_RESULT_TSENSE3_RESULT_ECOZ_SHIFT (0x00000010U)
546 #define SDL_TOP_CTRL_TSENSE3_RESULT_TSENSE3_RESULT_ECOZ_RESETVAL (0x00000000U)
547 #define SDL_TOP_CTRL_TSENSE3_RESULT_TSENSE3_RESULT_ECOZ_MAX (0x00000001U)
548 
549 #define SDL_TOP_CTRL_TSENSE3_RESULT_RESETVAL (0x00000000U)
550 
551 #ifdef __cplusplus
552 }
553 #endif
554 #endif
SDL_VTM_cfg1Regs::TSENSE1_DATA1
volatile uint32_t TSENSE1_DATA1
Definition: sdlr_vtm.h:81
SDL_VTM_cfg1Regs
Definition: sdlr_vtm.h:61
SDL_VTM_cfg1Regs::TSENSE0_ALERT
volatile uint32_t TSENSE0_ALERT
Definition: sdlr_vtm.h:67
SDL_VTM_cfg1Regs::TSENSE0_TSHUT
volatile uint32_t TSENSE0_TSHUT
Definition: sdlr_vtm.h:66
SDL_VTM_cfg1Regs::TSENSE1_TSHUT
volatile uint32_t TSENSE1_TSHUT
Definition: sdlr_vtm.h:76
SDL_VTM_cfg1Regs::TSENSE0_ACCU
volatile uint32_t TSENSE0_ACCU
Definition: sdlr_vtm.h:74
SDL_VTM_cfg1Regs::TSENSE2_RESULT
volatile uint32_t TSENSE2_RESULT
Definition: sdlr_vtm.h:86
SDL_VTM_cfg1Regs::TSENSE0_DATA2
volatile uint32_t TSENSE0_DATA2
Definition: sdlr_vtm.h:72
SDL_VTM_cfg1Regs::TSENSE0_DATA3
volatile uint32_t TSENSE0_DATA3
Definition: sdlr_vtm.h:73
SDL_VTM_cfg1Regs::TSENSE1_ALERT
volatile uint32_t TSENSE1_ALERT
Definition: sdlr_vtm.h:77
SDL_VTM_cfg1Regs::TSENSE1_ACCU
volatile uint32_t TSENSE1_ACCU
Definition: sdlr_vtm.h:84
SDL_VTM_cfg1Regs::TSENSE_STATUS
volatile uint32_t TSENSE_STATUS
Definition: sdlr_vtm.h:63
SDL_VTM_cfg1Regs::TSENSE_CFG
volatile uint32_t TSENSE_CFG
Definition: sdlr_vtm.h:62
SDL_VTM_cfg1Regs::TSENSE0_DATA0
volatile uint32_t TSENSE0_DATA0
Definition: sdlr_vtm.h:70
SDL_VTM_cfg1Regs::TSENSE0_RESULT
volatile uint32_t TSENSE0_RESULT
Definition: sdlr_vtm.h:69
SDL_VTM_cfg1Regs::TSENSE1_DATA3
volatile uint32_t TSENSE1_DATA3
Definition: sdlr_vtm.h:83
SDL_VTM_cfg1Regs::TSENSE1_RESULT
volatile uint32_t TSENSE1_RESULT
Definition: sdlr_vtm.h:79
SDL_VTM_cfg1Regs::TSENSE0_CNTL
volatile uint32_t TSENSE0_CNTL
Definition: sdlr_vtm.h:68
SDL_VTM_cfg1Regs::TSENSE_STATUS_RAW
volatile uint32_t TSENSE_STATUS_RAW
Definition: sdlr_vtm.h:64
SDL_VTM_cfg1Regs::TSENSE1_DATA2
volatile uint32_t TSENSE1_DATA2
Definition: sdlr_vtm.h:82
SDL_VTM_cfg1Regs::TSENSE3_RESULT
volatile uint32_t TSENSE3_RESULT
Definition: sdlr_vtm.h:88
SDL_VTM_cfg1Regs::TSENSE1_CNTL
volatile uint32_t TSENSE1_CNTL
Definition: sdlr_vtm.h:78
SDL_VTM_cfg1Regs::TSENSE0_DATA1
volatile uint32_t TSENSE0_DATA1
Definition: sdlr_vtm.h:71
SDL_VTM_cfg1Regs::TSENSE1_DATA0
volatile uint32_t TSENSE1_DATA0
Definition: sdlr_vtm.h:80