This Header file contains enumerations, structure definitions and function declarations for SDL ECC interface.
Sub Modules | |
ECC_AGGR Data Structures | |
ECC_AGGR Enumerated Data Types | |
ECC_AGGR Functions | |
ECC_AGGR Macros | |
Files | |
file | sdl_ecc.h |
Header file contains enumerations, structure definitions and function. | |
file | sdl_ecc_soc.h |
Header file contains MemEntries, RamIdTables, aggrTables and aggrBaseAddressTable. | |
Typedefs | |
typedef void(* | SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address) |
typedef void(* | SDL_ECC_VIMDEDVector_t) (void) |
#define SDL_ECC_WIDTH_UNDEFINED 0x1 |
#define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U) |
#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U) |
#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U) |
#define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U) |
#define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U) |
#define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (10U) |
#define SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (5U) |
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U) |
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U) |
#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U) |
#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U) |
#define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U) |
#define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U) |
#define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U) |
#define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U) |
#define SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U) |
#define SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U) |
#define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U) |
#define SDL_ECC_Base_Address_TOTAL_ENTRIES (18U) |
#define SDL_CPSW0_ECC_U_BASE (SDL_CPSW0_U_BASE + 0x3f000u) |
#define SDL_OSPI_ECC_U_BASE (0x53807000u) |
#define SDL_FOTA_ECC_U_BASE (0x5380F000u) |
#define SDL_R5FSS0_CORE0_TCM_ERR_STATUS (0x50D18104U) |
#define SDL_R5FSS0_CORE0_TCM_ERR_STATUS_RAW (0x50D18108U) |
#define SDL_R5SS0_TCM_ADDRPARITY_ERRFORCE (0x50D1813CU) |
#define SDL_R5FSS0_CORE1_TCM_ERR_STATUS (0x50D18114U) |
#define SDL_R5FSS0_CORE1_TCM_ERR_STATUS_RAW (0x50D18118U) |
#define SDL_R5FSS1_CORE0_TCM_ERR_STATUS (0x50D18144U) |
#define SDL_R5FSS1_CORE0_TCM_ERR_STATUS_RAW (0x50D18148U) |
#define SDL_R5SS1_TCM_ADDRPARITY_ERRFORCE (0x50D1817CU) |
#define SDL_R5FSS1_CORE1_TCM_ERR_STATUS (0x50D18154U) |
#define SDL_R5FSS1_CORE1_TCM_ERR_STATUS_RAW (0x50D18158U) |
#define SDL_R5FSS0_CORE0_TPCC0_PARITY_CTRL (0x50D18180U) |
#define SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS (0x50D18184U) |
#define SDL_TPCC0_ERRAGG_STATUS (0x50D18004U) |
#define SDL_TPCC0_ERRAGG_MASK (0x50D18000U) |
#define SDL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL (0x50D18188U) |
#define SDL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL (0x50D18190U) |
#define SDL_TMU_R5SS1_CORE0_ROM_PARITY_CTRL (0x50D18198U) |
#define SDL_TMU_R5SS1_CORE1_ROM_PARITY_CTRL (0x50D181A0U) |
#define SDL_TMU0_ROM_PARITY_EN (0x1U) |
#define SDL_TMU0_ROM_PARITY_FORCE_ERR (0x2U) |
#define SDL_TMU0_ROM_PARITY_ERR_CLR (0x10000U) |
#define SDL_PARAM_REG_1 (SDL_PARAM_REG_SET0 + 0x20U) |
#define SDL_PARAM_REG_2 (SDL_PARAM_REG_SET0 + 0x30U) |
typedef void(* SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address) |
/brief Format of ECC error Call back function
typedef void(* SDL_ECC_VIMDEDVector_t) (void) |
/brief Format of VIM DED vector function
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
|
static |
SDL_ecc_aggrRegs* SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX] |
|
static |