Introduction

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DCC Operation Mode

typedef uint32_t	SDL_DCC_mode
	Enum to select the DCC Operation Mode. More...

#define	SDL_DCC_MODE_SINGLE_SHOT (DCC_DCCGCTRL_SINGLESHOT_MODE)

#define	SDL_DCC_MODE_CONTINUOUS (DCC_DCCGCTRL_SINGLESHOT_DISABLE)

DCC Clock source of COUNT0

typedef uint32_t	SDL_DCC_clkSrc0
	Enum to select the COUNT0 clock source. More...

#define	SDL_DCC_CLK0_SRC_CLOCK0_0 (DCC_DCCCLKSRC0_CLKSRC0_0)

#define	SDL_DCC_CLK0_SRC_CLOCK0_1 (DCC_DCCCLKSRC0_CLKSRC0_1)

#define	SDL_DCC_CLK0_SRC_CLOCK0_2 (DCC_DCCCLKSRC0_CLKSRC0_2)

DCC Clock source of COUNT1

typedef uint32_t	SDL_DCC_clkSrc1
	Enum to select the COUNT1 clock source. More...

#define	SDL_DCC_CLK1_SRC_CLOCKSRC0 (DCC_DCCCLKSRC1_CLKSRC_0)

#define	SDL_DCC_CLK1_SRC_CLOCKSRC1 (DCC_DCCCLKSRC1_CLKSRC_1)

#define	SDL_DCC_CLK1_SRC_CLOCKSRC2 (DCC_DCCCLKSRC1_CLKSRC_2)

#define	SDL_DCC_CLK1_SRC_CLOCKSRC3 (DCC_DCCCLKSRC1_CLKSRC_3)

#define	SDL_DCC_CLK1_SRC_CLOCKSRC4 (DCC_DCCCLKSRC1_CLKSRC_4)

#define	SDL_DCC_CLK1_SRC_CLOCKSRC5 (DCC_DCCCLKSRC1_CLKSRC_5)

#define	SDL_DCC_CLK1_SRC_CLOCKSRC6 (DCC_DCCCLKSRC1_CLKSRC_6)

#define	SDL_DCC_CLK1_SRC_CLOCKSRC7 (DCC_DCCCLKSRC1_CLKSRC_7)

#define	SDL_DCC_CLK1_SRC_FICLK (SDL_DCC2_DCCCLKSRC1_CLKSRC_OTHER)

DCC Interrupt type

typedef uint32_t	SDL_DCC_intrType
	Enum for DCC interrupts. More...

#define	SDL_DCC_INTERRUPT_ERR (0x0U)

#define	SDL_DCC_INTERRUPT_DONE (0x1U)

Macro Definition Documentation

◆ SDL_DCC_MODE_SINGLE_SHOT

#define SDL_DCC_MODE_SINGLE_SHOT (DCC_DCCGCTRL_SINGLESHOT_MODE)

Stop counting when counter0 and valid0 both reach zero Stop counting when counter1 reaches zero

◆ SDL_DCC_MODE_CONTINUOUS

#define SDL_DCC_MODE_CONTINUOUS (DCC_DCCGCTRL_SINGLESHOT_DISABLE)

Continuously repeat (until error)

◆ SDL_DCC_CLK0_SRC_CLOCK0_0

#define SDL_DCC_CLK0_SRC_CLOCK0_0 (DCC_DCCCLKSRC0_CLKSRC0_0)

SYS_CLK1 is selected as source for COUNT0

◆ SDL_DCC_CLK0_SRC_CLOCK0_1

#define SDL_DCC_CLK0_SRC_CLOCK0_1 (DCC_DCCCLKSRC0_CLKSRC0_1)

SYS_CLK2 is selected as source for COUNT0

◆ SDL_DCC_CLK0_SRC_CLOCK0_2

#define SDL_DCC_CLK0_SRC_CLOCK0_2 (DCC_DCCCLKSRC0_CLKSRC0_2)

XREF_CLK is selected as source for COUNT0

◆ SDL_DCC_CLK1_SRC_CLOCKSRC0

#define SDL_DCC_CLK1_SRC_CLOCKSRC0 (DCC_DCCCLKSRC1_CLKSRC_0)

TEST_CLK0 is selected as source for COUNT1

◆ SDL_DCC_CLK1_SRC_CLOCKSRC1

#define SDL_DCC_CLK1_SRC_CLOCKSRC1 (DCC_DCCCLKSRC1_CLKSRC_1)

TEST_CLK1 is selected as source for COUNT1

◆ SDL_DCC_CLK1_SRC_CLOCKSRC2

#define SDL_DCC_CLK1_SRC_CLOCKSRC2 (DCC_DCCCLKSRC1_CLKSRC_2)

TEST_CLK2 is selected as source for COUNT1

◆ SDL_DCC_CLK1_SRC_CLOCKSRC3

#define SDL_DCC_CLK1_SRC_CLOCKSRC3 (DCC_DCCCLKSRC1_CLKSRC_3)

TEST_CLK3 is selected as source for COUNT1

◆ SDL_DCC_CLK1_SRC_CLOCKSRC4

#define SDL_DCC_CLK1_SRC_CLOCKSRC4 (DCC_DCCCLKSRC1_CLKSRC_4)

TEST_CLK4 is selected as source for COUNT1

◆ SDL_DCC_CLK1_SRC_CLOCKSRC5

#define SDL_DCC_CLK1_SRC_CLOCKSRC5 (DCC_DCCCLKSRC1_CLKSRC_5)

TEST_CLK5 is selected as source for COUNT1

◆ SDL_DCC_CLK1_SRC_CLOCKSRC6

#define SDL_DCC_CLK1_SRC_CLOCKSRC6 (DCC_DCCCLKSRC1_CLKSRC_6)

TEST_CLK6 is selected as source for COUNT1

◆ SDL_DCC_CLK1_SRC_CLOCKSRC7

#define SDL_DCC_CLK1_SRC_CLOCKSRC7 (DCC_DCCCLKSRC1_CLKSRC_7)

TEST_CLK7 is selected as source for COUNT1

◆ SDL_DCC_CLK1_SRC_FICLK

#define SDL_DCC_CLK1_SRC_FICLK (SDL_DCC2_DCCCLKSRC1_CLKSRC_OTHER)

OTHER_CLK is selected as source for COUNT1

◆ SDL_DCC_INTERRUPT_ERR

#define SDL_DCC_INTERRUPT_ERR (0x0U)

The error signal

◆ SDL_DCC_INTERRUPT_DONE

#define SDL_DCC_INTERRUPT_DONE (0x1U)

Done interrupt signal

Typedef Documentation

◆ SDL_DCC_mode

typedef uint32_t SDL_DCC_mode

Enum to select the DCC Operation Mode.

    DCC can either operate in single shot or continuous mode.

◆ SDL_DCC_clkSrc0

typedef uint32_t SDL_DCC_clkSrc0

Enum to select the COUNT0 clock source.

◆ SDL_DCC_clkSrc1

typedef uint32_t SDL_DCC_clkSrc1

Enum to select the COUNT1 clock source.

◆ SDL_DCC_intrType

typedef uint32_t SDL_DCC_intrType

Enum for DCC interrupts.