Macros
#define	SIPC_MSG_SIZE (13u)
	SIPC message size in bytes each element of queue will be of this size. More...

#define	INTR_CFG_NUM_MAX (1u)

#define	HSM_SOC_CTRL_U_BASE (0x40000000U)

#define	HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK (0x00000048U)

#define	HSM_SOC_CTRL_HSM_MBOX_READ_DONE (0x0000004CU)

#define	R5FSS0_0_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE_ACK)

#define	R5FSS0_0_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE)

#define	R5FSS0_1_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE_ACK)

#define	R5FSS0_1_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE)

#define	R5FSS1_0_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE_ACK)

#define	R5FSS1_0_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE)

#define	R5FSS1_1_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE_ACK)

#define	R5FSS1_1_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE)

#define	HSM0_0_MBOX_READ_DONE_ACK (HSM_SOC_CTRL_U_BASE + HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK)

#define	HSM0_0_MBOX_READ_DONE (HSM_SOC_CTRL_U_BASE + HSM_SOC_CTRL_HSM_MBOX_READ_DONE)

#define	R5FSS0_0_MBOX_WRITE_PROC_BIT_POS ( 0U)

#define	R5FSS0_1_MBOX_WRITE_PROC_BIT_POS ( 4U)

#define	R5FSS1_0_MBOX_WRITE_PROC_BIT_POS ( 8U)

#define	R5FSS1_1_MBOX_WRITE_PROC_BIT_POS ( 12U)

#define	HSM0_0_MBOX_WRITE_PROC_BIT_POS ( 6U)

#define	R5FSS0_0_MBOX_READ_PROC_BIT_POS ( 0U)

#define	R5FSS0_1_MBOX_READ_PROC_BIT_POS ( 4U)

#define	R5FSS1_0_MBOX_READ_PROC_BIT_POS ( 8U)

#define	R5FSS1_1_MBOX_READ_PROC_BIT_POS (12U)

#define	HSM0_0_MBOX_READ_PROC_BIT_POS (24U)

#define	R5FSS0_0_MBOX_READ_ACK_INTR ( 137U)

#define	R5FSS0_1_MBOX_READ_ACK_INTR ( 137U)

#define	R5FSS1_0_MBOX_READ_ACK_INTR ( 137U)

#define	R5FSS1_1_MBOX_READ_ACK_INTR ( 137U)

#define	HSM0_0_MBOX_READ_ACK_INTR ( 56U )

#define	CORE_ID_R5FSS0_0 (0U)

#define	CORE_ID_R5FSS0_1 (1U)

#define	CORE_ID_R5FSS1_0 (2U)

#define	CORE_ID_R5FSS1_1 (3U)

#define	CORE_ID_HSM0_0 (4U)

#define	CORE_ID_MAX (5U)

#define	CORE_INDEX_SEC_MASTER_0 (0U)

#define	CORE_INDEX_SEC_MASTER_1 (1U)

#define	CORE_INDEX_HSM (2U)

#define	MAX_SEC_CORES_WITH_HSM (3U)

#define	SIPC_CLIENT_ID_MAX (2U)

#define	SELF_CORE_ID (CORE_ID_HSM0_0)

#define	SIPC_BOOT_NOTIFY_CLIENT_ID (0U)

Typedefs
typedef uint32_t	SIPC_coreId
	Core Ids to identify different cores. More...

typedef uint32_t	SIPC_SecCoreId
	Secure host Id to identify different secure hosts. Max number of secure host on AM263x is 2. More...

Macro Definition Documentation

◆ SIPC_MSG_SIZE

#define SIPC_MSG_SIZE (13u)

SIPC message size in bytes each element of queue will be of this size.

◆ INTR_CFG_NUM_MAX

#define INTR_CFG_NUM_MAX (1u)

◆ HSM_SOC_CTRL_U_BASE

#define HSM_SOC_CTRL_U_BASE (0x40000000U)

◆ HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK

#define HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK (0x00000048U)

◆ HSM_SOC_CTRL_HSM_MBOX_READ_DONE

#define HSM_SOC_CTRL_HSM_MBOX_READ_DONE (0x0000004CU)

◆ R5FSS0_0_MBOX_READ_DONE_ACK

#define R5FSS0_0_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE_ACK)

◆ R5FSS0_0_MBOX_READ_DONE

#define R5FSS0_0_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE)

◆ R5FSS0_1_MBOX_READ_DONE_ACK

#define R5FSS0_1_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE_ACK)

◆ R5FSS0_1_MBOX_READ_DONE

#define R5FSS0_1_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE)

◆ R5FSS1_0_MBOX_READ_DONE_ACK

#define R5FSS1_0_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE_ACK)

◆ R5FSS1_0_MBOX_READ_DONE

#define R5FSS1_0_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE)

◆ R5FSS1_1_MBOX_READ_DONE_ACK

#define R5FSS1_1_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE_ACK)

◆ R5FSS1_1_MBOX_READ_DONE

#define R5FSS1_1_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE)

◆ HSM0_0_MBOX_READ_DONE_ACK

#define HSM0_0_MBOX_READ_DONE_ACK (HSM_SOC_CTRL_U_BASE + HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK)

◆ HSM0_0_MBOX_READ_DONE

#define HSM0_0_MBOX_READ_DONE (HSM_SOC_CTRL_U_BASE + HSM_SOC_CTRL_HSM_MBOX_READ_DONE)

◆ R5FSS0_0_MBOX_WRITE_PROC_BIT_POS

#define R5FSS0_0_MBOX_WRITE_PROC_BIT_POS ( 0U)

◆ R5FSS0_1_MBOX_WRITE_PROC_BIT_POS

#define R5FSS0_1_MBOX_WRITE_PROC_BIT_POS ( 4U)

◆ R5FSS1_0_MBOX_WRITE_PROC_BIT_POS

#define R5FSS1_0_MBOX_WRITE_PROC_BIT_POS ( 8U)

◆ R5FSS1_1_MBOX_WRITE_PROC_BIT_POS

#define R5FSS1_1_MBOX_WRITE_PROC_BIT_POS ( 12U)

◆ HSM0_0_MBOX_WRITE_PROC_BIT_POS

#define HSM0_0_MBOX_WRITE_PROC_BIT_POS ( 6U)

◆ R5FSS0_0_MBOX_READ_PROC_BIT_POS

#define R5FSS0_0_MBOX_READ_PROC_BIT_POS ( 0U)

◆ R5FSS0_1_MBOX_READ_PROC_BIT_POS

#define R5FSS0_1_MBOX_READ_PROC_BIT_POS ( 4U)

◆ R5FSS1_0_MBOX_READ_PROC_BIT_POS

#define R5FSS1_0_MBOX_READ_PROC_BIT_POS ( 8U)

◆ R5FSS1_1_MBOX_READ_PROC_BIT_POS

#define R5FSS1_1_MBOX_READ_PROC_BIT_POS (12U)

◆ HSM0_0_MBOX_READ_PROC_BIT_POS

#define HSM0_0_MBOX_READ_PROC_BIT_POS (24U)

◆ R5FSS0_0_MBOX_READ_ACK_INTR

#define R5FSS0_0_MBOX_READ_ACK_INTR ( 137U)

◆ R5FSS0_1_MBOX_READ_ACK_INTR

#define R5FSS0_1_MBOX_READ_ACK_INTR ( 137U)

◆ R5FSS1_0_MBOX_READ_ACK_INTR

#define R5FSS1_0_MBOX_READ_ACK_INTR ( 137U)

◆ R5FSS1_1_MBOX_READ_ACK_INTR

#define R5FSS1_1_MBOX_READ_ACK_INTR ( 137U)

◆ HSM0_0_MBOX_READ_ACK_INTR

#define HSM0_0_MBOX_READ_ACK_INTR ( 56U )

◆ CORE_ID_R5FSS0_0

#define CORE_ID_R5FSS0_0 (0U)

◆ CORE_ID_R5FSS0_1

#define CORE_ID_R5FSS0_1 (1U)

◆ CORE_ID_R5FSS1_0

#define CORE_ID_R5FSS1_0 (2U)

◆ CORE_ID_R5FSS1_1

#define CORE_ID_R5FSS1_1 (3U)

◆ CORE_ID_HSM0_0

#define CORE_ID_HSM0_0 (4U)

◆ CORE_ID_MAX

#define CORE_ID_MAX (5U)

◆ CORE_INDEX_SEC_MASTER_0

#define CORE_INDEX_SEC_MASTER_0 (0U)

◆ CORE_INDEX_SEC_MASTER_1

#define CORE_INDEX_SEC_MASTER_1 (1U)

◆ CORE_INDEX_HSM

#define CORE_INDEX_HSM (2U)

◆ MAX_SEC_CORES_WITH_HSM

#define MAX_SEC_CORES_WITH_HSM (3U)

◆ SIPC_CLIENT_ID_MAX

#define SIPC_CLIENT_ID_MAX (2U)

◆ SELF_CORE_ID

#define SELF_CORE_ID (CORE_ID_HSM0_0)

◆ SIPC_BOOT_NOTIFY_CLIENT_ID

#define SIPC_BOOT_NOTIFY_CLIENT_ID (0U)

Macros

Typedefs