sdl_ecc_soc.h File Reference

Introduction

Header file contains MemEntries, RamIdTables, aggrTables and aggrBaseAddressTable.

declarations for SDL ECC interface.

Go to the source code of this file.

Macros
#define	SDL_ECC_WIDTH_UNDEFINED   0x1
#define	SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (6U)
#define	SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)
#define	SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)
#define	SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (10U)
#define	SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)
#define	SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)
#define	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ECC_Base_Address_TOTAL_ENTRIES   (12U)
#define	SDL_CPSW0_ECC_U_BASE   (SDL_CPSW0_U_BASE + 0x3f000u)
#define	SDL_OSPI_ECC_U_BASE   (0x53807000u)
#define	SDL_FOTA_ECC_U_BASE   (0x5380F000u)
#define	SDL_R5FSS0_CORE0_TCM_ERR_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS)
#define	SDL_R5FSS0_CORE0_TCM_ERR_STATUS_RAW   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW)
#define	SDL_R5SS0_TCM_ADDRPARITY_ERRFORCE   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_TCM_ADDRPARITY_ERRFORCE)
#define	SDL_R5FSS0_CORE1_TCM_ERR_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS)
#define	SDL_R5FSS0_CORE1_TCM_ERR_STATUS_RAW   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW)
#define	SDL_R5FSS0_CORE0_TPCC0_PARITY_CTRL   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_PARITY_CTRL)
#define	SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_PARITY_STATUS)
#define	SDL_TPCC0_ERRAGG_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_ERRAGG_STATUS)
#define	SDL_TPCC0_ERRAGG_MASK   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_ERRAGG_MASK)
#define	SDL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL)
#define	SDL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL)
#define	SDL_TMU0_ROM_PARITY_EN   (0x1U)
#define	SDL_TMU0_ROM_PARITY_FORCE_ERR   (0x2U)
#define	SDL_TMU0_ROM_PARITY_ERR_CLR   (0x10000U)
#define	SDL_PARAM_REG_1   (SDL_PARAM_REG_SET0 + 0x20U)
#define	SDL_PARAM_REG_2   (SDL_PARAM_REG_SET0 + 0x30U)

Variables
static const SDL_GrpChkConfig_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_SOC_ECC_AGGR_MemEntries [SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries [SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries [SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_HSM_ECC_AGGR_MemEntries [SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries [SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries [SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_CPSW3GCSS_ECC_AGGR_MemEntries [SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries [SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries [SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_OSPI1_RAM_ECC_AGGR_MemEntries [SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_RAMIdEntry_t	SDL_SOC_ECC_AGGR_RamIdTable [SDL_SOC_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable [SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable [SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_HSM_ECC_AGGR_RamIdTable [SDL_HSM_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable [SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable [SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CPSW3GCSS_ECC_AGGR_RamIdTable [SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable [SDL_FSS_OSPI_RAM_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable [SDL_FSS_FOTA_8051_RAM_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_OSPI1_RAM_ECC_AGGR_RamIdTable [SDL_OSPI1_RAM_ECC_AGGR_NUM_RAMS]
static SDL_ecc_aggrRegs *const	SDL_ECC_aggrBaseAddressTable [SDL_ECC_Base_Address_TOTAL_ENTRIES]
SDL_ecc_aggrRegs *	SDL_ECC_aggrTransBaseAddressTable [SDL_ECC_MEMTYPE_MAX]
static const SDL_EccAggrEntry_t	SDL_ECC_aggrTable [SDL_ECC_MEMTYPE_MAX]