AM261x MCU+ SDK  10.00.01
phy_common.h
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32 
49 #ifndef PHY_COMMON_H_
50 #define PHY_COMMON_H_
51 
52 /* ========================================================================== */
53 /* Include Files */
54 /* ========================================================================== */
55 
56 #include <stdint.h>
57 #include <stdbool.h>
58 
59 #ifdef __cplusplus
60 extern "C" {
61 #endif
62 
63 /* ========================================================================== */
64 /* Macros */
65 /* ========================================================================== */
66 
67 #define ETHPHYDRV_MAX_OBJ_SIZE ((6*4) + 1 + 3) /* to meet the size of Phy_Obj_t */
68 
70 #define PHY_DIV_ROUNDUP(val, div) (((val) + (div) - 1) / (div))
71 
73 #define PHY_BIT(n) (1U << (n))
74 
76 #define PHY_ON (1U)
77 
78 #define PHY_OFF (0U)
79 
80 #define PHY_CFG_IS_ON(name) ((PHY_CFG_ ## name) == PHY_ON)
81 
82 #define PHY_CFG_IS_OFF(name) ((PHY_CFG_ ## name) == PHY_OFF)
83 
94 #define PHY_SOK ( (int32_t) (0))
95 
96 #define PHY_EFAIL (-(int32_t) (1))
97 
98 #define PHY_EBADARGS (-(int32_t) (2)) (-(int32_t) (2))
99 
100 #define PHY_EINVALIDPARAMS (-(int32_t) (3))
101 
102 #define PHY_ETIMEOUT (-(int32_t) (4))
103 
104 #define PHY_EALLOC (-(int32_t) (8))
105 
106 #define PHY_EPERM (PHY_EALLOC - 4)
107 
108 #define PHY_ENOTSUPPORTED (PHY_EALLOC - 5)
109 
112 /* PHY Register Definitions */
113 
115 #define PHY_BMCR (0x00U)
116 
117 #define PHY_BMSR (0x01U)
118 
119 #define PHY_PHYIDR1 (0x02U)
120 
121 #define PHY_PHYIDR2 (0x03U)
122 
123 #define PHY_ANAR (0x04U)
124 
125 #define PHY_ANLPAR (0x05U)
126 
127 #define PHY_ANER (0x06U)
128 
129 #define PHY_ANNPTR (0x07U)
130 
131 #define PHY_ANNPRR (0x08U)
132 
133 #define PHY_GIGCR (0x09U)
134 
135 #define PHY_GIGSR (0x0AU)
136 
137 #define PHY_MMD_CR (0x0DU)
138 
139 #define PHY_MMD_DR (0x0EU)
140 
141 #define PHY_GIGESR (0x0FU)
142 
143 /* MMD_CR register definitions */
144 #define MMD_CR_ADDR (0x0000U)
145 #define MMD_CR_DATA_NOPOSTINC (0x4000U)
146 #define MMD_CR_DATA_POSTINC_RW (0x8000U)
147 #define MMD_CR_DATA_POSTINC_W (0xC000U)
148 #define MMD_CR_DEVADDR (0x001FU)
149 
150 /* BMCR register definitions */
151 #define PHY_BMCR_RESET PHY_BIT(15)
152 #define PHY_BMCR_LOOPBACK PHY_BIT(14)
153 #define PHY_BMCR_SPEED100 PHY_BIT(13)
154 #define PHY_BMCR_ANEN PHY_BIT(12)
155 #define PHY_BMCR_PWRDOWN PHY_BIT(11)
156 #define PHY_BMCR_ISOLATE PHY_BIT(10)
157 #define PHY_BMCR_ANRESTART PHY_BIT(9)
158 #define PHY_BMCR_FD PHY_BIT(8)
159 #define PHY_BMCR_SPEED1000 PHY_BIT(6)
160 
162 #define PHY_EXTENDED_CFG_SIZE_MAX (128U)
163 
164 
166 #define PHY_LINK_CAP_HD10 PHY_BIT(1)
167 
168 #define PHY_LINK_CAP_FD10 PHY_BIT(2)
169 
170 #define PHY_LINK_CAP_HD100 PHY_BIT(3)
171 
172 #define PHY_LINK_CAP_FD100 PHY_BIT(4)
173 
174 #define PHY_LINK_CAP_HD1000 PHY_BIT(5)
175 
176 #define PHY_LINK_CAP_FD1000 PHY_BIT(6)
177 
178 #define PHY_LINK_CAP_10 (PHY_LINK_CAP_HD10 | PHY_LINK_CAP_FD10)
179 
180 #define PHY_LINK_CAP_100 (PHY_LINK_CAP_HD100 | PHY_LINK_CAP_FD100)
181 
182 #define PHY_LINK_CAP_1000 (PHY_LINK_CAP_HD1000 | PHY_LINK_CAP_FD1000)
183 
184 #define PHY_LINK_CAP_ALL (PHY_LINK_CAP_HD10 | PHY_LINK_CAP_FD10 | \
185  PHY_LINK_CAP_HD100 | PHY_LINK_CAP_FD100 | \
186  PHY_LINK_CAP_HD1000 | PHY_LINK_CAP_FD1000)
187 
188 /* ========================================================================== */
189 /* Structures and Enums */
190 /* ========================================================================== */
191 
192 
193 typedef struct Phy_Version_s
194 {
196  uint32_t oui;
198  uint32_t model;
200  uint32_t revision;
201 } Phy_Version;
202 
203 typedef enum Phy_Mii_e
204 {
206  PHY_MAC_MII_MII = 0U,
207 
209  PHY_MAC_MII_RMII,
210 
212  PHY_MAC_MII_GMII,
213 
215  PHY_MAC_MII_RGMII,
216 
218  PHY_MAC_MII_SGMII,
219 
221  PHY_MAC_MII_QSGMII,
222 } Phy_Mii;
223 
224 typedef struct
225 {
226  int32_t (*EnetPhy_readReg)(void* pArgs, uint32_t reg, uint16_t *val);
227 
228  int32_t (*EnetPhy_writeReg)(void* pArgs, uint32_t reg, uint16_t val);
229 
230  int32_t (*EnetPhy_rmwReg)(void* pArgs, uint32_t reg, uint16_t mask,
231  uint16_t val);
232 
233  int32_t (*EnetPhy_readExtReg)(void* pArgs, uint32_t reg,
234  uint16_t *val);
235 
236  int32_t (*EnetPhy_writeExtReg)(void* pArgs, uint32_t reg,
237  uint16_t val);
238 
240  void* pArgs;
241 
242 } Phy_RegAccessCb_t;
243 
244 typedef uint8_t EthPhyDrv_Handle[ETHPHYDRV_MAX_OBJ_SIZE];
245 
246 typedef struct
247 {
248 
249  struct
250  {
251 
257  const char *name;
258 
274  bool (*isPhyDevSupported)(EthPhyDrv_Handle hPhy,
275  const void *pVersion);
276 
288  bool (*isMacModeSupported)(EthPhyDrv_Handle hPhy,
289  Phy_Mii mii);
290 
302  void (*bind)(EthPhyDrv_Handle* hPhy,
303  uint8_t phyAddr,
304  Phy_RegAccessCb_t* pRegAccessCb);
305 
319  int32_t (*config)(EthPhyDrv_Handle hPhy,
320  const void *pExtCfg,
321  const uint32_t extCfgSize,
322  Phy_Mii mii,
323  bool loopbackEn);
324 
333  void (*reset)(EthPhyDrv_Handle hPhy);
334 
345  bool (*isResetComplete)(EthPhyDrv_Handle hPhy);
346 
359  int32_t (*readExtReg)(EthPhyDrv_Handle hPhy,
360  uint32_t reg,
361  uint16_t* val);
362 
375  int32_t (*writeExtReg)(EthPhyDrv_Handle hPhy,
376  uint32_t reg,
377  uint16_t val);
378 
390  int32_t (*rmwExtReg)(EthPhyDrv_Handle hPhy,
391  uint32_t reg,
392  uint16_t mask,
393  uint16_t* val);
394 
396  void (*printRegs)(EthPhyDrv_Handle hPhy);
397 
409  int32_t (*adjPtpFreq)(EthPhyDrv_Handle hPhy,
410  int64_t ppb);
411 
423  int32_t (*adjPtpPhase)(EthPhyDrv_Handle hPhy,
424  int64_t offset);
425 
437  int32_t (*getPtpTime)(EthPhyDrv_Handle hPhy,
438  uint64_t *ts64);
439 
451  int32_t (*setPtpTime)(EthPhyDrv_Handle hPhy,
452  uint64_t ts64);
453 
468  int32_t (*getPtpTxTime)(EthPhyDrv_Handle hPhy,
469  uint32_t domain,
470  uint32_t msgType,
471  uint32_t seqId,
472  uint64_t *ts64);
473 
488  int32_t (*getPtpRxTime)(EthPhyDrv_Handle hPhy,
489  uint32_t domain,
490  uint32_t msgType,
491  uint32_t seqId,
492  uint64_t *ts64);
493 
507  int32_t (*waitPtpTxTime)(EthPhyDrv_Handle hPhy,
508  uint32_t domain,
509  uint32_t msgType,
510  uint32_t seqId);
511 
525  int32_t (*procStatusFrame)(EthPhyDrv_Handle hPhy,
526  uint8_t *frame,
527  uint32_t size,
528  uint32_t *types);
529 
542  int32_t (*getStatusFrameEthHeader)(EthPhyDrv_Handle hPhy,
543  uint8_t *ethhdr,
544  uint32_t size);
545 
558  int32_t (*enablePtp)(EthPhyDrv_Handle hPhy,
559  bool on,
560  uint32_t srcMacStatusFrameType);
561 
571  int32_t (*tickDriver)(EthPhyDrv_Handle hPhy);
572 
587  int32_t (*enableEventCapture)(EthPhyDrv_Handle hPhy, uint32_t eventIdx,
588  bool falling, bool on);
589 
606  int32_t (*enableTriggerOutput)(EthPhyDrv_Handle hPhy, uint32_t triggerIdx,
607  uint64_t start, uint64_t period, bool repeat);
608 
621  int32_t (*getEventTs)(EthPhyDrv_Handle hPhy, uint32_t *eventIdx,
622  uint32_t *seqId, uint64_t *ts64);
623  } fxn;
624 
625  EthPhyDrv_Handle hDrv;
626 } Phy_DrvObj_t;
627 
628 typedef Phy_DrvObj_t* EthPhyDrv_If;
629 
630 
631 /* TODO: Move this to private files */
632 typedef struct
633 {
634  uint8_t phyAddr;
635  Phy_RegAccessCb_t regAccessApi;
636 } Phy_Obj_t;
637 
638 /* ========================================================================== */
639 /* Global Variables Declarations */
640 /* ========================================================================== */
641 
642 /* ========================================================================== */
643 /* Function Declarations */
644 /* ========================================================================== */
645 
646 int32_t GenericPhy_readExtReg(EthPhyDrv_Handle hPhy,
647  uint32_t reg,
648  uint16_t* val);
649 
650 int32_t GenericPhy_writeExtReg(EthPhyDrv_Handle hPhy,
651  uint32_t reg,
652  uint16_t val);
653 
654 void GenericPhy_reset(EthPhyDrv_Handle hPhy);
655 
656 bool GenericPhy_isResetComplete(EthPhyDrv_Handle hPhy);
657 
658 /* ========================================================================== */
659 /* Deprecated Function Declarations */
660 /* ========================================================================== */
661 
662 /* None */
663 
664 /* ========================================================================== */
665 /* Static Function Definitions */
666 /* ========================================================================== */
667 
668 /* None */
669 
670 #ifdef __cplusplus
671 }
672 #endif
673 
674 #endif /* PHY_COMMON_H_ */
675 
EthPhyDrv_If
Phy_DrvObj_t * EthPhyDrv_If
Definition: phy_common.h:628
PHY_MAC_MII_RGMII
@ PHY_MAC_MII_RGMII
RGMII interface.
Definition: phy_common.h:215
EnetPhy_writeExtReg
int32_t EnetPhy_writeExtReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY extended register.
Phy_Obj_t::regAccessApi
Phy_RegAccessCb_t regAccessApi
Definition: phy_common.h:635
EnetPhy_readExtReg
int32_t EnetPhy_readExtReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY extended register.
Phy_RegAccessCb_t
Definition: phy_common.h:225
EnetPhy_writeReg
int32_t EnetPhy_writeReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY register.
EthPhyDrv_Handle
uint8_t EthPhyDrv_Handle[ETHPHYDRV_MAX_OBJ_SIZE]
Definition: phy_common.h:244
Phy_DrvObj_t
Definition: phy_common.h:247
Phy_Mii
Phy_Mii
Definition: phy_common.h:204
Phy_Version
Definition: phy_common.h:194
PHY_MAC_MII_GMII
@ PHY_MAC_MII_GMII
GMII interface.
Definition: phy_common.h:212
PHY_MAC_MII_QSGMII
@ PHY_MAC_MII_QSGMII
QSGMII interface.
Definition: phy_common.h:221
GenericPhy_readExtReg
int32_t GenericPhy_readExtReg(EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t *val)
PHY_MAC_MII_SGMII
@ PHY_MAC_MII_SGMII
SGMII interface.
Definition: phy_common.h:218
Phy_Obj_t::phyAddr
uint8_t phyAddr
Definition: phy_common.h:634
GenericPhy_reset
void GenericPhy_reset(EthPhyDrv_Handle hPhy)
Phy_Version::model
uint32_t model
Definition: phy_common.h:198
Phy_Version::revision
uint32_t revision
Definition: phy_common.h:200
EnetPhy_rmwReg
int32_t EnetPhy_rmwReg(void *pArgs, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
EnetPhy_readReg
int32_t EnetPhy_readReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY register.
ETHPHYDRV_MAX_OBJ_SIZE
#define ETHPHYDRV_MAX_OBJ_SIZE
Definition: phy_common.h:67
Phy_RegAccessCb_t::pArgs
void * pArgs
Definition: phy_common.h:240
GenericPhy_isResetComplete
bool GenericPhy_isResetComplete(EthPhyDrv_Handle hPhy)
Phy_Version::oui
uint32_t oui
Definition: phy_common.h:196
Phy_DrvObj_t::name
const char * name
Driver name.
Definition: phy_common.h:257
GenericPhy_writeExtReg
int32_t GenericPhy_writeExtReg(EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t val)
Phy_Obj_t
Definition: phy_common.h:633
PHY_MAC_MII_MII
@ PHY_MAC_MII_MII
MII interface.
Definition: phy_common.h:206
Phy_DrvObj_t::hDrv
EthPhyDrv_Handle hDrv
Definition: phy_common.h:625
PHY_MAC_MII_RMII
@ PHY_MAC_MII_RMII
RMII interface.
Definition: phy_common.h:209