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Macros
#define	SOC_BOOTMODE_MMCSD (0X36C3)
	Switch value for SD card boot mode. More...

#define	SOC_FWL_OPEN_MAGIC_NUM (0XFEDCBA98u)
	Software defined MAGIC number to indicate SRAM firewall open by SBL. More...

#define	MCU_MCSPI0_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_MCSPI0_CFG_BASE + 0x80000000)

#define	MCU_MCSPI1_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_MCSPI1_CFG_BASE + 0x80000000)

#define	MCU_UART0_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_UART0_BASE + 0x80000000)

#define	MCU_UART1_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_UART1_BASE + 0x80000000)

#define	MCU_I2C0_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_I2C0_CFG_BASE + 0x80000000)

#define	MCU_I2C1_CFG_BASE_AFTER_ADDR_TRANSLATE (CSL_MCU_I2C1_CFG_BASE + 0x80000000)

#define	IS_OSPI_BASE_ADDR_VALID(baseAddr) (baseAddr == CSL_FSS0_OSPI0_CTRL_BASE)
	Macro to check if the OSPI base address is valid. More...

#define	IS_OSPI_DATA_BASE_ADDR_VALID(baseAddr) (baseAddr == CSL_FSS0_DAT_REG1_BASE)
	Macro to check if the OSPI base address is valid. More...

SOC Domain ID

#define	SOC_DOMAIN_ID_MAIN (0U)

#define	SOC_DOMAIN_ID_MCU (1U)


#define	SOC_PSC_DOMAIN_ID_MAIN (0U)

#define	SOC_PSC_DOMAIN_ID_MCU (1U)

SOC PSC Module State

#define	SOC_PSC_SYNCRESETDISABLE (0x0U)

#define	SOC_PSC_SYNCRESET (0x1U)

#define	SOC_PSC_DISABLE (0x2U)

#define	SOC_PSC_ENABLE (0x3U)

SOC PSC Domain State

#define	SOC_PSC_DOMAIN_OFF (0x0U)

#define	SOC_PSC_DOMAIN_ON (0x1U)

Functions
static int32_t	I2C_lld_isBaseAddrValid (uint32_t baseAddr)
	API to validate I2C base address. More...

static int32_t	MCSPI_lld_isBaseAddrValid (uint32_t baseAddr)
	API to validate MCSPI base address. More...

static int32_t	UART_IsBaseAddrValid (uint32_t baseAddr)
	API to validate UART base address. More...

static int32_t	MMCSD_lld_isBaseAddrValid (uint32_t ctrlBaseAddr, uint32_t ssBaseAddr)
	API to validate MMCSD base addresses. More...

int32_t	SOC_moduleClockEnable (uint32_t moduleId, uint32_t enable)
	Enable clock to specified module. More...

int32_t	SOC_moduleSetClockFrequencyWithParent (uint32_t moduleId, uint32_t clkId, uint32_t clkParent, uint64_t clkRate)
	Set module clock to specified frequency and with a specific parent. More...

int32_t	SOC_moduleSetClockFrequency (uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
	Set module clock to specified frequency. More...

int32_t	SOC_moduleGetClockFrequency (uint32_t moduleId, uint32_t clkId, uint64_t *clkRate)
	Get module clock frequency. More...

const char *	SOC_getCoreName (uint16_t coreId)
	Convert a core ID to a user readable name. More...

uint64_t	SOC_getSelfCpuClk (void)
	Get the clock frequency in Hz of the CPU on which the driver is running. More...

void	SOC_controlModuleLockMMR (uint32_t domainId, uint32_t partition)
	Lock control module partition to prevent writes into control MMRs. More...

void	SOC_controlModuleUnlockMMR (uint32_t domainId, uint32_t partition)
	Unlock control module partition to allow writes into control MMRs. More...

void	SOC_setEpwmTbClk (uint32_t epwmInstance, uint32_t enable)
	Enable or disable ePWM time base clock from Control MMR. More...

void	SOC_allowEpwmTzReg (uint32_t epwmInstance, uint32_t enable)
	Enable or disable writes to the EPWM tripZone registers. More...

uint64_t	SOC_virtToPhy (void *virtAddr)
	SOC Virtual (CPU) to Physical address translation function. More...

void *	SOC_phyToVirt (uint64_t phyAddr)
	Physical to Virtual (CPU) address translation function. More...

void	SOC_unlockAllMMR (void)
	Unlocks all the control MMRs. More...

void	SOC_setDevStat (uint32_t bootMode)
	Change boot mode by setting devstat register. More...

uint32_t	SOC_isR5FDualCoreMode (CSL_ArmR5CPUInfo *cpuInfo)
	Return R5SS supporting single or dual core mode. More...

void	SOC_generateSwWarmResetMainDomain (void)
	Generate SW Warm Reset Main Domain. More...

void	SOC_generateSwPORResetMainDomain (void)
	Generate SW POR Reset Main Domain. More...

uint32_t	SOC_getWarmResetCauseMainDomain (void)
	Get the reset reason source for Main Domain. More...

void	SOC_generateSwWarmResetMcuDomain (void)
	Generate SW WARM Reset Mcu Domain. More...

void	SOC_generateSwWarmResetMainDomainFromMcuDomain (void)
	Generate SW WARM Reset Main Domain from Mcu Domain. More...

void	SOC_generateSwPORResetMainDomainFromMcuDomain (void)
	Generate SW POR Reset Main Domain from Mcu Domain. More...

uint32_t	SOC_getWarmResetCauseMcuDomain (void)
	Get the reset reason source for Mcu Domain. More...

void	SOC_clearResetCauseMainMcuDomain (uint32_t resetCause)
	Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLMMR_MCU_RST_SRC register. It is read only. So we need to write 1 to CTRLMMR_MCU_RST_SRC to clear the reset reason. More...

int32_t	SOC_enableResetIsolation (uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, uint32_t debugIsolationEnable)
	Enable reset isolation of MCU domain for safety applications. More...

void	SOC_setMCUResetIsolationDone (uint32_t value)
	Set MCU reset isolation done flag. More...

void	SOC_waitMainDomainReset (void)
	Wait for main domain reset to complete. More...

int32_t	SOC_getPSCState (uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t domainState, uint32_t moduleState)
	Get PSC (Power Sleep Controller) state. More...

int32_t	SOC_setPSCState (uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState)
	Set PSC (Power Sleep Controller) state. More...

void	SOC_waitForFwlUnlock (void)
	Wait for Firewall unlock from SBL. The function polls for a Software defined Magic number at the PSRAM location (Software defined) More...

int32_t	SOC_isHsDevice (void)
	Check the device is HS or not. More...

uint32_t	SOC_getFlashDataBaseAddr (void)
	This function gets the SOC mapped data base address of the flash. More...

Macros

Functions