Introduction

DMSC controls the power management, security and resource management of the device.

Macros
#define	TISCI_DEV_ADC0 0U
	This file contains: More...

#define	TISCI_DEV_CMP_EVENT_INTROUTER0 1U

#define	TISCI_DEV_DBGSUSPENDROUTER0 2U

#define	TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3U

#define	TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0 5U

#define	TISCI_DEV_TIMESYNC_EVENT_INTROUTER0 6U

#define	TISCI_DEV_MCU_M4FSS0 7U

#define	TISCI_DEV_MCU_M4FSS0_CBASS_0 8U

#define	TISCI_DEV_MCU_M4FSS0_CORE0 9U

#define	TISCI_DEV_CPSW0 13U

#define	TISCI_DEV_CPT2_AGGR0 14U

#define	TISCI_DEV_STM0 15U

#define	TISCI_DEV_DCC0 16U

#define	TISCI_DEV_DCC1 17U

#define	TISCI_DEV_DCC2 18U

#define	TISCI_DEV_DCC3 19U

#define	TISCI_DEV_DCC4 20U

#define	TISCI_DEV_DCC5 21U

#define	TISCI_DEV_DMSC0 22U

#define	TISCI_DEV_MCU_DCC0 23U

#define	TISCI_DEV_DEBUGSS_WRAP0 24U

#define	TISCI_DEV_DMASS0 25U

#define	TISCI_DEV_DMASS0_BCDMA_0 26U

#define	TISCI_DEV_DMASS0_CBASS_0 27U

#define	TISCI_DEV_DMASS0_INTAGGR_0 28U

#define	TISCI_DEV_DMASS0_IPCSS_0 29U

#define	TISCI_DEV_DMASS0_PKTDMA_0 30U

#define	TISCI_DEV_DMASS0_RINGACC_0 33U

#define	TISCI_DEV_MCU_TIMER0 35U

#define	TISCI_DEV_TIMER0 36U

#define	TISCI_DEV_TIMER1 37U

#define	TISCI_DEV_TIMER2 38U

#define	TISCI_DEV_TIMER3 39U

#define	TISCI_DEV_TIMER4 40U

#define	TISCI_DEV_TIMER5 41U

#define	TISCI_DEV_TIMER6 42U

#define	TISCI_DEV_TIMER7 43U

#define	TISCI_DEV_TIMER8 44U

#define	TISCI_DEV_TIMER9 45U

#define	TISCI_DEV_TIMER10 46U

#define	TISCI_DEV_TIMER11 47U

#define	TISCI_DEV_MCU_TIMER1 48U

#define	TISCI_DEV_MCU_TIMER2 49U

#define	TISCI_DEV_MCU_TIMER3 50U

#define	TISCI_DEV_ECAP0 51U

#define	TISCI_DEV_ECAP1 52U

#define	TISCI_DEV_ECAP2 53U

#define	TISCI_DEV_ELM0 54U

#define	TISCI_DEV_EMIF_DATA_0_VD 55U

#define	TISCI_DEV_MMCSD0 57U

#define	TISCI_DEV_MMCSD1 58U

#define	TISCI_DEV_EQEP0 59U

#define	TISCI_DEV_EQEP1 60U

#define	TISCI_DEV_GTC0 61U

#define	TISCI_DEV_EQEP2 62U

#define	TISCI_DEV_ESM0 63U

#define	TISCI_DEV_MCU_ESM0 64U

#define	TISCI_DEV_FSIRX0 65U

#define	TISCI_DEV_FSIRX1 66U

#define	TISCI_DEV_FSIRX2 67U

#define	TISCI_DEV_FSIRX3 68U

#define	TISCI_DEV_FSIRX4 69U

#define	TISCI_DEV_FSIRX5 70U

#define	TISCI_DEV_FSITX0 71U

#define	TISCI_DEV_FSITX1 72U

#define	TISCI_DEV_FSS0 73U

#define	TISCI_DEV_FSS0_FSAS_0 74U

#define	TISCI_DEV_FSS0_OSPI_0 75U

#define	TISCI_DEV_GICSS0 76U

#define	TISCI_DEV_GPIO0 77U

#define	TISCI_DEV_GPIO1 78U

#define	TISCI_DEV_MCU_GPIO0 79U

#define	TISCI_DEV_GPMC0 80U

#define	TISCI_DEV_PRU_ICSSG0 81U

#define	TISCI_DEV_PRU_ICSSG1 82U

#define	TISCI_DEV_LED0 83U

#define	TISCI_DEV_CPTS0 84U

#define	TISCI_DEV_DDPA0 85U

#define	TISCI_DEV_EPWM0 86U

#define	TISCI_DEV_EPWM1 87U

#define	TISCI_DEV_EPWM2 88U

#define	TISCI_DEV_EPWM3 89U

#define	TISCI_DEV_EPWM4 90U

#define	TISCI_DEV_EPWM5 91U

#define	TISCI_DEV_EPWM6 92U

#define	TISCI_DEV_EPWM7 93U

#define	TISCI_DEV_EPWM8 94U

#define	TISCI_DEV_VTM0 95U

#define	TISCI_DEV_MAILBOX0 96U

#define	TISCI_DEV_MAIN2MCU_VD 97U

#define	TISCI_DEV_MCAN0 98U

#define	TISCI_DEV_MCAN1 99U

#define	TISCI_DEV_MCU_MCRC64_0 100U

#define	TISCI_DEV_MCU2MAIN_VD 101U

#define	TISCI_DEV_I2C0 102U

#define	TISCI_DEV_I2C1 103U

#define	TISCI_DEV_I2C2 104U

#define	TISCI_DEV_I2C3 105U

#define	TISCI_DEV_MCU_I2C0 106U

#define	TISCI_DEV_MCU_I2C1 107U

#define	TISCI_DEV_PCIE0 114U

#define	TISCI_DEV_R5FSS0 119U

#define	TISCI_DEV_R5FSS1 120U

#define	TISCI_DEV_R5FSS0_CORE0 121U

#define	TISCI_DEV_R5FSS0_CORE1 122U

#define	TISCI_DEV_R5FSS1_CORE0 123U

#define	TISCI_DEV_R5FSS1_CORE1 124U

#define	TISCI_DEV_RTI0 125U

#define	TISCI_DEV_RTI1 126U

#define	TISCI_DEV_RTI8 127U

#define	TISCI_DEV_RTI9 128U

#define	TISCI_DEV_RTI10 130U

#define	TISCI_DEV_RTI11 131U

#define	TISCI_DEV_MCU_RTI0 132U

#define	TISCI_DEV_SA2_UL0 133U

#define	TISCI_DEV_COMPUTE_CLUSTER0 134U

#define	TISCI_DEV_A53SS0_CORE_0 135U

#define	TISCI_DEV_A53SS0_CORE_1 136U

#define	TISCI_DEV_A53SS0 137U

#define	TISCI_DEV_DDR16SS0 138U

#define	TISCI_DEV_PSC0 139U

#define	TISCI_DEV_MCU_PSC0 140U

#define	TISCI_DEV_MCSPI0 141U

#define	TISCI_DEV_MCSPI1 142U

#define	TISCI_DEV_MCSPI2 143U

#define	TISCI_DEV_MCSPI3 144U

#define	TISCI_DEV_MCSPI4 145U

#define	TISCI_DEV_UART0 146U

#define	TISCI_DEV_MCU_MCSPI0 147U

#define	TISCI_DEV_MCU_MCSPI1 148U

#define	TISCI_DEV_MCU_UART0 149U

#define	TISCI_DEV_SPINLOCK0 150U

#define	TISCI_DEV_TIMERMGR0 151U

#define	TISCI_DEV_UART1 152U

#define	TISCI_DEV_UART2 153U

#define	TISCI_DEV_UART3 154U

#define	TISCI_DEV_UART4 155U

#define	TISCI_DEV_UART5 156U

#define	TISCI_DEV_BOARD0 157U

#define	TISCI_DEV_UART6 158U

#define	TISCI_DEV_MCU_UART1 160U

#define	TISCI_DEV_USB0 161U

#define	TISCI_DEV_SERDES_10G0 162U

#define	TISCI_DEV_PBIST0 163U

#define	TISCI_DEV_PBIST1 164U

#define	TISCI_DEV_PBIST2 165U

#define	TISCI_DEV_PBIST3 166U

#define	TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0 167U

Macro Definition Documentation

◆ TISCI_DEV_ADC0

#define TISCI_DEV_ADC0 0U

This file contains:

    WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!

Data version: 230209_212853

◆ TISCI_DEV_CMP_EVENT_INTROUTER0

#define TISCI_DEV_CMP_EVENT_INTROUTER0 1U

◆ TISCI_DEV_DBGSUSPENDROUTER0

#define TISCI_DEV_DBGSUSPENDROUTER0 2U

◆ TISCI_DEV_MAIN_GPIOMUX_INTROUTER0

#define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3U

◆ TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0

#define TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0 5U

◆ TISCI_DEV_TIMESYNC_EVENT_INTROUTER0

#define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0 6U

◆ TISCI_DEV_MCU_M4FSS0

#define TISCI_DEV_MCU_M4FSS0 7U

◆ TISCI_DEV_MCU_M4FSS0_CBASS_0

#define TISCI_DEV_MCU_M4FSS0_CBASS_0 8U

◆ TISCI_DEV_MCU_M4FSS0_CORE0

#define TISCI_DEV_MCU_M4FSS0_CORE0 9U

◆ TISCI_DEV_CPSW0

#define TISCI_DEV_CPSW0 13U

◆ TISCI_DEV_CPT2_AGGR0

#define TISCI_DEV_CPT2_AGGR0 14U

◆ TISCI_DEV_STM0

#define TISCI_DEV_STM0 15U

◆ TISCI_DEV_DCC0

#define TISCI_DEV_DCC0 16U

◆ TISCI_DEV_DCC1

#define TISCI_DEV_DCC1 17U

◆ TISCI_DEV_DCC2

#define TISCI_DEV_DCC2 18U

◆ TISCI_DEV_DCC3

#define TISCI_DEV_DCC3 19U

◆ TISCI_DEV_DCC4

#define TISCI_DEV_DCC4 20U

◆ TISCI_DEV_DCC5

#define TISCI_DEV_DCC5 21U

◆ TISCI_DEV_DMSC0

#define TISCI_DEV_DMSC0 22U

◆ TISCI_DEV_MCU_DCC0

#define TISCI_DEV_MCU_DCC0 23U

◆ TISCI_DEV_DEBUGSS_WRAP0

#define TISCI_DEV_DEBUGSS_WRAP0 24U

◆ TISCI_DEV_DMASS0

#define TISCI_DEV_DMASS0 25U

◆ TISCI_DEV_DMASS0_BCDMA_0

#define TISCI_DEV_DMASS0_BCDMA_0 26U

◆ TISCI_DEV_DMASS0_CBASS_0

#define TISCI_DEV_DMASS0_CBASS_0 27U

◆ TISCI_DEV_DMASS0_INTAGGR_0

#define TISCI_DEV_DMASS0_INTAGGR_0 28U

◆ TISCI_DEV_DMASS0_IPCSS_0

#define TISCI_DEV_DMASS0_IPCSS_0 29U

◆ TISCI_DEV_DMASS0_PKTDMA_0

#define TISCI_DEV_DMASS0_PKTDMA_0 30U

◆ TISCI_DEV_DMASS0_RINGACC_0

#define TISCI_DEV_DMASS0_RINGACC_0 33U

◆ TISCI_DEV_MCU_TIMER0

#define TISCI_DEV_MCU_TIMER0 35U

◆ TISCI_DEV_TIMER0

#define TISCI_DEV_TIMER0 36U

◆ TISCI_DEV_TIMER1

#define TISCI_DEV_TIMER1 37U

◆ TISCI_DEV_TIMER2

#define TISCI_DEV_TIMER2 38U

◆ TISCI_DEV_TIMER3

#define TISCI_DEV_TIMER3 39U

◆ TISCI_DEV_TIMER4

#define TISCI_DEV_TIMER4 40U

◆ TISCI_DEV_TIMER5

#define TISCI_DEV_TIMER5 41U

◆ TISCI_DEV_TIMER6

#define TISCI_DEV_TIMER6 42U

◆ TISCI_DEV_TIMER7

#define TISCI_DEV_TIMER7 43U

◆ TISCI_DEV_TIMER8

#define TISCI_DEV_TIMER8 44U

◆ TISCI_DEV_TIMER9

#define TISCI_DEV_TIMER9 45U

◆ TISCI_DEV_TIMER10

#define TISCI_DEV_TIMER10 46U

◆ TISCI_DEV_TIMER11

#define TISCI_DEV_TIMER11 47U

◆ TISCI_DEV_MCU_TIMER1

#define TISCI_DEV_MCU_TIMER1 48U

◆ TISCI_DEV_MCU_TIMER2

#define TISCI_DEV_MCU_TIMER2 49U

◆ TISCI_DEV_MCU_TIMER3

#define TISCI_DEV_MCU_TIMER3 50U

◆ TISCI_DEV_ECAP0

#define TISCI_DEV_ECAP0 51U

◆ TISCI_DEV_ECAP1

#define TISCI_DEV_ECAP1 52U

◆ TISCI_DEV_ECAP2

#define TISCI_DEV_ECAP2 53U

◆ TISCI_DEV_ELM0

#define TISCI_DEV_ELM0 54U

◆ TISCI_DEV_EMIF_DATA_0_VD

#define TISCI_DEV_EMIF_DATA_0_VD 55U

◆ TISCI_DEV_MMCSD0

#define TISCI_DEV_MMCSD0 57U

◆ TISCI_DEV_MMCSD1

#define TISCI_DEV_MMCSD1 58U

◆ TISCI_DEV_EQEP0

#define TISCI_DEV_EQEP0 59U

◆ TISCI_DEV_EQEP1

#define TISCI_DEV_EQEP1 60U

◆ TISCI_DEV_GTC0

#define TISCI_DEV_GTC0 61U

◆ TISCI_DEV_EQEP2

#define TISCI_DEV_EQEP2 62U

◆ TISCI_DEV_ESM0

#define TISCI_DEV_ESM0 63U

◆ TISCI_DEV_MCU_ESM0

#define TISCI_DEV_MCU_ESM0 64U

◆ TISCI_DEV_FSIRX0

#define TISCI_DEV_FSIRX0 65U

◆ TISCI_DEV_FSIRX1

#define TISCI_DEV_FSIRX1 66U

◆ TISCI_DEV_FSIRX2

#define TISCI_DEV_FSIRX2 67U

◆ TISCI_DEV_FSIRX3

#define TISCI_DEV_FSIRX3 68U

◆ TISCI_DEV_FSIRX4

#define TISCI_DEV_FSIRX4 69U

◆ TISCI_DEV_FSIRX5

#define TISCI_DEV_FSIRX5 70U

◆ TISCI_DEV_FSITX0

#define TISCI_DEV_FSITX0 71U

◆ TISCI_DEV_FSITX1

#define TISCI_DEV_FSITX1 72U

◆ TISCI_DEV_FSS0

#define TISCI_DEV_FSS0 73U

◆ TISCI_DEV_FSS0_FSAS_0

#define TISCI_DEV_FSS0_FSAS_0 74U

◆ TISCI_DEV_FSS0_OSPI_0

#define TISCI_DEV_FSS0_OSPI_0 75U

◆ TISCI_DEV_GICSS0

#define TISCI_DEV_GICSS0 76U

◆ TISCI_DEV_GPIO0

#define TISCI_DEV_GPIO0 77U

◆ TISCI_DEV_GPIO1

#define TISCI_DEV_GPIO1 78U

◆ TISCI_DEV_MCU_GPIO0

#define TISCI_DEV_MCU_GPIO0 79U

◆ TISCI_DEV_GPMC0

#define TISCI_DEV_GPMC0 80U

◆ TISCI_DEV_PRU_ICSSG0

#define TISCI_DEV_PRU_ICSSG0 81U

◆ TISCI_DEV_PRU_ICSSG1

#define TISCI_DEV_PRU_ICSSG1 82U

◆ TISCI_DEV_LED0

#define TISCI_DEV_LED0 83U

◆ TISCI_DEV_CPTS0

#define TISCI_DEV_CPTS0 84U

◆ TISCI_DEV_DDPA0

#define TISCI_DEV_DDPA0 85U

◆ TISCI_DEV_EPWM0

#define TISCI_DEV_EPWM0 86U

◆ TISCI_DEV_EPWM1

#define TISCI_DEV_EPWM1 87U

◆ TISCI_DEV_EPWM2

#define TISCI_DEV_EPWM2 88U

◆ TISCI_DEV_EPWM3

#define TISCI_DEV_EPWM3 89U

◆ TISCI_DEV_EPWM4

#define TISCI_DEV_EPWM4 90U

◆ TISCI_DEV_EPWM5

#define TISCI_DEV_EPWM5 91U

◆ TISCI_DEV_EPWM6

#define TISCI_DEV_EPWM6 92U

◆ TISCI_DEV_EPWM7

#define TISCI_DEV_EPWM7 93U

◆ TISCI_DEV_EPWM8

#define TISCI_DEV_EPWM8 94U

◆ TISCI_DEV_VTM0

#define TISCI_DEV_VTM0 95U

◆ TISCI_DEV_MAILBOX0

#define TISCI_DEV_MAILBOX0 96U

◆ TISCI_DEV_MAIN2MCU_VD

#define TISCI_DEV_MAIN2MCU_VD 97U

◆ TISCI_DEV_MCAN0

#define TISCI_DEV_MCAN0 98U

◆ TISCI_DEV_MCAN1

#define TISCI_DEV_MCAN1 99U

◆ TISCI_DEV_MCU_MCRC64_0

#define TISCI_DEV_MCU_MCRC64_0 100U

◆ TISCI_DEV_MCU2MAIN_VD

#define TISCI_DEV_MCU2MAIN_VD 101U

◆ TISCI_DEV_I2C0

#define TISCI_DEV_I2C0 102U

◆ TISCI_DEV_I2C1

#define TISCI_DEV_I2C1 103U

◆ TISCI_DEV_I2C2

#define TISCI_DEV_I2C2 104U

◆ TISCI_DEV_I2C3

#define TISCI_DEV_I2C3 105U

◆ TISCI_DEV_MCU_I2C0

#define TISCI_DEV_MCU_I2C0 106U

◆ TISCI_DEV_MCU_I2C1

#define TISCI_DEV_MCU_I2C1 107U

◆ TISCI_DEV_PCIE0

#define TISCI_DEV_PCIE0 114U

◆ TISCI_DEV_R5FSS0

#define TISCI_DEV_R5FSS0 119U

◆ TISCI_DEV_R5FSS1

#define TISCI_DEV_R5FSS1 120U

◆ TISCI_DEV_R5FSS0_CORE0

#define TISCI_DEV_R5FSS0_CORE0 121U

◆ TISCI_DEV_R5FSS0_CORE1

#define TISCI_DEV_R5FSS0_CORE1 122U

◆ TISCI_DEV_R5FSS1_CORE0

#define TISCI_DEV_R5FSS1_CORE0 123U

◆ TISCI_DEV_R5FSS1_CORE1

#define TISCI_DEV_R5FSS1_CORE1 124U

◆ TISCI_DEV_RTI0

#define TISCI_DEV_RTI0 125U

◆ TISCI_DEV_RTI1

#define TISCI_DEV_RTI1 126U

◆ TISCI_DEV_RTI8

#define TISCI_DEV_RTI8 127U

◆ TISCI_DEV_RTI9

#define TISCI_DEV_RTI9 128U

◆ TISCI_DEV_RTI10

#define TISCI_DEV_RTI10 130U

◆ TISCI_DEV_RTI11

#define TISCI_DEV_RTI11 131U

◆ TISCI_DEV_MCU_RTI0

#define TISCI_DEV_MCU_RTI0 132U

◆ TISCI_DEV_SA2_UL0

#define TISCI_DEV_SA2_UL0 133U

◆ TISCI_DEV_COMPUTE_CLUSTER0

#define TISCI_DEV_COMPUTE_CLUSTER0 134U

◆ TISCI_DEV_A53SS0_CORE_0

#define TISCI_DEV_A53SS0_CORE_0 135U

◆ TISCI_DEV_A53SS0_CORE_1

#define TISCI_DEV_A53SS0_CORE_1 136U

◆ TISCI_DEV_A53SS0

#define TISCI_DEV_A53SS0 137U

◆ TISCI_DEV_DDR16SS0

#define TISCI_DEV_DDR16SS0 138U

◆ TISCI_DEV_PSC0

#define TISCI_DEV_PSC0 139U

◆ TISCI_DEV_MCU_PSC0

#define TISCI_DEV_MCU_PSC0 140U

◆ TISCI_DEV_MCSPI0

#define TISCI_DEV_MCSPI0 141U

◆ TISCI_DEV_MCSPI1

#define TISCI_DEV_MCSPI1 142U

◆ TISCI_DEV_MCSPI2

#define TISCI_DEV_MCSPI2 143U

◆ TISCI_DEV_MCSPI3

#define TISCI_DEV_MCSPI3 144U

◆ TISCI_DEV_MCSPI4

#define TISCI_DEV_MCSPI4 145U

◆ TISCI_DEV_UART0

#define TISCI_DEV_UART0 146U

◆ TISCI_DEV_MCU_MCSPI0

#define TISCI_DEV_MCU_MCSPI0 147U

◆ TISCI_DEV_MCU_MCSPI1

#define TISCI_DEV_MCU_MCSPI1 148U

◆ TISCI_DEV_MCU_UART0

#define TISCI_DEV_MCU_UART0 149U

◆ TISCI_DEV_SPINLOCK0

#define TISCI_DEV_SPINLOCK0 150U

◆ TISCI_DEV_TIMERMGR0

#define TISCI_DEV_TIMERMGR0 151U

◆ TISCI_DEV_UART1

#define TISCI_DEV_UART1 152U

◆ TISCI_DEV_UART2

#define TISCI_DEV_UART2 153U

◆ TISCI_DEV_UART3

#define TISCI_DEV_UART3 154U

◆ TISCI_DEV_UART4

#define TISCI_DEV_UART4 155U

◆ TISCI_DEV_UART5

#define TISCI_DEV_UART5 156U

◆ TISCI_DEV_BOARD0

#define TISCI_DEV_BOARD0 157U

◆ TISCI_DEV_UART6

#define TISCI_DEV_UART6 158U

◆ TISCI_DEV_MCU_UART1

#define TISCI_DEV_MCU_UART1 160U

◆ TISCI_DEV_USB0

#define TISCI_DEV_USB0 161U

◆ TISCI_DEV_SERDES_10G0

#define TISCI_DEV_SERDES_10G0 162U

◆ TISCI_DEV_PBIST0

#define TISCI_DEV_PBIST0 163U

◆ TISCI_DEV_PBIST1

#define TISCI_DEV_PBIST1 164U

◆ TISCI_DEV_PBIST2

#define TISCI_DEV_PBIST2 165U

◆ TISCI_DEV_PBIST3

#define TISCI_DEV_PBIST3 166U

◆ TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0

#define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0 167U