This page lists the exceptions TI's EtherCAT SubDevice Controller implementation when compared with ET1100 ASIC.
TI ESC register map is fully compatible with ET1100 ASIC register map except for the registers and register fields documented below.
Register(s) | Remarks |
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Write Register Enable (0x0020) Write Register Protection (0x0021) ESC Write Enable (0x0030) ESC Write Protection (0x0031) | Not available in TI ESC |
PDI Control (0x0140) ESC Configuration (0x0141) | PDI side access is an exception. RW access is enabled to allow loading of 0x140 and 0x141 from EEPROM ADDR: 0x0000 during RESET. TI ESC uses EEPROM emulation mode. For more details, see ESI EEPROM Emulation Support. |
PDI configuration (0x0150) Sync/Latch[1:0] PDI Configuration (0x0151) | NOT loaded from EEPROM ADDR: 0x0001 during RESET. This is read only and only bit field 3 and 7 are valid i.e. SYNC0/1 mapped to AL Event Request register 0x0220.2/0x0220.3. Beckhoff is going to make proposal to ETG to make EEPROM loading of this register [0x0150:0x0153] on RESET as well as PDI side implementation ESC vendor specific. |
On-chip bus extended configuration (0x0152:0x0153) | Not available in TI ESC |
RX Error Counter of Port 0 & 1 (0x0301 and 0x303) |
|
ECAT Processing Unit Error Counter(0x030C) | Physical layer errors are not counted by TI ESC. |
PDI Error Counter (0x030D) | Not available in TI ESC |
Watchdog Divider (0x0400:0x0401) | For TI ESC max value is:
|
Status SyncManager 0 : 0x0805.Bits4-7 Status SyncManager 1 : 0x080D.Bits4-7 Status SyncManager 2 : 0x0815.Bits4-7 Status SyncManager 3 : 0x081D.Bits4-7 Status SyncManager 4 : 0x0825.Bits4-7 Status SyncManager 5 : 0x082D.Bits4-7 Status SyncManager 6 : 0x0835.Bits4-7 Status SyncManager 7 : 0x083D.Bits4-7 | Following Bits are NOT implemented Bit 4-5: Buffered mode: buffer status (last written buffer) 00: 1. buffer 01: 2. buffer 10: 3. buffer 11: (no buffer written) Mailbox mode: reserved Bit 6: Read buffer in use (opened) Bit 7: Write buffer in use (opened) |
Activate SyncManager 0 : 0x806.Bits6-7 Activate SyncManager 1 : 0x80E.Bits6-7 Activate SyncManager 2 : 0x816.Bits6-7 Activate SyncManager 3 : 0x81E.Bits6-7 Activate SyncManager 4 : 0x826.Bits6-7 Activate SyncManager 5 : 0x82E.Bits6-7 Activate SyncManager 6 : 0x836.Bits6-7 Activate SyncManager 7 : 0x83E.Bits6-7 | Following Bits are NOT implemented Bit 6: Latch Event ECAT 1: Generate Latch event if EtherCAT MainDevice issues a buffer exchange Bit 7: Latch Event PDI 1: Generate Latch events if PDI issues a buffer exchange or if PDI accesses buffer start address |
Start Time Cyclic Operation (0x0990:0x0997) | System time of next pulse register (0x990:0x993) is not updated instantaneously, resulting in read of incorrect value if read immediately after sync pulse. |
Latch0 Status (0x09AE).Bit2 Latch1 Status (0x09AF).Bit2 | Following Bit is not implemented Bit 2: Latch0/1 pin state |
EtherCAT Buffer Change Event Time (0x09F0:0x09F3) PDI Buffer Start Event Time (0x09F8:0x09FB) PDI Buffer Change Event Time (0x09FC:0x09FF) | Not available in TI ESC |
Digital Outputs (0x0F00:0x0F03) | Digital Outputs are updated at the end of an EtherCAT frame which triggered the Process Data Watchdog in ET1100 with typical SyncManager configuration: a frame containing a write access to at least one of the registers 0x0F00:0x0F03. TI ESC firmware requires SyncManager address to be higher than or equal to 0x1000. |
Issue | Description |
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PINDSW-47/SDOCM00092510: Single datagram accessing multiple FMMU mapped areas using LRD/LWR commands from a single SubDevice | Increased codememory requirements needed in firmware to implement this support. LRW command supports this which is more optimal with lower framing overhead. Minor use case impact as more optimal solutions exists. May cause interop issues with certain MainDevices if 8 SM is supported by SubDevice and all of them are accessed via single logical datagram |
PINDSW-72/SDOCM00098105: PDI/PD watchdog counter incremented by 1 whenever PDI/PD watchdog is disabled using EtherCAT MainDevice | Whenever EtherCAT MainDevice disables WD by writing zero to respective Watchdog Time registers (0x0410:0x0411 or 0x0420:0x0421). ICSS h/w limitation, can potentially workaround in firmware by maintaining this counter in firmware but require additional instructions. This has very minor use case impact to undertake this. |
PINDSW-74/SDOCM00098950: LRD access on unused registers results in WKC increment | Firmware does not support register protection in LRD mode at this moment, it requires more firmware footprint to support, this minor spec compliance does not justify the footprint increase and there are no Write Only registers in ESC. LRD access to unused register is not a practical use case. |
PINDSW-141/SDOCM00105048: LRW access to non-interleaved input and output process data of multiple SubDevices does not work | Conditions in which failures occur Root Cause Work-around |
Functional Difference | Description |
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Increased Process Path latency | There are certain scenarios under which TI ESC requires increased process path latency. Please refer to section 3.6.2 of PRU-ICSS EtherCAT SubDevice Troubleshooting Guide for more details. |
Enhanced link detection using RX_ERR and PHY does not support fast link detection | RX_ERR detection is valid only during inside frame. This may not be as reliable as ET1100 which supports RX_ERR detection outside frame. |
APRW/FPRW/BRW for SM mapped process data memory | This is not a valid use as RW access to SM mapped area does not make sense. |
LINKACT LED is controlled using the Link/Activity signals from the PHY | It is recommended to drive the LINKACT LED from ESC, instead of the Link/Activity LED signals of the PHY. Possible Solution PHY LEDs can be controlled from R5F by periodically monitoring change in following registers: RX Port0 frame counter(0x0E00:0x0E03) RX Port1 frame counter(0x0E04:0x0E07) |
TI ESC follows section "11.2.4 EEPROM Emulation" in EtherCAT ESC Datasheet Section 1 - Technology from functional principle point of view. This is typically used in IP core based ESCs with non-volatile memory. Here, host CPU emulates all EEPROM operations (read/write/reload) using RAM and from EtherCAT MainDevice point of view, this is equivalent to I2C EEPROM managed by ESC.
In ET1100 ASIC, the EtherCAT MainDevice can invoke reloading the EEPROM content. In this case the Configured Station Alias 0x0012:0x0013 and PDI Control Bit 0x0140.9 (enhanced link detection) are not taken over, they are only taken over at the initial EEPROM loading after power-on or reset.
In IP core based ESCs, however the read data for a reload command (or the initial EEPROM loading) is reduced to the Configured Station Alias (0x0012:0x0013) and the Enhanced Link Detection Enables (0x0140[9], 0x0140[15:12]). IP core uses scheme described in section "2.45.1 EEPROM emulation with 32 bit EEPROM data register" of EtherCAT ESC Datasheet Section 2 - Register Description. There are some exceptions to how this implemented in TI ESC, compared to IP core.