rtl_flash_handler.h File Reference

#include <QtCore>
#include "fpl_common.h"

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Data Structures
struct	EraseInfo_t
	This structure is used as input to RTLDevice::eraseFlash(). More...
struct	ProgramInfo_t
	This structure is used as input to RTLDevice::programFlash() and RTLDevice::verifyFlash(). More...
class	RTLFlashHandler

Macros
#define	DONT_CHANGE_TEST_STATE   false

Enumerations
enum	RTL_ERASE_TYPE { ET_ERASE_ALL, ET_ERASE_ALL_FORCED, ET_ERASE_PAGE_RANGE, ET_ERASE_PAGES_IN_SOURCE }
enum	RTL_PROGRAM_TYPE { PT_PROGRAM_PAGES_IN_SOURCE, PT_PROGRAM_EXLUDE_PAGES, PT_PROGRAM_EXLUDE_PAGES_FILLED_WITH }
enum	CM3_CPU_REGISTERS {   CM3_CPU_REG_R0 = 512, CM3_CPU_REG_R1 = 1 + 512, CM3_CPU_REG_R2 = 2 + 512, CM3_CPU_REG_R3 = 3 + 512,   CM3_CPU_REG_R4 = 4 + 512, CM3_CPU_REG_R5 = 5 + 512, CM3_CPU_REG_R6 = 6 + 512, CM3_CPU_REG_R7 = 7 + 512,   CM3_CPU_REG_R8 = 8 + 512, CM3_CPU_REG_R9 = 9 + 512, CM3_CPU_REG_R10 = 10 + 512, CM3_CPU_REG_R11 = 11 + 512,   CM3_CPU_REG_R12 = 12 + 512, CM3_CPU_REG_R13 = 13 + 512, CM3_CPU_REG_R14 = 14 + 512, CM3_CPU_REG_R15 = 15 + 512,   CM3_CPU_REG_R13MSP = 17 + 512 }
	The XDS debug interface uses an offset of 512 to address the CPU registers. More...

Macro Definition Documentation

DONT_CHANGE_TEST_STATE

#define DONT_CHANGE_TEST_STATE   false

Enumeration Type Documentation

RTL_ERASE_TYPE

enum RTL_ERASE_TYPE

Enumerator
ET_ERASE_ALL	Erase all unprotected pages.
ET_ERASE_ALL_FORCED	Forced mass erase. Must be followed by a device re-connect.
ET_ERASE_PAGE_RANGE	Erase a range of pages.
ET_ERASE_PAGES_IN_SOURCE	Erase all pages used in source file.

RTL_PROGRAM_TYPE

enum RTL_PROGRAM_TYPE

Enumerator
PT_PROGRAM_PAGES_IN_SOURCE	Program all pages used in source file.
PT_PROGRAM_EXLUDE_PAGES	Exclude given pages from source file.
PT_PROGRAM_EXLUDE_PAGES_FILLED_WITH	Exclude pages from source file filled with given value.

CM3_CPU_REGISTERS

enum CM3_CPU_REGISTERS

The XDS debug interface uses an offset of 512 to address the CPU registers.

Enumerator
CM3_CPU_REG_R0	CPU Register 0.
CM3_CPU_REG_R1	CPU Register 1.
CM3_CPU_REG_R2	CPU Register 2.
CM3_CPU_REG_R3	CPU Register 3.
CM3_CPU_REG_R4	CPU Register 4.
CM3_CPU_REG_R5	CPU Register 5.
CM3_CPU_REG_R6	CPU Register 6.
CM3_CPU_REG_R7	CPU Register 7.
CM3_CPU_REG_R8	CPU Register 8.
CM3_CPU_REG_R9	CPU Register 9.
CM3_CPU_REG_R10	CPU Register 10.
CM3_CPU_REG_R11	CPU Register 11.
CM3_CPU_REG_R12	CPU Register 12.
CM3_CPU_REG_R13	CPU Register 13.
CM3_CPU_REG_R14	CPU Register 14.
CM3_CPU_REG_R15	CPU Register 15.
CM3_CPU_REG_R13MSP	CPU Register 15.