RF Core

Data Structures
struct	rfTrim_t

Functions
static void	RFCClockEnable (void)
	Enable the RF core clocks. More...
static void	RFCClockDisable (void)
	Disable the RF core clocks. More...
static void	RFCClockSet (uint32_t ui32Mask)
	Enable some of the RF core clocks. More...
static void	RFCClockClear (uint32_t ui32Mask)
	Disable some of the RF core clocks. More...
static void	RFCCpe0IntEnable (uint32_t ui32Mask)
	Enable CPE0 interrupt. More...
static void	RFCCpe1IntEnable (uint32_t ui32Mask)
	Enable CPE1 interrupt. More...
static void	RFCHwIntEnable (uint32_t ui32Mask)
static void	RFCCpeIntDisable (uint32_t ui32Mask)
	Disable CPE interrupt. More...
static void	RFCHwIntDisable (uint32_t ui32Mask)
	Disable HW interrupt. More...
uint32_t	RFCCpeIntGetAndClear (void)
	Get and clear CPE interrupt flags. More...
static void	RFCCpeIntClear (uint32_t ui32Mask)
	Clear interrupt flags. More...
static void	RFCHwIntClear (uint32_t ui32Mask)
	Clear interrupt flags. More...
static void	RFCAckIntClear (void)
	Clear interrupt flags. More...
uint32_t	RFCDoorbellSendTo (uint32_t pOp)
	Send command to doorbell and wait for ack. More...
void	RFCSynthPowerDown (void)
	Turn off synth, NOTE: Radio will no longer respond to commands! More...
void	RFCRfTrimRead (rfc_radioOp_t *pOpSetup, rfTrim_t *rfTrim)
	Read RF trim from flash using CM3. More...
void	RFCRfTrimSet (rfTrim_t *rfTrim)
	Write preloaded RF trim values to CM0. More...
void	RFCRTrim (rfc_radioOp_t *pOpSetup)
	Check Override RTrim vs FCFG RTrim. More...
void	RFCCPEPatchReset (void)
	Reset previously patched CPE RAM to a state where it can be patched again. More...
void	RFCAdi3VcoLdoVoltageMode (bool bEnable)
	Function to set VCOLDO reference to voltage mode. More...

Detailed Description

Function Documentation

static void RFCAckIntClear ( void  )

inlinestatic

Clear interrupt flags.

Referenced by RFCDoorbellSendTo().

{
  // Clear any pending interrupts.
  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0;
}

void RFCAdi3VcoLdoVoltageMode

(

bool

bEnable

)

Function to set VCOLDO reference to voltage mode.

{
    if (bEnable)
    {
        // First make sure the REFSYSCTL0 mux output is not further muxed out
        HWREGB(0x40086200) = 0x0;
        // Set the REFSYSCTL0 mux as desired for VCOLDO voltage mode
        HWREGB(ADI3_BASE + ADI_O_DIR + ADI_3_REFSYS_O_REFSYSCTL0) = ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V;
    }
    else
    {
        // Revert the mux override
        HWREGB(ADI3_BASE + ADI_O_DIR + ADI_3_REFSYS_O_REFSYSCTL0) = ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC;
    }
}

static void RFCClockClear ( uint32_t  ui32Mask )

inlinestatic

Disable some of the RF core clocks.

As soon as the RF core is started it will handle clock control autonomously. No check should be performed to check the clocks. Instead the radio can be ping'ed through the command interface.

When disabling clocks it is the programmers responsibility that the RF core clocks can be safely gated. I.e. the RF core should be safely 'parked'.

Returns

None

{
    //
    // Disable clocks
    //
    HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) &= ~ui32Mask;
}

static void RFCClockDisable ( void  )

inlinestatic

Disable the RF core clocks.

As soon as the RF core is started it will handle clock control autonomously. No check should be performed to check the clocks. Instead the radio can be ping'ed through the command interface.

When disabling clocks it is the programmers responsibility that the RF core clocks can be safely gated. I.e. the RF core should be safely 'parked'.

Returns

None

{
    // Disable all clocks
    HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0;
}

static void RFCClockEnable ( void  )

inlinestatic

Enable the RF core clocks.

As soon as the RF core is started it will handle clock control autonomously. No check should be performed to check the clocks. Instead the radio can be ping'ed through the command interface.

Returns

None

{
    // Enable all clocks
    HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) =
                                 RFC_PWR_PWMCLKEN_RFCTRC |
                                 RFC_PWR_PWMCLKEN_FSCA |
                                 RFC_PWR_PWMCLKEN_PHA |
                                 RFC_PWR_PWMCLKEN_RAT |
                                 RFC_PWR_PWMCLKEN_RFERAM |
                                 RFC_PWR_PWMCLKEN_RFE |
                                 RFC_PWR_PWMCLKEN_MDMRAM |
                                 RFC_PWR_PWMCLKEN_MDM |
                                 RFC_PWR_PWMCLKEN_CPERAM |
                                 RFC_PWR_PWMCLKEN_CPE |
                                 RFC_PWR_PWMCLKEN_RFC;
}

static void RFCClockSet ( uint32_t  ui32Mask )

inlinestatic

Enable some of the RF core clocks.

As soon as the RF core is started it will handle clock control autonomously. No check should be performed to check the clocks. Instead the radio can be ping'ed through the command interface.

Returns

None

{
    //
    // Enable clocks
    //
    HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) |= ui32Mask;
}

static void RFCCpe0IntEnable ( uint32_t  ui32Mask )

inlinestatic

Enable CPE0 interrupt.

{
  // Multiplex RF Core interrupts to CPE0 IRQ.
  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask;

  do
  {
    // Clear any pending interrupts.
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0;
  }while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) != 0x0);

  //  Enable the masked interrupts
  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask;
}

static void RFCCpe1IntEnable ( uint32_t  ui32Mask )

inlinestatic

Enable CPE1 interrupt.

{
  // Multiplex RF Core interrupts to CPE1 IRQ.
  HWREG( RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask;

  do
  {
    // Clear any pending interrupts.
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0;
  }while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) != 0x0);

  //  Enable the masked interrupts
  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask;
}

static void RFCCpeIntClear ( uint32_t  ui32Mask )

inlinestatic

Clear interrupt flags.

{
  do
  {
    // Clear interrupts that may now be pending
    HWREG(RFC_DBELL_BASE+RFC_DBELL_O_RFCPEIFG) = ~ui32Mask;
  }while (HWREG(RFC_DBELL_BASE+RFC_DBELL_O_RFCPEIFG) & ui32Mask);
}

static void RFCCpeIntDisable ( uint32_t  ui32Mask )

inlinestatic

Disable CPE interrupt.

{
  //  Disable the masked interrupts
  HWREG( RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN ) &= ~ui32Mask;
}

uint32_t RFCCpeIntGetAndClear

(

void

)

Get and clear CPE interrupt flags.

{
    uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE+RFC_DBELL_O_RFCPEIFG);

    do {
        HWREG(RFC_DBELL_BASE+RFC_DBELL_O_RFCPEIFG) = ~ui32Ifg;
    } while (HWREG(RFC_DBELL_BASE+RFC_DBELL_O_RFCPEIFG) & ui32Ifg);

    return (ui32Ifg);
}

void RFCCPEPatchReset

(

void

)

Reset previously patched CPE RAM to a state where it can be patched again.

{
    uint8_t *pPatchTab = (uint8_t *) (_CPERAM_START + _PARSER_PATCH_TAB_OFFSET);
    uint32_t *pIrqPatch = (uint32_t *) (_CPERAM_START + _IRQPATCH_OFFSET);

    memset(pPatchTab, 0xFF, _IRQPATCH_OFFSET - _PARSER_PATCH_TAB_OFFSET);

    int i;
    for (i = 0; i < sizeof(rfc_defaultIrqAddr)/sizeof(rfc_defaultIrqAddr[0]); i++)
    {
        pIrqPatch[i * 2 + 1] = rfc_defaultIrqAddr[i];
    }
}

uint32_t RFCDoorbellSendTo

(

uint32_t

pOp

)

Send command to doorbell and wait for ack.

{
    while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) != 0);

    RFCAckIntClear();

    HWREG(RFC_DBELL_BASE+RFC_DBELL_O_CMDR) = pOp;

    while(!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG));
    RFCAckIntClear();

    return(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDSTA));
}

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static void RFCHwIntClear ( uint32_t  ui32Mask )

inlinestatic

Clear interrupt flags.

{
  // Clear pending interrupts.
  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask;
}

static void RFCHwIntDisable ( uint32_t  ui32Mask )

inlinestatic

Disable HW interrupt.

{
  //  Disable the masked interrupts
  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask;
}

static void RFCHwIntEnable ( uint32_t  ui32Mask )

inlinestatic

This function is used to map only HW interrupts, and clears/unmasks them. These interrupts are then enabled.

{
  // Clear any pending interrupts.
  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = 0x0;

  //  Enable the masked interrupts
  HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask;
}

void RFCRfTrimRead	(	rfc_radioOp_t *	pOpSetup,
		rfTrim_t *	rfTrim
	)

Read RF trim from flash using CM3.

{
    int divider;
    // Check which setup command is used
    switch (pOpSetup->commandNo)
    {
    case CMD_RADIO_SETUP:
        divider = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->loDivider;
        break;
    case CMD_PROP_RADIO_DIV_SETUP:
        divider = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->loDivider;
        break;
    default:
        divider = 0; // Use 2.4 GHz
        break;
    }

    // Read trim from FCFG1
    pRfTrim->configIfAdc = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_IF_ADC);
    switch (divider)
    {
    case 5:
        pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV5);
        pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV5);
        pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV5)
                               & ~CONFIG_MISC_ADC_DIVIDER_BM) | (5U << CONFIG_MISC_ADC_DIVIDER);
        break;

    case 6:
        pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV6);
        pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV6);
        pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV6)
                               & ~CONFIG_MISC_ADC_DIVIDER_BM) | (6U << CONFIG_MISC_ADC_DIVIDER);
        break;

    case 10:
        pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV10);
        pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV10);
        pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV10)
                               & ~CONFIG_MISC_ADC_DIVIDER_BM) | (10U << CONFIG_MISC_ADC_DIVIDER);
        break;

    case 12:
        pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV12);
        pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV12);
        pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV12)
                               & ~CONFIG_MISC_ADC_DIVIDER_BM) | (12U << CONFIG_MISC_ADC_DIVIDER);
        break;

    case 15:
        pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV15);
        pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV15);
        pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV15)
                               & ~CONFIG_MISC_ADC_DIVIDER_BM) | (15U << CONFIG_MISC_ADC_DIVIDER);
        break;

    case 30:
        pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV30);
        pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV30);
        pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV30)
                               & ~CONFIG_MISC_ADC_DIVIDER_BM) | (30U << CONFIG_MISC_ADC_DIVIDER);
        break;

    default:
        pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND);
        pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH);
        // Make sure configMiscAdc is not 0 by setting an unused bit to 1
        pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC)
                               & ~CONFIG_MISC_ADC_DIVIDER_BM) | (2U << CONFIG_MISC_ADC_DIVIDER);
        break;
   }
}

void RFCRfTrimSet

(

rfTrim_t *

rfTrim

)

Write preloaded RF trim values to CM0.

{
    memcpy((void*)&HWREG(0x21000018), (void*)pRfTrim, sizeof(rfTrim_t));
}

void RFCRTrim

(

rfc_radioOp_t *

pOpSetup

)

Check Override RTrim vs FCFG RTrim.

{
    int32_t divider;
    uint32_t fcfg1_rtrim;
    uint32_t *pOverride;
    int32_t override_index;
    uint32_t override_value;
    uint32_t override_rtrim = 0;

    // Check which setup command is used
    switch (pOpSetup->commandNo)
    {
    case CMD_RADIO_SETUP:
        divider = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->loDivider;
        pOverride = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->pRegOverride;
        break;
    case CMD_PROP_RADIO_SETUP:
        divider = 2;
        pOverride = ((rfc_CMD_PROP_RADIO_SETUP_t *)pOpSetup)->pRegOverride;
        break;
    case CMD_PROP_RADIO_DIV_SETUP:
        divider = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->loDivider;
        pOverride = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->pRegOverride;
        break;
    default:
        return;
    }

    if (pOverride == 0)
    {
        //  Did not find override, return
        return;
    }


    // Search top 5 overrides for RTRIM
    for(override_index = 0; override_index < 5; override_index++)
    {
        override_value = pOverride[override_index];
        if((override_value & 0xFFFF) == 0x4038)
        {
            override_rtrim = (override_value & 0xF0000) >> 16;
            break;
        }
    }

    if (override_rtrim == 0)
    {
        //  Did not find override, return
        return;
    }

    // Read trim from FCFG1
    switch (divider)
    {
    case 2:
        fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC)
                       & FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_S;
        break;
    case 5:
        // Legacy
        fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_MISC_OTP_DATA)
                       & FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_M) >> FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_S;
        break;
    case 6:
        fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV6)
                       & FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_S;
        break;
    case 10:
        fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV10)
                       & FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_S;
        break;
    case 12:
        fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV12)
                       & FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_S;
        break;
    case 15:
        fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV15)
                       & FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_S;
        break;
    case 30:
        fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV30)
                       & FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_S;
        break;
    default:
        fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC)
                       & FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_S;
        break;
    }

    // Check for early samples
    if(fcfg1_rtrim == 0xF)
    {
        // set default
        switch (divider)
        {
        case 5:
        case 10:
        case 15:
        case 30:
            pOverride[override_index] = (override_value & 0xFFF0FFFF) | (0x7 << 16);
            break;
        case 2:
        case 6:
        case 12:
        default:
            pOverride[override_index] = (override_value & 0xFFF0FFFF) | (0x4 << 16);
            break;
        }
    }
    else
    {
        // Test Override vs FCFG1 limit.
        if(override_rtrim >= fcfg1_rtrim)
        {
            // Do nothing
            ;
        }
        else
        {
            // Set override to FCFG1 limit value
            pOverride[override_index] = (override_value & 0xFFF0FFFF) | (fcfg1_rtrim << 16);
        }
    }
}

void RFCSynthPowerDown

(

void

)

Turn off synth, NOTE: Radio will no longer respond to commands!

{
  // Disable CPE clock, enable FSCA clock. NOTE: Radio will no longer respond to commands!
  HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = (HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) & ~RFC_PWR_PWMCLKEN_CPE_M) | RFC_PWR_PWMCLKEN_FSCA_M;

  HWREG(RFC_RESERVED0) = 3;
  HWREG(RFC_RESERVED1) = 0x1030;
  HWREG(RFC_RESERVED2) = 1;
  HWREG(RFC_RESERVED1) = 0x50;
  HWREG(RFC_RESERVED2) = 1;
  HWREG(RFC_RESERVED1) = 0x650;
  HWREG(RFC_RESERVED2) = 1;
  HWREG(RFC_RESERVED3) = 1;

}