BLE-Stack APIs
3.00.01
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PDMCC26XX_I2S Audio Clock configuration. More...
Data Fields | |
uint16_t | bclkDiv:10 |
uint16_t | bclkSource:1 |
uint16_t | mclkDiv:10 |
uint16_t | reserved:5 |
uint16_t | sampleOnPositiveEdge:1 |
uint16_t | wclkDiv |
uint16_t | wclkInverted:1 |
uint16_t | wclkPhase:2 |
uint16_t | wclkSource:2 |
PDMCC26XX_I2S Audio Clock configuration.
These fields are used by the driver to set up the I2S module
A sample structure is shown below (single PDM microphone):
uint16_t bclkDiv |
I2S Bit Clock divider override
uint16_t bclkSource |
I2S Bit Clock source (PDMCC26XX_I2S_BitClockSource_Ext or PDMCC26XX_I2S_BitClockSource_Int)
uint16_t mclkDiv |
I2S Master Clock divider override
uint16_t reserved |
Reserved bit field
uint16_t sampleOnPositiveEdge |
I2S Sample Edge. 0 - data and WCLK are sampled on the negative edge and clocked out on the positive edge. 1 - data and WCLK are sampled on the positive edge and clocked out on the negative edge
uint16_t wclkDiv |
I2S Word Clock divider override
uint16_t wclkInverted |
I2S Invert Word Clock (PDMCC26XX_I2S_ClockSource_Inverted or PDMCC26XX_I2S_ClockSource_Normal)
uint16_t wclkPhase |
I2S Word Clock Phase(PDMCC26XX_I2S_WordClockPhase_Dual, PDMCC26XX_I2S_WordClockPhase_Single or PDMCC26XX_I2S_WordClockPhase_UserDefined)
uint16_t wclkSource |
I2S Word Clock source (PDMCC26XX_I2S_WordClockSource_Ext or PDMCC26XX_I2S_WordClockSource_Int)