[crypto] Crypto

Functions
uint32_t	CRYPTOAesLoadKey (uint32_t *pui32AesKey, uint32_t ui32KeyLocation)
	Write the key into the Key Ram. More...
uint32_t	CRYPTOAesCbc (uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength, uint32_t *pui32Nonce, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable)
	Start an AES-CBC operation (encryption or decryption). More...
uint32_t	CRYPTOAesCbcStatus (void)
	Check the result of an AES CBC operation. More...
uint32_t	CRYPTOAesEcb (uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable)
	Start an AES-ECB operation (encryption or decryption). More...
uint32_t	CRYPTOAesEcbStatus (void)
	Check the result of an AES ECB operation. More...
static void	CRYPTOAesEcbFinish (void)
	Finish the encryption operation by resetting the operation mode. More...
static void	CRYPTOAesCbcFinish (void)
	Finish the encryption operation by resetting the operation mode. More...
uint32_t	CRYPTOCcmAuthEncrypt (bool bEncrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32PlainText, uint32_t ui32PlainTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable)
	Start CCM operation. More...
uint32_t	CRYPTOCcmAuthEncryptStatus (void)
	Check the result of an AES CCM operation. More...
uint32_t	CRYPTOCcmAuthEncryptResultGet (uint32_t ui32TagLength, uint32_t *pui32CcmTag)
	Get the result of an AES CCM operation. More...
uint32_t	CRYPTOCcmInvAuthDecrypt (bool bDecrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable)
	Start a CCM Decryption and Inverse Authentication operation. More...
uint32_t	CRYPTOCcmInvAuthDecryptStatus (void)
	Checks CCM decrypt and Inverse Authentication result. More...
uint32_t	CRYPTOCcmInvAuthDecryptResultGet (uint32_t ui32AuthLength, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32CcmTag)
	Get the result of the CCM operation. More...
static uint32_t	CRYPTODmaStatus (void)
	Get the current status of the Crypto DMA controller. More...
void	CRYPTODmaEnable (uint32_t ui32Channels)
	Enable Crypto DMA operation. More...
void	CRYPTODmaDisable (uint32_t ui32Channels)
	Disable Crypto DMA operation. More...
static void	CRYPTOIntEnable (uint32_t ui32IntFlags)
	Enables individual Crypto interrupt sources. More...
static void	CRYPTOIntDisable (uint32_t ui32IntFlags)
	Disables individual CRYPTO interrupt sources. More...
static uint32_t	CRYPTOIntStatus (bool bMasked)
	Gets the current interrupt status. More...
static void	CRYPTOIntClear (uint32_t ui32IntFlags)
	Clears Crypto interrupt sources. More...
static void	CRYPTOIntRegister (void(*pfnHandler)(void))
	Registers an interrupt handler for a Crypto interrupt. More...
static void	CRYPTOIntUnregister (void)
	Unregisters an interrupt handler for a Crypto interrupt. More...

Detailed Description

Function Documentation

uint32_t CRYPTOAesCbc	(	uint32_t *	pui32MsgIn,
		uint32_t *	pui32MsgOut,
		uint32_t	ui32MsgLength,
		uint32_t *	pui32Nonce,
		uint32_t	ui32KeyLocation,
		bool	bEncrypt,
		bool	bIntEnable
	)

Start an AES-CBC operation (encryption or decryption).

The function starts an AES CBC mode encypt or decrypt operation. End operation can be deteced by enabling interrupt or by polling CRYPTOAesCbcStatus(). Result of operation is returned by CRYPTOAesCbcStatus().

Parameters

pui32MsgIn	is a pointer to the input data.
pui32MsgOut	is a pointer to the output data.
ui32MsgLength	is the length in bytes of the input data.
pui32Nonce	is a pointer to 16-byte Nonce.
ui32KeyLocation	is the location of the key in Key RAM. This parameter can have any of the following values: CRYPTO_KEY_AREA_0 CRYPTO_KEY_AREA_1 CRYPTO_KEY_AREA_2 CRYPTO_KEY_AREA_3 CRYPTO_KEY_AREA_4 CRYPTO_KEY_AREA_5 CRYPTO_KEY_AREA_6 CRYPTO_KEY_AREA_7
bEncrypt	is set true to encrypt or set false to decrypt.
bIntEnable	is set true to enable Crypto interrupts or false to disable Crypto interrupt.

Returns

Returns status of the AES-CBC operation:

• AES_SUCCESS
• AES_KEYSTORE_READ_ERROR

See also

CRYPTOAesCbcStatus()

{
    uint32_t ui32CtrlVal;

    // Enable internal interrupts.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;

    // Clear any outstanding interrupts.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
                                            CRYPTO_IRQCLR_RESULT_AVAIL);

    // Wait for interrupt lines from module to be cleared
    while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));

    // If using interrupts clear any pending interrupts and enable interrupts
    // for the Crypto module.
    if(bIntEnable)
    {
        IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
        IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
    }

    // Configure Master Control module.
    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;

    // Enable keys to read (e.g. Key 0).
    HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;

    //Wait until key is loaded to the AES module.
    do
    {
        CPUdelay(1);
    }
    while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));

    // Check for Key store Read error.
    if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
    {
        return (AES_KEYSTORE_READ_ERROR);
    }

    // Write initialization vector.
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = pui32Nonce[0];
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = pui32Nonce[1];
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = pui32Nonce[2];
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = pui32Nonce[3];

    // Configure AES engine for AES-CBC with 128-bit key size.
    ui32CtrlVal  = (CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CBC);
    if(bEncrypt)
    {
        ui32CtrlVal |= CRYPTO_AES128_ENCRYPT;
    }
    else
    {
        ui32CtrlVal |= CRYPTO_AES128_DECRYPT;
    }
    HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal;

    // Write the length of the crypto block (plain text).
    // Low and high part (high part is assumed to be always 0).
    HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32MsgLength;
    HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
    HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN)  = 0;

    // Enable Crypto DMA channel 0.
    HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;

    // Base address of the input data in ext. memory.
    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn;

    // Input data length in bytes, equal to the message.
    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32MsgLength;

    // Enable Crypto DMA channel 1.
    HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;

    // Set up the address and length of the output data.
    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut;
    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32MsgLength;

    // Return success
    return AES_SUCCESS;
}

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static void CRYPTOAesCbcFinish ( void  )

inlinestatic

Finish the encryption operation by resetting the operation mode.

This function should be called after CRYPTOAesCbcStatus() has reported that the operation is finished successfully.

Returns

None

See also

CRYPTOAesCbcStatus()

{
    // Result has already been copied to the output buffer by DMA.
    // Disable master control/DMA clock and clear the operating mode.
    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
    HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000;
}

uint32_t CRYPTOAesCbcStatus

(

void

)

Check the result of an AES CBC operation.

This function should be called after CRYPTOAesCbc() function to check if the AES CBC operation was successful.

Returns

Returns the status of the AES CBC operation:

• AES_SUCCESS : Successful.
• AES_DMA_BUS_ERROR : Failed.
• AES_DMA_BSY : Operation is ongoing.

See also

CRYPTOAesCbc()

{
    return(CRYPTOAesEcbStatus());
}

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uint32_t CRYPTOAesEcb	(	uint32_t *	pui32MsgIn,
		uint32_t *	pui32MsgOut,
		uint32_t	ui32KeyLocation,
		bool	bEncrypt,
		bool	bIntEnable
	)

Start an AES-ECB operation (encryption or decryption).

The ui32KeyLocation parameter is an enumerated type which specifies the Key Ram location in which the key is stored.

Parameters

pui32MsgIn	is a pointer to the input data.
pui32MsgOut	is a pointer to the output data.
ui32KeyLocation	is the location of the key in Key RAM. This parameter can have any of the following values: CRYPTO_KEY_AREA_0 CRYPTO_KEY_AREA_1 CRYPTO_KEY_AREA_2 CRYPTO_KEY_AREA_3 CRYPTO_KEY_AREA_4 CRYPTO_KEY_AREA_5 CRYPTO_KEY_AREA_6 CRYPTO_KEY_AREA_7
bEncrypt	is set true to encrypt or set false to decrypt.
bIntEnable	is set true to enable Crypto interrupts or false to disable Crypto interrupt.

Returns

Returns status of the AES-ECB operation:

• AES_SUCCESS
• AES_KEYSTORE_READ_ERROR

See also

CRYPTOAesEcbStatus()

{
    // Enable internal interrupts.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;

    // Clear any outstanding interrupts.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
                                            CRYPTO_IRQCLR_RESULT_AVAIL);

    // Wait for interrupt lines from module to be cleared
    while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));

    // If using interrupts clear any pending interrupts and enable interrupts
    // for the Crypto module.
    if(bIntEnable)
    {
        IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
        IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
    }

    // Configure Master Control module.
    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;

    // Enable keys to read (e.g. Key 0).
    HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;

    //Wait until key is loaded to the AES module.
    do
    {
        CPUdelay(1);
    }
    while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));

    // Check for Key store Read error.
    if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
    {
        return (AES_KEYSTORE_READ_ERROR);
    }

    // Configure AES engine (program AES-ECB-128 encryption and no
    // initialization vector - IV).
    if(bEncrypt)
    {
        HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_ENCRYPT;
    }
    else
    {
        HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_DECRYPT;
    }

    // Write the length of the data.
    HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = AES_ECB_LENGTH;
    HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;

    // Enable Crypto DMA channel 0.
    HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;

    // Base address of the input data in ext. memory.
    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn;

    // Input data length in bytes, equal to the message.
    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = AES_ECB_LENGTH;

    // Enable Crypto DMA channel 1.
    HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;

    // Set up the address and length of the output data.
    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut;
    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = AES_ECB_LENGTH;

    // Return success
    return AES_SUCCESS;
}

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static void CRYPTOAesEcbFinish ( void  )

inlinestatic

Finish the encryption operation by resetting the operation mode.

This function should be called after CRYPTOAesEcbStatus() has reported that the operation is finished successfully.

Returns

None

See also

CRYPTOAesEcbStatus()

{
    // Result has already been copied to the output buffer by DMA.
    // Disable master control/DMA clock and clear the operating mode.
    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
    HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000;
}

uint32_t CRYPTOAesEcbStatus

(

void

)

Check the result of an AES ECB operation.

This function should be called after CRYPTOAesEcb() function to check if the AES ECB operation was successful.

Returns

Returns the status of the AES ECB operation:

• AES_SUCCESS : Successful.
• AES_DMA_BUS_ERROR : Failed.
• AES_DMA_BSY : Operation is ongoing.

See also

CRYPTOAesEcb()

Referenced by CRYPTOAesCbcStatus().

{
    uint32_t ui32Status;

    // Get the current DMA status.
    ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT);

    // Check if DMA is still busy.
    if(ui32Status & CRYPTO_DMA_BSY)
    {
        return (AES_DMA_BSY);
    }

    // Check the status of the DMA operation - return error if not success.
    if(ui32Status & CRYPTO_DMA_BUS_ERROR)
    {
        return (AES_DMA_BUS_ERROR);
    }

    // Operation successful - disable interrupt and return success.
    IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
    return (AES_SUCCESS);
}

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uint32_t CRYPTOAesLoadKey	(	uint32_t *	pui32AesKey,
		uint32_t	ui32KeyLocation
	)

Write the key into the Key Ram.

The ui32KeyLocation parameter is an enumerated type which specifies the Key Ram location in which the key is stored.

The pointer pui8AesKey has the address where the Key is stored.

Parameters

pui32AesKey	is a pointer to an AES Key.
ui32KeyLocation	is the location of the key in Key RAM. This parameter can have any of the following values: CRYPTO_KEY_AREA_0 CRYPTO_KEY_AREA_1 CRYPTO_KEY_AREA_2 CRYPTO_KEY_AREA_3 CRYPTO_KEY_AREA_4 CRYPTO_KEY_AREA_5 CRYPTO_KEY_AREA_6 CRYPTO_KEY_AREA_7

Returns

Returns status of the function:

• AES_SUCCESS
• AES_KEYSTORE_READ_ERROR

{
    // Check the arguments.
    ASSERT((ui32KeyLocation == CRYPTO_KEY_AREA_0) |
           (ui32KeyLocation == CRYPTO_KEY_AREA_1) |
           (ui32KeyLocation == CRYPTO_KEY_AREA_2) |
           (ui32KeyLocation == CRYPTO_KEY_AREA_3) |
           (ui32KeyLocation == CRYPTO_KEY_AREA_4) |
           (ui32KeyLocation == CRYPTO_KEY_AREA_5) |
           (ui32KeyLocation == CRYPTO_KEY_AREA_6) |
           (ui32KeyLocation == CRYPTO_KEY_AREA_7));

    // Disable the external interrupt to stop the interrupt form propagating
    // from the module to the System CPU.
    IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);

    // Enable internal interrupts.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |
                                          CRYPTO_IRQEN_RESULT_AVAIL;

    // Configure master control module.
    HWREGBITW(CRYPTO_BASE + CRYPTO_O_ALGSEL, CRYPTO_ALGSEL_KEY_STORE_BITN) = 1;

    // Clear any outstanding events.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
                                            CRYPTO_IRQCLR_RESULT_AVAIL);

    // Configure key store module for 128 bit operation.
    HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) &= ~CRYPTO_KEYSIZE_SIZE_M;
    HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) |= KEY_STORE_SIZE_128;

    // Enable keys to write (e.g. Key 0).
    HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation);

    // Enable Crypto DMA channel 0.
    HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;

    // Base address of the key in ext. memory.
    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey;

    // Total key length in bytes (e.g. 16 for 1 x 128-bit key).
    // Writing the length of the key enables the DMA operation.
    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = KEY_BLENGTH;

    // Wait for the DMA operation to complete.
    do
    {
        CPUdelay(1);
    }
    while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & 0x00000001));

    // Check for errors in DMA and key store.
    if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) &
            (CRYPTO_IRQSTAT_DMA_BUS_ERR |
             CRYPTO_IRQSTAT_KEY_ST_WR_ERR)) == 0)
    {
        // Acknowledge/clear the interrupt and disable the master control.
        HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
                                                CRYPTO_IRQCLR_RESULT_AVAIL);
        HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;

        // Check status, if error return error code.
        if(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) != (0x00000001 << ui32KeyLocation))
        {
            return (AES_KEYSTORE_READ_ERROR);
        }
    }

    // Return success.
    return (AES_SUCCESS);
}

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uint32_t CRYPTOCcmAuthEncrypt	(	bool	bEncrypt,
		uint32_t	ui32AuthLength,
		uint32_t *	pui32Nonce,
		uint32_t *	pui32PlainText,
		uint32_t	ui32PlainTextLength,
		uint32_t *	pui32Header,
		uint32_t	ui32HeaderLength,
		uint32_t	ui32KeyLocation,
		uint32_t	ui32FieldLength,
		bool	bIntEnable
	)

Start CCM operation.

The ui32KeyLocation is an enumerated type which specifies the Key Ram location in which the key is stored.

Parameters

bEncrypt	determines whether to run encryption or not.
ui32AuthLength	is the the length of the authentication field - 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets.
pui32Nonce	is a pointer to 13-byte or 12-byte Nonce (Number used once).
pui32PlainText	is a pointer to the octet string input message.
ui32PlainTextLength	is the length of the message.
pui32Header	is the length of the header (Additional Authentication Data or AAD).
ui32HeaderLength	is the length of the header in octets.
ui32KeyLocation	is the location in Key RAM where the key is stored. This parameter can have any of the following values: CRYPTO_KEY_AREA_0 CRYPTO_KEY_AREA_1 CRYPTO_KEY_AREA_2 CRYPTO_KEY_AREA_3 CRYPTO_KEY_AREA_4 CRYPTO_KEY_AREA_5 CRYPTO_KEY_AREA_6 CRYPTO_KEY_AREA_7
ui32FieldLength	is the size of the length field (2 or 3).
bIntEnable	enables interrupts.

Returns

Returns the status of the CCM operation

• AES_SUCCESS
• AES_KEYSTORE_READ_ERROR
• AES_DMA_BUS_ERROR

See also

CRYPTOCcmAuthEncryptStatus()

{
    uint32_t ui32CtrlVal;
    uint32_t i;
    uint32_t *pui32CipherText;
    union {
        uint32_t w[4];
        uint8_t  b[16];
    } ui8InitVec;

    // Input address for the encryption engine is the same as the output.
    pui32CipherText = pui32PlainText;

    // Disable global interrupt, enable local interrupt and clear any pending
    // interrupts.
    IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
                                            CRYPTO_IRQCLR_RESULT_AVAIL);

    // Enable internal interrupts.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |
                                          CRYPTO_IRQEN_RESULT_AVAIL;

    // Configure master control module for AES operation.
    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;

    // Enable keys to read (e.g. Key 0).
    HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;

    // Wait until key is loaded to the AES module.
    do
    {
        CPUdelay(1);
    }
    while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));

    // Check for Key store Read error.
    if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
    {
        return (AES_KEYSTORE_READ_ERROR);
    }

    // Prepare the initialization vector (IV),
    // Length of Nonce l(n) = 15 - ui32FieldLength.
    ui8InitVec.b[0] = ui32FieldLength - 1;
    for(i = 0; i < 12; i++)
    {
        ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i];
    }
    if(ui32FieldLength == 2)
    {
        ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12];
    }
    else
    {
        ui8InitVec.b[13] = 0;
    }
    ui8InitVec.b[14] = 0;
    ui8InitVec.b[15] = 0;

    // Write initialization vector.
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0];
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1];
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2];
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3];

    // Configure AES engine.
    ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S);
    if ( ui32AuthLength >= 2 ) {
        ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S );
    }
    ui32CtrlVal |= CRYPTO_AESCTL_CCM;
    ui32CtrlVal |= CRYPTO_AESCTL_CTR;
    ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT;
    ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S);
    ui32CtrlVal |= (1 << CRYPTO_AESCTL_DIR_S);
    ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S);

    // Write the configuration for 128 bit AES-CCM.
    HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal;

    // Write the length of the crypto block (plain text).
    // Low and high part (high part is assumed to be always 0).
    HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32PlainTextLength;
    HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1)  =  0;

    // Write the length of the header field.
    // Also called AAD - Additional Authentication Data.
    HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength;

    // Check if any header information (AAD).
    // If so configure the DMA controller to fetch the header.
    if(ui32HeaderLength != 0)
    {
        // Enable DMA channel 0.
        HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;

        // Register the base address of the header (AAD).
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header;

        // Header length in bytes (may be non-block size aligned).
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength;

        // Wait for completion of the header data transfer, DMA_IN_DONE.
        do
        {
            CPUdelay(1);
        }
        while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE));

        // Check for DMA errors.
        if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR)
        {
            return AES_DMA_BUS_ERROR;
        }
    }

    // Clear interrupt status.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
                                            CRYPTO_IRQCLR_RESULT_AVAIL);

    // Wait for interrupt lines from module to be cleared
    while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));

    // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only
    // want interrupt to trigger once RESULT_AVAIL occurs.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE;


    // Is using interrupts enable globally.
    if(bIntEnable)
    {
        IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
        IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
    }

    // Enable interrupts locally.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;

    // Perform encryption if requested.
    if(bEncrypt)
    {
        // Enable DMA channel 0
        HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;

        // base address of the payload data in ext. memory.
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) =
            (uint32_t)pui32PlainText;

        // Enable DMA channel 1
        HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;

        // Base address of the output data buffer.
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) =
            (uint32_t)pui32CipherText;

        // Payload data length in bytes, equal to the plaintext length.
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32PlainTextLength;
        // Output data length in bytes, equal to the plaintext length.
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32PlainTextLength;
    }

    return AES_SUCCESS;
}

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uint32_t CRYPTOCcmAuthEncryptResultGet	(	uint32_t	ui32TagLength,
		uint32_t *	pui32CcmTag
	)

Get the result of an AES CCM operation.

This function should be called after CRYPTOCcmAuthEncryptStatus().

Parameters

ui32TagLength	is length of the Tag.
pui32CcmTag	is the location of the authentication Tag.

Returns

Returns AES_SUCCESS if successful.

See also

CRYPTOCcmAuthEncryptStatus()

Get the result of an AES CCM operation.

{
    uint32_t volatile ui32Tag[4];
    uint32_t ui32Idx;

    // Result has already been copied to the output buffer by DMA
    // Disable master control.
    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;

    // Read tag - wait for the context ready bit.
    do
    {
        CPUdelay(1);
    }
    while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) &
            CRYPTO_AESCTL_SAVED_CONTEXT_RDY));

    // Read the Tag registers.
    ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0);
    ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1);
    ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2);
    ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3);

    for(ui32Idx = 0; ui32Idx < ui32TagLength ; ui32Idx++)
    {
        *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx);
    }

    // Operation successful -  clear interrupt status.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
                                            CRYPTO_IRQCLR_RESULT_AVAIL);
    return AES_SUCCESS;
}

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uint32_t CRYPTOCcmAuthEncryptStatus

(

void

)

Check the result of an AES CCM operation.

This function should be called after CRYPTOCcmAuthEncrypt() function to check if the AES CCM operation was successful.

Returns

Returns the status of the AES CCM operation:

• AES_SUCCESS : Successful.
• AES_DMA_BUS_ERROR : Failed.
• AES_DMA_BSY : Operation is ongoing.

See also

CRYPTOCcmAuthEncrypt()

{
    uint32_t ui32Status;

    // Get the current DMA status.
    ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT);

    // Check if DMA is still busy.
    if(ui32Status & CRYPTO_DMA_BSY)
    {
        return (AES_DMA_BSY);
    }

    // Check the status of the DMA operation - return error if not success.
    if(ui32Status & CRYPTO_DMA_BUS_ERROR)
    {
        return (AES_DMA_BUS_ERROR);
    }

    // Operation successful - disable interrupt and return success.
    IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
    return (AES_SUCCESS);
}

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uint32_t CRYPTOCcmInvAuthDecrypt	(	bool	bDecrypt,
		uint32_t	ui32AuthLength,
		uint32_t *	pui32Nonce,
		uint32_t *	pui32CipherText,
		uint32_t	ui32CipherTextLength,
		uint32_t *	pui32Header,
		uint32_t	ui32HeaderLength,
		uint32_t	ui32KeyLocation,
		uint32_t	ui32FieldLength,
		bool	bIntEnable
	)

Start a CCM Decryption and Inverse Authentication operation.

The ui32KeyLocation is an enumerated type which specifies the Key Ram location in which the key is stored.

Parameters

bDecrypt	determines whether to run decryption or not.
ui32AuthLength	is the the length of the authentication field - 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets.
pui32Nonce	is a pointer to 13-byte or 12-byte Nonce (Number used once).
pui32CipherText	is a pointer to the octet string encrypted message.
ui32CipherTextLength	is the length of the encrypted message.
pui32Header	is the length of the header (Additional Authentication Data or AAD).
ui32HeaderLength	is the length of the header in octets.
ui32KeyLocation	is the location in Key RAM where the key is stored. This parameter can have any of the following values: CRYPTO_KEY_AREA_0 CRYPTO_KEY_AREA_1 CRYPTO_KEY_AREA_2 CRYPTO_KEY_AREA_3 CRYPTO_KEY_AREA_4 CRYPTO_KEY_AREA_5 CRYPTO_KEY_AREA_6 CRYPTO_KEY_AREA_7
ui32FieldLength	is the size of the length field (2 or 3).
bIntEnable	enables interrupts.

Returns

Returns the status of the operation:

• AES_SUCCESS
• AES_KEYSTORE_READ_ERROR
• AES_DMA_BUS_ERROR

{
    uint32_t ui32CtrlVal;
    uint32_t i;
    uint32_t *pui32PlainText;
    uint32_t ui32CryptoBlockLength;
    union {
        uint32_t w[4];
        uint8_t  b[16];
    } ui8InitVec;

    // Input address for the encryption engine is the same as the output.
    pui32PlainText = pui32CipherText;

    // Disable global interrupt, enable local interrupt and clear any pending.
    // interrupts.
    IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
                                            CRYPTO_IRQCLR_RESULT_AVAIL);
    // Enable internal interrupts.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |
                                          CRYPTO_IRQEN_RESULT_AVAIL;

    // Configure master control module for AES operation.
    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;

    // Enable keys to read (e.g. Key 0).
    HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;

    // Wait until key is loaded to the AES module.
    do
    {
        CPUdelay(1);
    }
    while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));

    // Check for Key store Read error.
    if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
    {
        return (AES_KEYSTORE_READ_ERROR);
    }

    // Prepare the initialization vector (IV),
    // Length of Nonce l(n) = 15 - ui32FieldLength.
    ui8InitVec.b[0] = ui32FieldLength - 1;
    for(i = 0; i < 12; i++)
    {
        ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i];
    }
    if(ui32FieldLength == 2)
    {
        ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12];
    }
    else
    {
        ui8InitVec.b[13] = 0;
    }
    ui8InitVec.b[14] = 0;
    ui8InitVec.b[15] = 0;

    // Write initialization vector.
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0];
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1];
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2];
    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3];

    // Configure AES engine
    ui32CryptoBlockLength = ui32CipherTextLength - ui32AuthLength;
    ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S);
    if ( ui32AuthLength >= 2 ) {
        ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S );
    }
    ui32CtrlVal |= CRYPTO_AESCTL_CCM;
    ui32CtrlVal |= CRYPTO_AESCTL_CTR;
    ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT;
    ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S);
    ui32CtrlVal |= (0 << CRYPTO_AESCTL_DIR_S);
    ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S);

    // Write the configuration for 128 bit AES-CCM.
    HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal;

    // Write the length of the crypto block (plain text).
    // Low and high part (high part is assumed to be always 0).
    HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32CryptoBlockLength;
    HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1)  =  0;

    // Write the length of the header field.
    // Also called AAD - Additional Authentication Data.
    HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength;

    // Check if any header information (AAD).
    // If so configure the DMA controller to fetch the header.
    if(ui32HeaderLength != 0)
    {
        // Enable DMA channel 0.
        HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;

        // Register the base address of the header (AAD).
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header;

        // Header length in bytes (may be non-block size aligned).
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength;

        // Wait for completion of the header data transfer, DMA_IN_DONE.
        do
        {
            CPUdelay(1);
        }
        while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE));

        // Check for DMA errors.
        if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR)
        {
            return AES_DMA_BUS_ERROR;
        }
    }

    // Clear interrupt status.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
                                            CRYPTO_IRQCLR_RESULT_AVAIL);

    // Wait for interrupt lines from module to be cleared
    while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));

    // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only
    // want interrupt to trigger once RESULT_AVAIL occurs.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE;

    // Is using interrupts - clear and enable globally.
    if(bIntEnable)
    {
        IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
        IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
    }

    // Enable internal interrupts.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;

    // Perform decryption if requested.
    if(bDecrypt)
    {
        // Configure the DMA controller - enable both DMA channels.
        HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;

        // Base address of the payload data in ext. memory.
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) =
            (uint32_t)pui32CipherText;

        // Payload data length in bytes, equal to the cipher text length.
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32CryptoBlockLength;

        // Enable DMA channel 1.
        HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;

        // Base address of the output data buffer.
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) =
            (uint32_t)pui32PlainText;

        // Output data length in bytes, equal to the cipher text length.
        HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32CryptoBlockLength;
    }

    return AES_SUCCESS;
}

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uint32_t CRYPTOCcmInvAuthDecryptResultGet	(	uint32_t	ui32AuthLength,
		uint32_t *	pui32CipherText,
		uint32_t	ui32CipherTextLength,
		uint32_t *	pui32CcmTag
	)

Get the result of the CCM operation.

Parameters

ui32AuthLength	is the the length of the authentication field - 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets.
pui32CipherText	is a pointer to the octet string encrypted message.
ui32CipherTextLength	is the length of the encrypted message.
pui32CcmTag	is the location of the authentication Tag.

Returns

Returns AES_SUCCESS if successful.

{
    uint32_t volatile ui32Tag[4];
    uint32_t ui32TagIndex;
    uint32_t i;
    uint32_t ui32Idx;

    ui32TagIndex = ui32CipherTextLength - ui32AuthLength;

    // Result has already been copied to the output buffer by DMA
    // Disable master control.
    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;

    // Read tag - wait for the context ready bit.
    do
    {
        CPUdelay(1);
    }
    while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) &
            CRYPTO_AESCTL_SAVED_CONTEXT_RDY));

    // Read the Tag registers.
    ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0);
    ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1);
    ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2);
    ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3);

    for(ui32Idx = 0; ui32Idx < ui32AuthLength ; ui32Idx++)
    {
        *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx);
    }

    // Operation successful -  clear interrupt status.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
                                            CRYPTO_IRQCLR_RESULT_AVAIL);

    // Verify the Tag.
    for(i = 0; i < ui32AuthLength; i++)
    {
        if(*((uint8_t *)pui32CcmTag + i) !=
            (*((uint8_t *)pui32CipherText + ui32TagIndex + i)))
        {
            return CCM_AUTHENTICATION_FAILED;
        }
    }

    return AES_SUCCESS;
}

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uint32_t CRYPTOCcmInvAuthDecryptStatus

(

void

)

Checks CCM decrypt and Inverse Authentication result.

Returns

Returns status of operation:

• AES_SUCCESS : Operation was successful.
• AES_DMA_BSY : Operation is busy.
• AES_DMA_BUS_ERROR : An error is encountered.

{
    uint32_t ui32Status;

    // Get the current DMA status.
    ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT);

    // Check if DMA is still busy.
    if(ui32Status & CRYPTO_DMA_BSY)
    {
        return (AES_DMA_BSY);
    }

    // Check the status of the DMA operation - return error if not success.
    if(ui32Status & CRYPTO_DMA_BUS_ERROR)
    {
        return (AES_DMA_BUS_ERROR);
    }

    // Operation successful - disable interrupt and return success
    IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
    return (AES_SUCCESS);
}

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void CRYPTODmaDisable

(

uint32_t

ui32Channels

)

Disable Crypto DMA operation.

The specified Crypto DMA channels are disabled.

Parameters

ui32Channels

is a bitwise OR of the channels to disable. CRYPTO_DMA_CHAN0 CRYPTO_DMA_CHAN1

Returns

None

{
    // Check the arguments.
    ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) |
           (ui32Channels & CRYPTO_DMA_CHAN1));

    // Enable the selected channels.
    if(ui32Channels & CRYPTO_DMA_CHAN0)
    {
        HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 0;
    }
    if(ui32Channels & CRYPTO_DMA_CHAN1)
    {
        HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 0;
    }
}

void CRYPTODmaEnable

(

uint32_t

ui32Channels

)

Enable Crypto DMA operation.

The specified Crypto DMA channels are enabled.

Parameters

ui32Channels

is a bitwise OR of the channels to enable. CRYPTO_DMA_CHAN0 CRYPTO_DMA_CHAN1

Returns

None

{
    // Check the arguments.
    ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) |
           (ui32Channels & CRYPTO_DMA_CHAN1));

    // Enable the selected channels,
    if(ui32Channels & CRYPTO_DMA_CHAN0)
    {
        HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
    }
    if(ui32Channels & CRYPTO_DMA_CHAN1)
    {
        HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
    }
}

static uint32_t CRYPTODmaStatus ( void  )

inlinestatic

Get the current status of the Crypto DMA controller.

This function is used to poll the Crypto DMA controller to check if it is ready for a new operation or if an error has occurred.

The CRYPTO_DMA_BUS_ERROR can also be caught using the crypto event handler.

Returns

Returns the current status of the DMA controller:

• CRYPTO_DMA_READY : DMA ready for a new operation
• CRYPTO_DMA_BSY : DMA is busy
• CRYPTO_DMA_BUS_ERROR : DMA Bus error

{
    // Return the value of the status register.
    return (HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT));
}

static void CRYPTOIntClear ( uint32_t  ui32IntFlags )

inlinestatic

Clears Crypto interrupt sources.

The specified Crypto interrupt sources are cleared, so that they no longer assert. This function must be called in the interrupt handler to keep the interrupt from being recognized again immediately upon exit.

Note

Due to write buffers and synchronizers in the system it may take several clock cycles from a register write clearing an event in a module and until the event is actually cleared in the NVIC of the system CPU. It is recommended to clear the event source early in the interrupt service routine (ISR) to allow the event clear to propagate to the NVIC before returning from the ISR. At the same time, an early event clear allows new events of the same type to be pended instead of ignored if the event is cleared later in the ISR. It is the responsibility of the programmer to make sure that enough time has passed before returning from the ISR to avoid false re-triggering of the cleared event. A simple, although not necessarily optimal, way of clearing an event before returning from the ISR is:

1. Write to clear event (interrupt source). (buffered write)
2. Dummy read from the event source module. (making sure the write has propagated)
3. Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)

Parameters

ui32IntFlags

is a bit mask of the interrupt sources to be cleared. CRYPTO_DMA_IN_DONE CRYPTO_RESULT_RDY

Returns

None

{
    // Check the arguments.
    ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) |
           (ui32IntFlags & CRYPTO_RESULT_RDY));

    // Clear the requested interrupt sources,
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = ui32IntFlags;
}

static void CRYPTOIntDisable ( uint32_t  ui32IntFlags )

inlinestatic

Disables individual CRYPTO interrupt sources.

This function disables the indicated Crypto interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt. Disabled sources have no effect on the processor.

Parameters

ui32IntFlags

is the bitwise OR of the interrupt sources to be enabled. CRYPTO_DMA_IN_DONE CRYPTO_RESULT_RDY

Returns

None

{
    // Check the arguments.
    ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) |
           (ui32IntFlags & CRYPTO_RESULT_RDY));

    // Disable the specified interrupts.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~ui32IntFlags;
}

static void CRYPTOIntEnable ( uint32_t  ui32IntFlags )

inlinestatic

Enables individual Crypto interrupt sources.

This function enables the indicated Crypto interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt. Disabled sources have no effect on the processor.

Parameters

ui32IntFlags

is the bitwise OR of the interrupt sources to be enabled. CRYPTO_DMA_IN_DONE CRYPTO_RESULT_RDY

Returns

None

{
    // Check the arguments.
    ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) |
           (ui32IntFlags & CRYPTO_RESULT_RDY));

    // Using level interrupt.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;

    // Enable the specified interrupts.
    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= ui32IntFlags;
}

static void CRYPTOIntRegister ( void(*)(void)  pfnHandler )

inlinestatic

Registers an interrupt handler for a Crypto interrupt.

This function does the actual registering of the interrupt handler. This function enables the global interrupt in the interrupt controller; specific UART interrupts must be enabled via CRYPTOIntEnable(). It is the interrupt handler's responsibility to clear the interrupt source.

Parameters

pfnHandler

is a pointer to the function to be called when the UART interrupt occurs.

Returns

None

See also

IntRegister() for important information about registering interrupt handlers.

{
    // Register the interrupt handler.
    IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, pfnHandler);

    // Enable the UART interrupt.
    IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
}

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static uint32_t CRYPTOIntStatus ( bool  bMasked )

inlinestatic

Gets the current interrupt status.

This function returns the interrupt status for the specified Crypto. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Parameters

bMasked

whether to use raw or masked interrupt status: false : Raw interrupt status is required. true : Masked interrupt status is required.

Returns

Returns the current interrupt status:

• CRYPTO_DMA_IN_DONE
• CRYPTO_RESULT_RDY

{
    uint32_t ui32Mask;

    // Return either the interrupt status or the raw interrupt status as
    // requested.
    if(bMasked)
    {
        ui32Mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN);
        return(ui32Mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT));
    }
    else
    {
        return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & 0x00000003);
    }
}

static void CRYPTOIntUnregister ( void  )

inlinestatic

Unregisters an interrupt handler for a Crypto interrupt.

This function does the actual unregistering of the interrupt handler. It clears the handler to be called when a Crypto interrupt occurs. This function also masks off the interrupt in the interrupt controller so that the interrupt handler no longer is called.

Returns

None

See also

IntRegister() for important information about registering interrupt handlers.

{
    // Disable the interrupt.
    IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);

    // Unregister the interrupt handler.
    IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ);
}

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Macro Definition Documentation

#define AES_CCM_TEST_ERROR   10

#define AES_DMA_BSY   11

Referenced by CRYPTOAesEcbStatus(), CRYPTOCcmAuthEncryptStatus(), and CRYPTOCcmInvAuthDecryptStatus().

#define AES_DMA_BUS_ERROR   3

Referenced by CRYPTOAesEcbStatus(), CRYPTOCcmAuthEncrypt(), CRYPTOCcmAuthEncryptStatus(), CRYPTOCcmInvAuthDecrypt(), and CRYPTOCcmInvAuthDecryptStatus().

#define AES_ECB_LENGTH   16

Referenced by CRYPTOAesEcb().

#define AES_ECB_TEST_ERROR   8

#define AES_KEYSTORE_READ_ERROR   1

Referenced by CRYPTOAesCbc(), CRYPTOAesEcb(), CRYPTOAesLoadKey(), CRYPTOCcmAuthEncrypt(), and CRYPTOCcmInvAuthDecrypt().

#define AES_KEYSTORE_WRITE_ERROR   2

#define AES_NULL_ERROR   9

#define AES_SUCCESS   0

Referenced by CRYPTOAesCbc(), CRYPTOAesEcb(), CRYPTOAesEcbStatus(), CRYPTOAesLoadKey(), CRYPTOCcmAuthEncrypt(), CRYPTOCcmAuthEncryptResultGet(), CRYPTOCcmAuthEncryptStatus(), CRYPTOCcmInvAuthDecrypt(), CRYPTOCcmInvAuthDecryptResultGet(), and CRYPTOCcmInvAuthDecryptStatus().

#define CCM_AUTHENTICATION_FAILED   4

Referenced by CRYPTOCcmInvAuthDecryptResultGet().

#define CRYPTO_AES128_DECRYPT   0x00000008

Referenced by CRYPTOAesCbc(), and CRYPTOAesEcb().

#define CRYPTO_AES128_ENCRYPT   0x0000000C

Referenced by CRYPTOAesCbc(), and CRYPTOAesEcb().

#define CRYPTO_AES_CBC   5

#define CRYPTO_AES_CCM   3

#define CRYPTO_AES_CTR_128   0x3

Referenced by CRYPTOCcmAuthEncrypt(), and CRYPTOCcmInvAuthDecrypt().

#define CRYPTO_AES_CTR_32   0x0

#define CRYPTO_AES_CTR_64   0x1

#define CRYPTO_AES_CTR_96   0x2

#define CRYPTO_AES_ECB   2

#define CRYPTO_AES_KEYL0AD   1

#define CRYPTO_AES_NONE   0

#define CRYPTO_AES_RNG   4

#define CRYPTO_DMA_BSY   0x00000003

Referenced by CRYPTOAesEcbStatus(), CRYPTOCcmAuthEncryptStatus(), and CRYPTOCcmInvAuthDecryptStatus().

#define CRYPTO_DMA_BUS_ERR   0x80000000

Referenced by CRYPTOCcmAuthEncrypt(), and CRYPTOCcmInvAuthDecrypt().

#define CRYPTO_DMA_BUS_ERROR   0x00020000

Referenced by CRYPTOAesEcbStatus(), CRYPTOCcmAuthEncryptStatus(), and CRYPTOCcmInvAuthDecryptStatus().

#define CRYPTO_DMA_CHAN0   0x00000001

Referenced by CRYPTODmaDisable(), and CRYPTODmaEnable().

#define CRYPTO_DMA_CHAN1   0x00000002

Referenced by CRYPTODmaDisable(), and CRYPTODmaEnable().

#define CRYPTO_DMA_IN_DONE   0x00000002

Referenced by CRYPTOIntClear(), CRYPTOIntDisable(), and CRYPTOIntEnable().

#define CRYPTO_DMA_READY   0x00000000

#define CRYPTO_IRQTYPE_LEVEL   0x00000001

Referenced by CRYPTOAesCbc(), CRYPTOAesEcb(), CRYPTOAesLoadKey(), CRYPTOCcmAuthEncrypt(), CRYPTOCcmInvAuthDecrypt(), and CRYPTOIntEnable().

#define CRYPTO_IRQTYPE_PULSE   0x00000000

#define CRYPTO_KEY_AREA_0   0

Referenced by CRYPTOAesLoadKey().

#define CRYPTO_KEY_AREA_1   1

Referenced by CRYPTOAesLoadKey().

#define CRYPTO_KEY_AREA_2   2

Referenced by CRYPTOAesLoadKey().

#define CRYPTO_KEY_AREA_3   3

Referenced by CRYPTOAesLoadKey().

#define CRYPTO_KEY_AREA_4   4

Referenced by CRYPTOAesLoadKey().

#define CRYPTO_KEY_AREA_5   5

Referenced by CRYPTOAesLoadKey().

#define CRYPTO_KEY_AREA_6   6

Referenced by CRYPTOAesLoadKey().

#define CRYPTO_KEY_AREA_7   7

Referenced by CRYPTOAesLoadKey().

#define CRYPTO_KEY_ST_RD_ERR   0x20000000

Referenced by CRYPTOAesCbc(), CRYPTOAesEcb(), CRYPTOCcmAuthEncrypt(), and CRYPTOCcmInvAuthDecrypt().

#define CRYPTO_KEY_ST_WR_ERR   0x40000000

#define CRYPTO_RESULT_RDY   0x00000001

Referenced by CRYPTOIntClear(), CRYPTOIntDisable(), and CRYPTOIntEnable().

#define KEY_BLENGTH   16

Referenced by CRYPTOAesLoadKey().

#define KEY_EXP_LENGTH   176

#define KEY_STORE_SIZE_128   0x00000001

Referenced by CRYPTOAesLoadKey(), CRYPTOCcmAuthEncrypt(), and CRYPTOCcmInvAuthDecrypt().

#define KEY_STORE_SIZE_192   0x00000002

#define KEY_STORE_SIZE_256   0x00000003

#define KEY_STORE_SIZE_BITS   0x00000003

#define STATE_BLENGTH   16