CC13xx Driver Library
Functions
[setup] Setup
System Control

Functions

void SetupTrimDevice (void)
 Performs the necessary trim of the device which is not done in boot code. More...
 
void SetupAfterColdResetWakeupFromShutDownCfg1 (uint32_t ccfg_ModeConfReg)
 First part of configuration required when waking up from shutdown. More...
 
void SetupAfterColdResetWakeupFromShutDownCfg2 (uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)
 Second part of configuration required when waking up from shutdown. More...
 
void SetupAfterColdResetWakeupFromShutDownCfg3 (uint32_t ccfg_ModeConfReg)
 Third part of configuration required when waking up from shutdown. More...
 
uint32_t SetupGetTrimForAdcShModeEn (uint32_t ui32Fcfg1Revision)
 Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting. More...
 
uint32_t SetupGetTrimForAdcShVbufEn (uint32_t ui32Fcfg1Revision)
 Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting. More...
 
uint32_t SetupGetTrimForAmpcompCtrl (uint32_t ui32Fcfg1Revision)
 Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG. More...
 
uint32_t SetupGetTrimForAmpcompTh1 (void)
 Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG. More...
 
uint32_t SetupGetTrimForAmpcompTh2 (void)
 Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG. More...
 
uint32_t SetupGetTrimForAnabypassValue1 (uint32_t ccfg_ModeConfReg)
 Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG. More...
 
uint32_t SetupGetTrimForDblrLoopFilterResetVoltage (uint32_t ui32Fcfg1Revision)
 Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting. More...
 
uint32_t SetupGetTrimForRadcExtCfg (uint32_t ui32Fcfg1Revision)
 Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG. More...
 
uint32_t SetupGetTrimForRcOscLfIBiasTrim (uint32_t ui32Fcfg1Revision)
 Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM. More...
 
uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim (void)
 Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG. More...
 
uint32_t SetupGetTrimForXoscHfCtl (uint32_t ui32Fcfg1Revision)
 Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG. More...
 
uint32_t SetupGetTrimForXoscHfFastStart (void)
 Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START. More...
 
uint32_t SetupGetTrimForXoscHfIbiastherm (void)
 Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in the ANABYPASS_VALUE2 register in OSC_DIG. More...
 
uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio (uint32_t ui32Fcfg1Revision)
 Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet spanning bits [5:0] in the returned value. More...
 
static int32_t SetupSignExtendVddrTrimValue (uint32_t ui32VddrTrimVal)
 Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) More...
 
void SetupSetCacheModeAccordingToCcfgSetting (void)
 Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM) More...
 
void SetupSetAonRtcSubSecInc (uint32_t subSecInc)
 Doing the tricky stuff needed to enter new RTCSUBSECINC value. More...
 
void SetupSetVddrLevel (uint32_t ccfg_ModeConfReg)
 Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and setting VDDS_BOD to max). More...
 

Detailed Description

Function Documentation

void SetupAfterColdResetWakeupFromShutDownCfg1 ( uint32_t  ccfg_ModeConfReg)

First part of configuration required when waking up from shutdown.

Parameters
ccfg_ModeConfReg
Returns
None

Referenced by TrimAfterColdResetWakeupFromShutDown().

188 {
189  int32_t i32VddrSleepTrim;
190  int32_t i32VddrSleepDelta;
191 
192  // Check for CC13xx boost mode
193  // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode
194  if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) &&
195  (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) {
196  // Set VDDS_BOD trim - using masked write {MASK8:DATA8}
197  // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1
198  // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to
199  // latch new VDDS BOD. Set to 0 first to guarantee a positive transition.
200  HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
201 // if ( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) {
202  //
203  // VDDS_BOD_LEVEL = 1 means that boost mode is selected
204  // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31)
205  HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) =
206  ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) |
207  ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ;
208 // } else {
209 // //
210 // // VDDS_BOD_LEVEL = 0
211 // // - Set VDDS_BOD to FCFG1..TRIMBOD_H
212 // //
213 // HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) =
214 // ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) |
215 // ((( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) &
216 // FCFG1_VOLT_TRIM_TRIMBOD_H_M ) >>
217 // FCFG1_VOLT_TRIM_TRIMBOD_H_S ) << ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S );
218 // }
219  HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
220 
221  SetupSetVddrLevel( ccfg_ModeConfReg );
222 
223  i32VddrSleepTrim = SetupSignExtendVddrTrimValue((
224  HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) &
225  FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M ) >>
226  FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S ) ;
227  } else
228  {
229  i32VddrSleepTrim = SetupSignExtendVddrTrimValue((
230  HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) &
231  FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M ) >>
232  FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S ) ;
233  }
234 
235  // Adjust the VDDR_TRIM_SLEEP value with value adjustable by customer (CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA)
236  // Read and sign extend VddrSleepDelta (in range -8 to +7)
237  i32VddrSleepDelta =
238  (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S )))
239  >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W ));
240  // Calculate new VDDR sleep trim
241  i32VddrSleepTrim = ( i32VddrSleepTrim + i32VddrSleepDelta + 1 );
242  if ( i32VddrSleepTrim > 21 ) i32VddrSleepTrim = 21;
243  if ( i32VddrSleepTrim < -10 ) i32VddrSleepTrim = -10;
244  // Write adjusted value using MASKED write (MASK8)
245  HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL1 * 2 )) = (( ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M << 8 ) |
246  (( i32VddrSleepTrim << ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S ) & ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M ));
247 
248  // 1.
249  // Do not allow DCDC to be enabled if in external regulator mode.
250  // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg).
251  //
252  // 2.
253  // Adjusted battery monitor low limit in internal regulator mode.
254  // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode.
255  if ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) {
256  ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M );
257  } else {
258  HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0;
259  }
260 
261  // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE
262  // Note: Inverse polarity
263  HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL, AON_SYSCTL_PWRCTL_DCDC_EN_BITN ) =
264  ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 );
265 
266  // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE
267  // Note: Inverse polarity
268  HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL, AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN ) =
269  ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 );
270 }
SetupSetVddrLevel
void SetupSetVddrLevel(uint32_t ccfg_ModeConfReg)
Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and setting VDDS_BOD to max)...
Definition: setup_rom.c:124
SetupSignExtendVddrTrimValue
static int32_t SetupSignExtendVddrTrimValue(uint32_t ui32VddrTrimVal)
Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21)
Definition: setup_rom.h:294

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void SetupAfterColdResetWakeupFromShutDownCfg2 ( uint32_t  ui32Fcfg1Revision,
uint32_t  ccfg_ModeConfReg 
)

Second part of configuration required when waking up from shutdown.

Parameters
ui32Fcfg1Revision
ccfg_ModeConfReg
Returns
None

Referenced by TrimAfterColdResetWakeupFromShutDown().

279 {
280  uint32_t ui32Trim;
281 
282  // Following sequence is required for using XOSCHF, if not included
283  // devices crashes when trying to switch to XOSCHF.
284  //
285  // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1
286  // register
287  ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg );
288  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim);
289 
290  // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and
291  // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register.
292  ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim();
293  DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL,
294  (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M |
295  DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M),
296  DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S,
297  ui32Trim);
298 
299  // Trim XOSCHF IBIAS THERM. Get and set trim value for the
300  // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other
301  // register bit fields are set to 0.
302  ui32Trim = SetupGetTrimForXoscHfIbiastherm();
303  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2,
304  ui32Trim<<DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S);
305 
306  // Trim AMPCOMP settings required before switch to XOSCHF
307  ui32Trim = SetupGetTrimForAmpcompTh2();
308  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH2, ui32Trim);
309  ui32Trim = SetupGetTrimForAmpcompTh1();
310  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH1, ui32Trim);
311 #if ( CCFG_BASE == CCFG_BASE_DEFAULT )
312  ui32Trim = SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision );
313 #else
314  ui32Trim = NOROM_SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision );
315 #endif
316  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPCTL, ui32Trim);
317 
318  // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN in accordance to FCFG1 setting
319  // This is bit[5] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
320  // Using MASK4 write + 1 => writing to bits[7:4]
321  ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision );
322  HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
323  ( 0x20 | ( ui32Trim << 1 ));
324 
325  // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting
326  // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
327  // Using MASK4 write + 1 => writing to bits[7:4]
328  ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision );
329  HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
330  ( 0x10 | ( ui32Trim ));
331 
332  // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields
333  // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting.
334  // Remaining register bit fields are set to their reset values of 0.
335  ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision);
336  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim);
337 
338  // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting
339  // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL)
340  // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4))
341  // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and
342  // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000)
343  ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision );
344  HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) =
345  ( 0x60 | ( ui32Trim << 1 ));
346 
347  // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from
348  // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM
349  // This is DDI_0_OSC_O_ATESTCTL bit[7]
350  // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020))
351  // Using MASK4 write + 1 => writing to bits[7:4]
352  ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision );
353  HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) =
354  ( 0x80 | ( ui32Trim << 3 ));
355 
356  // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and
357  // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write
358  // This can be simplified since the registers are packed together in the same
359  // order both in FCFG1 and in the HW register.
360  // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18]
361  // Using MASK8 write + 4 => writing to bits[23:16]
362  ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision );
363  HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) =
364  ( 0xFC00 | ( ui32Trim << 2 ));
365 
366  // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit
367  // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting.
368  // Remaining register bit fields are set to their reset values of 0.
369  ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision);
370  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim);
371 
372  // Setting FORCE_KICKSTART_EN (ref. CC26_V1_BUG00261). Should also be done for PG2
373  // (This is bit 22 in DDI_0_OSC_O_CTL0)
374  HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_FORCE_KICKSTART_EN;
375 }
SetupGetTrimForAmpcompTh1
uint32_t SetupGetTrimForAmpcompTh1(void)
Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG.
Definition: setup_rom.c:654
SetupGetTrimForRcOscLfRtuneCtuneTrim
uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim(void)
Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the RCOSCLF_CTUNE_TRIM bit fields in...
Definition: setup_rom.c:572
SetupGetTrimForAmpcompTh2
uint32_t SetupGetTrimForAmpcompTh2(void)
Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG.
Definition: setup_rom.c:619
SetupGetTrimForDblrLoopFilterResetVoltage
uint32_t SetupGetTrimForDblrLoopFilterResetVoltage(uint32_t ui32Fcfg1Revision)
Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting.
Definition: setup_rom.c:771
SetupGetTrimForAdcShVbufEn
uint32_t SetupGetTrimForAdcShVbufEn(uint32_t ui32Fcfg1Revision)
Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting.
Definition: setup_rom.c:809
DDI16BitfieldWrite
void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)
Write a bit field via the DDI using 16-bit maskable write.
Definition: ddi.c:117
SetupGetTrimForRadcExtCfg
uint32_t SetupGetTrimForRadcExtCfg(uint32_t ui32Fcfg1Revision)
Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG.
Definition: setup_rom.c:878
SetupGetTrimForRcOscLfIBiasTrim
uint32_t SetupGetTrimForRcOscLfIBiasTrim(uint32_t ui32Fcfg1Revision)
Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM.
Definition: setup_rom.c:910
SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio(uint32_t ui32Fcfg1Revision)
Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet spanning bits [5:0] in the retur...
Definition: setup_rom.c:929
SetupGetTrimForAnabypassValue1
uint32_t SetupGetTrimForAnabypassValue1(uint32_t ccfg_ModeConfReg)
Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG.
Definition: setup_rom.c:503
SetupGetTrimForAdcShModeEn
uint32_t SetupGetTrimForAdcShModeEn(uint32_t ui32Fcfg1Revision)
Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting.
Definition: setup_rom.c:790
SetupGetTrimForAmpcompCtrl
uint32_t SetupGetTrimForAmpcompCtrl(uint32_t ui32Fcfg1Revision)
Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG.
Definition: setup_rom.c:689
DDI32RegWrite
void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
Write a 32 bit value to a register in the DDI slave.
Definition: ddi.c:66
SetupGetTrimForXoscHfCtl
uint32_t SetupGetTrimForXoscHfCtl(uint32_t ui32Fcfg1Revision)
Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG.
Definition: setup_rom.c:828
SetupGetTrimForXoscHfIbiastherm
uint32_t SetupGetTrimForXoscHfIbiastherm(void)
Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in the ANABYPASS_VALUE2 regist...
Definition: setup_rom.c:599

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void SetupAfterColdResetWakeupFromShutDownCfg3 ( uint32_t  ccfg_ModeConfReg)

Third part of configuration required when waking up from shutdown.

Parameters
ccfg_ModeConfReg
Returns
None

Referenced by TrimAfterColdResetWakeupFromShutDown().

384 {
385  uint32_t fcfg1OscConf;
386  uint32_t ui32Trim;
387  uint32_t currentHfClock;
388  uint32_t ccfgExtLfClk;
389 
390  // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC
391  switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) {
392  case 2 :
393  // XOSC source is a 48 MHz crystal
394  // Do nothing (since this is the reset setting)
395  break;
396  case 1 :
397  // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC)
398 
399  fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF );
400 
401  if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) {
402  // This is a HPOSC chip, apply HPOSC settings
403  // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0)
404  HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN;
405 
406  // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit)
407  // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits)
408  // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits)
409  // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit)
410  // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits)
411  // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits)
412  // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit)
413 
414  HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) &
415  ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) |
416  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) |
417  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) );
418  HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) |
419  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) );
420  HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) &
421  ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) |
422  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) |
423  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) |
424  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) |
425  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) );
426  break;
427  }
428  // Not a HPOSC chip - fall through to default
429  default :
430  // XOSC source is a 24 MHz crystal (default)
431  // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0)
432  HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M;
433  break;
434  }
435 
436  // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO
437  // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used.
438  if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) {
439  HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS;
440  }
441 
442  // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0.
443  // This is typically already 0 except on Lizard where it is set in ROM-boot
444  HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN;
445 
446  // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1
447  ui32Trim = SetupGetTrimForXoscHfFastStart();
448  HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim );
449 
450  // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION
451  switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) {
452  case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz)
453  OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF );
454  SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency
455  break;
456  case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT)
457  // Set SCLK_LF to use the same source as SCLK_HF
458  // Can be simplified a bit since possible return values for HF matches LF settings
459  currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF );
460  OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock );
461  while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) {
462  // Wait until switched
463  }
464  ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK );
465  SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S );
466  IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S,
467  IOC_PORT_AON_CLK32K,
468  IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis
469  // Set XOSC_LF in bypass mode to allow external 32 kHz clock
470  HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS;
471  // Fall through to set XOSC_LF as SCLK_LF source
472  case 2 : // XOSC_LF -> SLCK_LF (32768 Hz)
473  OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF );
474  break;
475  default : // (=3) RCOSC_LF
476  OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF );
477  break;
478  }
479 
480  // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1
481  HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) =
482  ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >>
483  FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) <<
484  ADI_4_AUX_ADCREF1_VTRIM_S ) &
485  ADI_4_AUX_ADCREF1_VTRIM_M );
486 
487  // Set ADI_4_AUX:ADC0.SMPL_CYCLE_EXP to it's default minimum value (=3)
488  // (Note: Using MASK8B requires that the bits to be modified must be within the same
489  // byte boundary which is the case for the ADI_4_AUX_ADC0_SMPL_CYCLE_EXP field)
490  HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_ADC0 * 2 )) =
491  ( ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M << 8 ) | ( 3 << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S );
492 
493  // Sync with AON
494  SysCtrlAonSync();
495 }
SysCtrlAonSync
static void SysCtrlAonSync(void)
Sync all accesses to the AON register interface.
Definition: sys_ctrl.h:177
IOC_PORT_AON_CLK32K
#define IOC_PORT_AON_CLK32K
Definition: ioc.h:169
OSCClockSourceGet
uint32_t OSCClockSourceGet(uint32_t ui32SrcClk)
Get the source clock settings.
Definition: osc.c:147
IOC_STD_INPUT
#define IOC_STD_INPUT
Definition: ioc.h:297
SetupSetAonRtcSubSecInc
void SetupSetAonRtcSubSecInc(uint32_t subSecInc)
Doing the tricky stuff needed to enter new RTCSUBSECINC value.
Definition: setup_rom.c:994
OSC_SRC_CLK_HF
#define OSC_SRC_CLK_HF
Definition: osc.h:112
OSC_XOSC_HF
#define OSC_XOSC_HF
Definition: osc.h:117
OSC_SRC_CLK_LF
#define OSC_SRC_CLK_LF
Definition: osc.h:114
OSC_RCOSC_LF
#define OSC_RCOSC_LF
Definition: osc.h:118
IOCPortConfigureSet
void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)
Set the configuration of an IO port.
Definition: ioc.c:96
IOC_HYST_ENABLE
#define IOC_HYST_ENABLE
Definition: ioc.h:220
SetupGetTrimForXoscHfFastStart
uint32_t SetupGetTrimForXoscHfFastStart(void)
Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START.
Definition: setup_rom.c:860
OSCClockSourceSet
void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc)
Configure the oscillator input to the a source clock.
Definition: osc.c:100
OSC_XOSC_LF
#define OSC_XOSC_LF
Definition: osc.h:119

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uint32_t SetupGetTrimForAdcShModeEn ( uint32_t  ui32Fcfg1Revision)

Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting.

Parameters
ui32Fcfg1Revision
Returns
Returns the trim value from FCFG1.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

791 {
792  uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting
793 
794  if ( ui32Fcfg1Revision >= 0x00000022 ) {
795  getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
796  FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >>
797  FCFG1_OSC_CONF_ADC_SH_MODE_EN_S;
798  }
799 
800  return ( getTrimForAdcShModeEnValue );
801 }
uint32_t SetupGetTrimForAdcShVbufEn ( uint32_t  ui32Fcfg1Revision)

Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting.

Parameters
ui32Fcfg1Revision
Returns
Returns the trim value from FCFG1.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

810 {
811  uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting
812 
813  if ( ui32Fcfg1Revision >= 0x00000022 ) {
814  getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
815  FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >>
816  FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S;
817  }
818 
819  return ( getTrimForAdcShVbufEnValue );
820 }
uint32_t SetupGetTrimForAmpcompCtrl ( uint32_t  ui32Fcfg1Revision)

Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG.

Parameters
ui32Fcfg1Revision
Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

690 {
691  uint32_t ui32TrimValue ;
692  uint32_t ui32Fcfg1Value ;
693  uint32_t ibiasOffset ;
694  uint32_t ibiasInit ;
695  uint32_t modeConf1 ;
696  int32_t deltaAdjust ;
697 
698  // Use device specific trim values located in factory configuration
699  // area. Register bit fields without trim values in the factory
700  // configuration area will be set to the value of 0.
701  ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 );
702 
703  ibiasOffset = ( ui32Fcfg1Value &
704  FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >>
705  FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ;
706  ibiasInit = ( ui32Fcfg1Value &
707  FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >>
708  FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ;
709 
710  if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) {
711  // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG
712  modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 );
713 
714  // Both fields are signed 4-bit values. This is an assumption when doing the sign extension.
715  deltaAdjust =
716  (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S )))
717  >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W ));
718  deltaAdjust += (int32_t)ibiasOffset;
719  if ( deltaAdjust < 0 ) {
720  deltaAdjust = 0;
721  }
722  if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) {
723  deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S );
724  }
725  ibiasOffset = (uint32_t)deltaAdjust;
726 
727  deltaAdjust =
728  (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S )))
729  >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W ));
730  deltaAdjust += (int32_t)ibiasInit;
731  if ( deltaAdjust < 0 ) {
732  deltaAdjust = 0;
733  }
734  if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) {
735  deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S );
736  }
737  ibiasInit = (uint32_t)deltaAdjust;
738  }
739  ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) |
740  ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ;
741 
742  ui32TrimValue |= (((ui32Fcfg1Value &
743  FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>>
744  FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<<
745  DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S);
746  ui32TrimValue |= (((ui32Fcfg1Value &
747  FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>>
748  FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<<
749  DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S);
750  ui32TrimValue |= (((ui32Fcfg1Value &
751  FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>>
752  FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<<
753  DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S);
754 
755  if ( ui32Fcfg1Revision >= 0x00000022 ) {
756  ui32TrimValue |= ((( ui32Fcfg1Value &
757  FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >>
758  FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) <<
759  DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S );
760  }
761 
762  return(ui32TrimValue);
763 }
uint32_t SetupGetTrimForAmpcompTh1 ( void  )

Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG.

Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

655 {
656  uint32_t ui32TrimValue;
657  uint32_t ui32Fcfg1Value;
658 
659  // Use device specific trim values located in factory configuration
660  // area. All defined register bit fields have a corresponding trim
661  // value in the factory configuration area
662  ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1);
663  ui32TrimValue = (((ui32Fcfg1Value &
664  FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>>
665  FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<<
666  DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S);
667  ui32TrimValue |= (((ui32Fcfg1Value &
668  FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>>
669  FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<<
670  DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S);
671  ui32TrimValue |= (((ui32Fcfg1Value &
672  FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>>
673  FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<<
674  DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S);
675  ui32TrimValue |= (((ui32Fcfg1Value &
676  FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>>
677  FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<<
678  DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S);
679 
680  return(ui32TrimValue);
681 }
uint32_t SetupGetTrimForAmpcompTh2 ( void  )

Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG.

Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

620 {
621  uint32_t ui32TrimValue;
622  uint32_t ui32Fcfg1Value;
623 
624  // Use device specific trim value located in factory configuration
625  // area. All defined register bit fields have corresponding trim
626  // value in the factory configuration area
627  ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2);
628  ui32TrimValue = ((ui32Fcfg1Value &
629  FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>>
630  FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<<
631  DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S;
632  ui32TrimValue |= (((ui32Fcfg1Value &
633  FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>>
634  FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<<
635  DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S);
636  ui32TrimValue |= (((ui32Fcfg1Value &
637  FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>>
638  FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<<
639  DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S);
640  ui32TrimValue |= (((ui32Fcfg1Value &
641  FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>>
642  FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<<
643  DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S);
644 
645  return(ui32TrimValue);
646 }
uint32_t SetupGetTrimForAnabypassValue1 ( uint32_t  ccfg_ModeConfReg)

Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG.

Parameters
ccfg_ModeConfReg
Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

504 {
505  uint32_t ui32Fcfg1Value ;
506  uint32_t ui32XoscHfRow ;
507  uint32_t ui32XoscHfCol ;
508  uint32_t ui32TrimValue ;
509 
510  // Use device specific trim values located in factory configuration
511  // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in
512  // the ANABYPASS_VALUE1 register. Value for the other bit fields
513  // are set to 0.
514 
515  ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP);
516  ui32XoscHfRow = (( ui32Fcfg1Value &
517  FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >>
518  FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S );
519  ui32XoscHfCol = (( ui32Fcfg1Value &
520  FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >>
521  FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S );
522 
523  if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) {
524  // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation
525  // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg
526  // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by
527  // a define and sign extension must therefore be hard coded.
528  // ( A small test program is created verifying the code lines below:
529  // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c)
530  int32_t i32CustomerDeltaAdjust =
531  (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S )))
532  >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W ));
533 
534  while ( i32CustomerDeltaAdjust < 0 ) {
535  ui32XoscHfCol >>= 1; // COL 1 step down
536  if ( ui32XoscHfCol == 0 ) { // if COL below minimum
537  ui32XoscHfCol = 0xFFFF; // Set COL to maximum
538  ui32XoscHfRow >>= 1; // ROW 1 step down
539  if ( ui32XoscHfRow == 0 ) { // if ROW below minimum
540  ui32XoscHfRow = 1; // Set both ROW and COL
541  ui32XoscHfCol = 1; // to minimum
542  }
543  }
544  i32CustomerDeltaAdjust++;
545  }
546  while ( i32CustomerDeltaAdjust > 0 ) {
547  ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up
548  if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum
549  ui32XoscHfCol = 1; // Set COL to minimum
550  ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up
551  if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum
552  ui32XoscHfRow = 0xF; // Set both ROW and COL
553  ui32XoscHfCol = 0xFFFF; // to maximum
554  }
555  }
556  i32CustomerDeltaAdjust--;
557  }
558  }
559 
560  ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) |
561  ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) );
562 
563  return (ui32TrimValue);
564 }
uint32_t SetupGetTrimForDblrLoopFilterResetVoltage ( uint32_t  ui32Fcfg1Revision)

Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting.

Parameters
ui32Fcfg1Revision
Returns
Returns the trim value from FCFG1.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

772 {
773  uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value
774 
775  if ( ui32Fcfg1Revision >= 0x00000020 ) {
776  dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) &
777  FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >>
778  FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S;
779  }
780 
781  return ( dblrLoopFilterResetVoltageValue );
782 }
uint32_t SetupGetTrimForRadcExtCfg ( uint32_t  ui32Fcfg1Revision)

Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG.

Parameters
ui32Fcfg1Revision
Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

879 {
880  uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting
881  uint32_t fcfg1Data;
882 
883  if ( ui32Fcfg1Revision >= 0x00000020 ) {
884  fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
885  getTrimForRadcExtCfgValue =
886  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >>
887  FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) <<
888  DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S);
889 
890  getTrimForRadcExtCfgValue |=
891  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >>
892  FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) <<
893  DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S);
894 
895  getTrimForRadcExtCfgValue |=
896  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >>
897  FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) <<
898  DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S);
899  }
900 
901  return ( getTrimForRadcExtCfgValue );
902 }
uint32_t SetupGetTrimForRcOscLfIBiasTrim ( uint32_t  ui32Fcfg1Revision)

Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM.

Parameters
ui32Fcfg1Revision
Returns
Returns the trim value from FCFG1.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

911 {
912  uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value
913 
914  if ( ui32Fcfg1Revision >= 0x00000022 ) {
915  trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
916  FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >>
917  FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ;
918  }
919 
920  return ( trimForRcOscLfIBiasTrimValue );
921 }
uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim ( void  )

Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG.

Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

573 {
574  uint32_t ui32TrimValue;
575 
576  // Use device specific trim values located in factory configuration
577  // area
578  ui32TrimValue =
579  ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
580  FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>>
581  FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<<
582  DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S;
583 
584  ui32TrimValue |=
585  ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
586  FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>>
587  FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<<
588  DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S;
589 
590  return(ui32TrimValue);
591 }
uint32_t SetupGetTrimForXoscHfCtl ( uint32_t  ui32Fcfg1Revision)

Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG.

Parameters
ui32Fcfg1Revision
Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

829 {
830  uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting
831  uint32_t fcfg1Data;
832 
833  if ( ui32Fcfg1Revision >= 0x00000020 ) {
834  fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
835  getTrimForXoschfCtlValue =
836  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >>
837  FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) <<
838  DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S);
839 
840  getTrimForXoschfCtlValue |=
841  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >>
842  FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) <<
843  DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S);
844 
845  getTrimForXoschfCtlValue |=
846  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >>
847  FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) <<
848  DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S);
849  }
850 
851  return ( getTrimForXoschfCtlValue );
852 }
uint32_t SetupGetTrimForXoscHfFastStart ( void  )

Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START.

Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg3().

861 {
862  uint32_t ui32XoscHfFastStartValue ;
863 
864  // Get value from FCFG1
865  ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
866  FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >>
867  FCFG1_OSC_CONF_XOSC_HF_FAST_START_S;
868 
869  return ( ui32XoscHfFastStartValue );
870 }
uint32_t SetupGetTrimForXoscHfIbiastherm ( void  )

Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in the ANABYPASS_VALUE2 register in OSC_DIG.

Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

600 {
601  uint32_t ui32TrimValue;
602 
603  // Use device specific trim value located in factory configuration
604  // area
605  ui32TrimValue =
606  (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) &
607  FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>>
608  FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S;
609 
610  return(ui32TrimValue);
611 }
uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ( uint32_t  ui32Fcfg1Revision)

Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet spanning bits [5:0] in the returned value.

Parameters
ui32Fcfg1Revision
Returns
Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

930 {
931  uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields
932 
933  if ( ui32Fcfg1Revision >= 0x00000022 ) {
934  trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
935  ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M |
936  FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >>
937  FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ;
938  }
939 
940  return ( trimForXoscLfRegulatorAndCmirrwrRatioValue );
941 }
void SetupSetAonRtcSubSecInc ( uint32_t  subSecInc)

Doing the tricky stuff needed to enter new RTCSUBSECINC value.

Parameters
subSecInc
Returns
None

Referenced by SetupAfterColdResetWakeupFromShutDownCfg3().

995 {
996  // Loading a new RTCSUBSECINC value is done in 5 steps:
997  // 1. Write bit[15:0] of new SUBSECINC value to AUX_WUC_O_RTCSUBSECINC0
998  // 2. Write bit[23:16] of new SUBSECINC value to AUX_WUC_O_RTCSUBSECINC1
999  // 3. Set AUX_WUC_RTCSUBSECINCCTL_UPD_REQ
1000  // 4. Wait for AUX_WUC_RTCSUBSECINCCTL_UPD_ACK
1001  // 5. Clear AUX_WUC_RTCSUBSECINCCTL_UPD_REQ
1002  HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_WUC_RTCSUBSECINC0_INC15_0_M );
1003  HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_WUC_RTCSUBSECINC1_INC23_16_M );
1004 
1005  HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL ) = AUX_WUC_RTCSUBSECINCCTL_UPD_REQ;
1006  while( ! ( HWREGBITW( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL, AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN )));
1007  HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL ) = 0;
1008 }
void SetupSetCacheModeAccordingToCcfgSetting ( void  )

Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM)

Returns
None

Referenced by SetupTrimDevice().

950 {
951  // - Make sure to enable aggressive VIMS clock gating for power optimization
952  // Only for PG2 devices.
953  // - Enable cache prefetch enable as default setting
954  // (Slightly higher power consumption, but higher CPU performance)
955  // - IF ( CCFG_..._DIS_GPRAM == 1 )
956  // then: Enable cache (set cache mode = 1), even if set by ROM boot code
957  // (This is done because it's not set by boot code when running inside
958  // a debugger supporting the Halt In Boot (HIB) functionality).
959  // else: Set MODE_GPRAM if not already set (see inline comments as well)
960  uint32_t vimsCtlMode0 ;
961 
962  while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) {
963  // Do nothing - wait for an eventual ongoing mode change to complete.
964  // (There should typically be no wait time here, but need to be sure)
965  }
966 
967  // Note that Mode=0 is equal to MODE_GPRAM
968  vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M );
969 
970 
971  if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) {
972  // Enable cache (and hence disable GPRAM)
973  HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE );
974  } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) {
975  // GPRAM is enabled in CCFG but not selected
976  // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM
977  HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF );
978  while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) {
979  // Do nothing - wait for an eventual mode change to complete (This goes fast).
980  }
981  HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0;
982  } else {
983  // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set
984  HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0;
985  }
986 }
void SetupSetVddrLevel ( uint32_t  ccfg_ModeConfReg)

Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and setting VDDS_BOD to max).

Parameters
ccfg_ModeConfReg
Returns
None

Referenced by SetupAfterColdResetWakeupFromShutDownCfg1().

125 {
126  uint32_t newTrimRaw ;
127  int32_t targetTrim ;
128  int32_t currentTrim ;
129  int32_t deltaTrim ;
130 
131 // if ( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) {
132  //
133  // VDDS_BOD_LEVEL = 1 means that boost mode is selected
134  // - Step up VDDR_TRIM to FCFG1..VDDR_TRIM_HH
135  newTrimRaw = (( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) &
136  FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >>
137  FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ;
138 // } else {
139 // //
140 // // VDDS_BOD_LEVEL = 0
141 // // - Step up VDDR_TRIM to FCFG1..VDDR_TRIM_H
142 // //
143 // newTrimRaw = (( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) &
144 // FCFG1_VOLT_TRIM_VDDR_TRIM_H_M ) >>
145 // FCFG1_VOLT_TRIM_VDDR_TRIM_H_S ) ;
146 // }
147  targetTrim = SetupSignExtendVddrTrimValue( newTrimRaw );
148  currentTrim = SetupSignExtendVddrTrimValue((
149  HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) &
150  ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >>
151  ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ;
152 
153  if ( currentTrim != targetTrim ) {
154  // Disable VDDR BOD
155  HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN ) = 0;
156 
157  while ( currentTrim != targetTrim ) {
158  deltaTrim = targetTrim - currentTrim;
159  if ( deltaTrim > 2 ) deltaTrim = 2;
160  if ( deltaTrim < -2 ) deltaTrim = -2;
161  currentTrim += deltaTrim;
162 
163  HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait one SCLK_LF period
164 
165  HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL0 * 2 )) =
166  ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M << 8 ) | (( currentTrim <<
167  ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) &
168  ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) ;
169 
170  HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ) = 1; // Force SCLK_LF period wait on next read
171  }
172 
173  HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait one SCLK_LF period
174  HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ) = 1; // Force SCLK_LF period wait on next read
175  HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait one more SCLK_LF period before re-enabling VDDR BOD
176  HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN ) = 1;
177  HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate
178  }
179 }
SetupSignExtendVddrTrimValue
static int32_t SetupSignExtendVddrTrimValue(uint32_t ui32VddrTrimVal)
Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21)
Definition: setup_rom.h:294

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static int32_t SetupSignExtendVddrTrimValue ( uint32_t  ui32VddrTrimVal)
inlinestatic

Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21)

Parameters
ui32VddrTrimVal
Returns
Returns Sign extended VDDR_TRIM setting.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg1(), SetupSetVddrLevel(), and SysCtrlSetRechargeBeforePowerDown().

295 {
296  // The VDDR trim value is 5 bits representing the range from -10 to +21
297  // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15)
298  int32_t i32SignedVddrVal = ui32VddrTrimVal;
299  if ( i32SignedVddrVal > 0x15 ) {
300  i32SignedVddrVal -= 0x20;
301  }
302  return ( i32SignedVddrVal );
303 }
void SetupTrimDevice ( void  )

Performs the necessary trim of the device which is not done in boot code.

This function should only execute coming from ROM boot. The current implementation does not take soft reset into account. However, it does no damage to execute it again. It only consumes time.

Returns
None
113 {
114  uint32_t ui32Fcfg1Revision;
115  uint32_t ui32AonSysResetctl;
116 
117  // Get layout revision of the factory configuration area
118  // (Handle undefined revision as revision = 0)
119  ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION);
120  if ( ui32Fcfg1Revision == 0xFFFFFFFF ) {
121  ui32Fcfg1Revision = 0;
122  }
123 
124  // This driverlib version and setup file is for CC13x0 PG2.0 and later.
125  // Halt if violated
126  ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated();
127 
128  // Enable standby in flash bank
129  HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
130 
131  // Clock must always be enabled for the semaphore module (due to ADI/DDI HW workaround)
132  HWREG( AUX_WUC_BASE + AUX_WUC_O_MODCLKEN1 ) = AUX_WUC_MODCLKEN1_SMPH;
133 
134  // Warm resets on CC13x0 and CC26x0 complicates software design because much of
135  // our software expect that initialization is done from a full system reset.
136  // This includes RTC setup, oscillator configuration and AUX setup.
137  // To ensure a full reset of the device is done when customers get e.g. a Watchdog
138  // reset, the following is set here:
139  HWREGBITW( PRCM_BASE + PRCM_O_WARMRESET, PRCM_WARMRESET_WR_TO_PINRESET_BITN ) = 1;
140 
141  // Select correct CACHE mode and set correct CACHE configuration
142 #if ( CCFG_BASE == CCFG_BASE_DEFAULT )
143  SetupSetCacheModeAccordingToCcfgSetting();
144 #else
145  NOROM_SetupSetCacheModeAccordingToCcfgSetting();
146 #endif
147 
148  // 1. Check for powerdown
149  // 2. Check for shutdown
150  // 3. Assume cold reset if none of the above.
151  //
152  // It is always assumed that the application will freeze the latches in
153  // AON_IOC when going to powerdown in order to retain the values on the IOs.
154  //
155  // NB. If this bit is not cleared before proceeding to powerdown, the IOs
156  // will all default to the reset configuration when restarting.
157  if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN )))
158  {
159  // NB. This should be calling a ROM implementation of required trim and
160  // compensation
161  // e.g. TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()
162  TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
163  }
164  // Check for shutdown
165  //
166  // When device is going to shutdown the hardware will automatically clear
167  // the SLEEPDIS bit in the SLEEP register in the AON_SYSCTL module.
168  // It is left for the application to assert this bit when waking back up,
169  // but not before the desired IO configuration has been re-established.
170  else if( ! ( HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL, AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN )))
171  {
172  // NB. This should be calling a ROM implementation of required trim and
173  // compensation
174  // e.g. TrimAfterColdResetWakeupFromShutDown() -->
175  // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
176  TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision);
177  TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
178  }
179  else
180  {
181  // Consider adding a check for soft reset to allow debugging to skip
182  // this section!!!
183  //
184  // NB. This should be calling a ROM implementation of required trim and
185  // compensation
186  // e.g. TrimAfterColdReset() -->
187  // TrimAfterColdResetWakeupFromShutDown() -->
188  // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()
189  TrimAfterColdReset();
190  TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision);
191  TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
192 
193  }
194 
195  // Set VIMS power domain control.
196  // PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered
197  HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0;
198 
199  // Configure optimal wait time for flash FSM in cases where flash pump
200  // wakes up from sleep
201  HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) &
202  ~FLASH_FPAC1_PSLEEPTDIS_M) |
203  (0x139<<FLASH_FPAC1_PSLEEPTDIS_S);
204 
205  // And finally at the end of the flash boot process:
206  // SET BOOT_DET bits in AON_SYSCTL to 3 if already found to be 1
207  // Note: The BOOT_DET_x_CLR/SET bits must be manually cleared
208  if ((( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) &
209  ( AON_SYSCTL_RESETCTL_BOOT_DET_1_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_M )) >>
210  AON_SYSCTL_RESETCTL_BOOT_DET_0_S ) == 1 )
211  {
212  ui32AonSysResetctl = ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) &
213  ~( AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M |
214  AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M ));
215  HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M;
216  HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl;
217  }
218 
219  // Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice()
220  // (There should typically be no wait time here, but need to be sure)
221  while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) {
222  // Do nothing - wait for an eventual ongoing mode change to complete.
223  }
224 }
TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown
static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(void)
Trims to be applied when coming from POWER_DOWN (also called when coming from SHUTDOWN and PIN_RESET)...
Definition: setup.c:235
ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated
void ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated(void)
Verifies that current chip is CC13x0 HwRev 2.0 or later and never returns if violated.
Definition: chipinfo.c:176
SetupSetCacheModeAccordingToCcfgSetting
void SetupSetCacheModeAccordingToCcfgSetting(void)
Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM)
Definition: setup_rom.c:949
TrimAfterColdResetWakeupFromShutDown
static void TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision)
Trims to be applied when coming from SHUTDOWN (also called when coming from PIN_RESET).
Definition: setup.c:251
TrimAfterColdReset
static void TrimAfterColdReset(void)
Trims to be applied when coming from PIN_RESET.
Definition: setup.c:356

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