SPI Chip Select

Description

SPI master chip select (CSN)

This resource implements Serial Peripheral Interface (SPI) chip select pins (CSN) for the SPI Data Transfer resource. Multiple chip select pins can be used to access multiple SPI slaves, with shared clock and data lines for all slaves. The pins are mapped in the I/O Mapping Panel .

The CSN signal is active low.

The CSN pins can be configured individually as driven high (default) or pulled high while deasserted.

It is assumed that the SPI signals are not shared with another SPI master. The SCLK and MOSI lines are driven while CSN is deasserted to prevent these lines from floating. The MISO line can be configured as no pull, pull-up or pull-down. Note that the MISO input buffer is disabled while CSN is deasserted, and will not cause leakage if the pin is left floating in this state (with no pull).

For information on the SPI_POLx_PHAy constants, see the SPI Data Transfer resource documentation.

Examples

Write Multiple SPI Device Configuration Registers

// MACRO: Writes an 8-bit value to an accelerometer register with 8-bit address
macro spiWriteAccelReg(addr, value) {
    spiBegin(SPI_POL0_PHA0, AUXIO_SPI_CSN_ACCEL);
    spiTx8bit(SPI_POL0_PHA0, ACCEL_SPI_WRITE);
    spiTx8bit(SPI_POL0_PHA0, addr);
    spiTx8bit(SPI_POL0_PHA0, value);
    spiEnd(SPI_POL0_PHA0, AUXIO_SPI_CSN_ACCEL);
}

// Perform soft reset of the accelerometer, and wait for 50 ms
spiWriteAccelReg(ACCEL_REG_SOFT_RESET, ACCEL_SR_KEY);
fwDelayUs(50000, FW_DELAY_RANGE_50_MS);

// Perform one-time configuration of the accelerometer
spiWriteAccelReg(ACCEL_REG_INTMAP1, ACCEL_IM_DATA_READY);
spiWriteAccelReg(ACCEL_REG_POWER_CTL, ACCEL_PC_LOW_NOISE_0 | ACCEL_PC_MEASURE_ON);

Read Array of SPI Device Registers

// Read accelerometer data:
// - Write 8-bit register address
// - Read 16-bit value for each axis, most significant byte first (no need to swap endianess)
spiBegin(SPI_POL0_PHA0, AUXIO_SPI_CSN_ACCEL);
spiTx8bit(SPI_POL0_PHA0, 0x42);
spiRx16bit(SPI_POL0_PHA0; output.x);
spiRx16bit(SPI_POL0_PHA0; output.y);
spiRx16bit(SPI_POL0_PHA0; output.z);
spiEnd(SPI_POL0_PHA0, AUXIO_SPI_CSN_ACCEL);

Read Array of SPI Device Registers with Endianess Conversion

// MACRO: Reads a 16-bit value over SPI, and swaps endianess (LSB is received before MSB)
macro spiRx16bitSwapEndianess(value) {
    U16 valueLsbFirst;
    spiRx16bit(SPI_POL0_PHA0; valueLsbFirst);
    utilSwapEndianess(valueLsbFirst; value);
}

// Read accelerometer data:
// - Write 8-bit register address
// - Read 16-bit value for each axis, least significant byte first (need to swap endianess)
spiBegin(SPI_POL0_PHA0, AUXIO_SPI_CSN_ACCEL);
spiTx8bit(SPI_POL0_PHA0, 0x42);
spiRx16bitSwapEndianess(output.x);
spiRx16bitSwapEndianess(output.y);
spiRx16bitSwapEndianess(output.z);
spiEnd(SPI_POL0_PHA0, AUXIO_SPI_CSN_ACCEL);

Procedures Overview

Name Brief description
spiBegin() Asserts the selected SPI chip select pin (active low). More …
spiEnd() Deasserts the selected SPI chip select pin (active low). More …

Constants

None.

Global Variables

None.

Procedures

spiBegin

Prototype: spiBegin(#cfg, #auxio)

Asserts the selected SPI chip select pin (active low). This procedure shall be called at the start of an SPI transfer.

Parameter value(s)

  • #cfg : SCLK polarity and phase configuration (SPI_POLx_PHAy)
  • #auxio : SPI CSN pin selection (index of AUX I/O pin)

spiEnd

Prototype: spiEnd(#cfg, #auxio)

Deasserts the selected SPI chip select pin (active low). This procedure shall be called at the end of an SPI transfer.

Parameter value(s)

  • #cfg : SCLK polarity and phase configuration (SPI_POLx_PHAy)
  • #auxio : SPI CSN pin selection (index of AUX I/O pin)