OsalRegisterIntParams_corepac_t Struct Reference

Detailed Description

Interrupt Configuration parameters for the corepac (c6x/a15/m5/a8/a9)

Data Fields
char *	name
int32_t	corepacEventNum
int32_t	intVecNum
Osal_IsrRoutine	isrRoutine
uintptr_t	arg
uint32_t	priority
uint32_t	triggerSensitivity
uint32_t	enableIntr

Field Documentation

name

char* OsalRegisterIntParams_corepac_t::name

Name of the instance for debugging purposes, could be set to NULL

corepacEventNum

int32_t OsalRegisterIntParams_corepac_t::corepacEventNum

Event number going in to the DSP corepac

intVecNum

int32_t OsalRegisterIntParams_corepac_t::intVecNum

Interrupt vector number for ARM corepac

isrRoutine

Osal_IsrRoutine OsalRegisterIntParams_corepac_t::isrRoutine

The ISR routine to hook the corepacEventNum to

arg

uintptr_t OsalRegisterIntParams_corepac_t::arg

Argument to the ISR routine

priority

uint32_t OsalRegisterIntParams_corepac_t::priority

Device specific priority for ARM corepac where a lower priority value indicates a higher priority, the priority range is corepac specific as listed below:

• A8: 0-127
• A9/A15/A53: 0-255
• ARP32: 1(NMI), 2-13(INT4-15)
• R5: 0-15
• M4: None Note: For R5 Core, baremetal case, there is no device specific priority set - all interrupts are handled at the same priority So, this is not applicable for bare metal R5 Core interrupt config.

triggerSensitivity

uint32_t OsalRegisterIntParams_corepac_t::triggerSensitivity

Set an interrupt's trigger sensitivity for ARM corepac as OSAL_armGicTrigType_t. The applicable trigger types are corepac specific and listed below:

• A53: Level and Edge Trigger
• A15: Low/High Level and Rising/Falling Edge Trigger
• A8/A9: Low/High Level and Rising/Falling/Both Edge Trigger
• R5: Level Trigger and Pulse Trigger

enableIntr

uint32_t OsalRegisterIntParams_corepac_t::enableIntr

When set to TRUE, interrupt is enabled after registration (Osal_RegisterInterrupt) otherwise interrupt is disabled