PDK API Guide for J721E
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CacheP interface
Files | |
file | CacheP.h |
Cache Handling routines for the RTOS Porting Interface. | |
Functions | |
void | CacheP_wb (const void *addr, int32_t size) |
Function to write back cache lines. More... | |
void | CacheP_Inv (const void *addr, int32_t size) |
Function to invalidate cache lines. More... | |
void | CacheP_wbInv (const void *addr, int32_t size) |
Function to write back and invalidate cache lines. More... | |
void | CacheP_fenceCpu2Dma (uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent) |
Function to call before handing over the memory buffer to DMA from CPU. More... | |
void | CacheP_fenceDma2Cpu (uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent) |
Function to call before reading the memory to CPU after DMA operations. More... | |
void | CacheP_setMar (void *baseAddr, uint32_t size, uint32_t value) |
Set MAR attribute for a memory range. More... | |
uint32_t | CacheP_getMar (void *baseAddr) |
Get MAR attribute for a region of 16MB. More... | |
Enumerations | |
enum | CacheP_Mar { CacheP_Mar_DISABLE = ((uint32_t) 0), CacheP_Mar_ENABLE = ((uint32_t) 1) } |
MAR register setting type definition. More... | |
Cache coherent type definitions | |
typedef uint32_t | Osal_CacheP_isCoherent |
This enumerator defines the cache coherent types. More... | |
#define | OSAL_CACHEP_COHERENT ((uint32_t) 0U) |
#define | OSAL_CACHEP_NOT_COHERENT ((uint32_t) 1U) |
#define OSAL_CACHEP_COHERENT ((uint32_t) 0U) |
Cache is coherent on this CPU
#define OSAL_CACHEP_NOT_COHERENT ((uint32_t) 1U) |
Cache is not coherent on this CPU
typedef uint32_t Osal_CacheP_isCoherent |
This enumerator defines the cache coherent types.
enum CacheP_Mar |
void CacheP_wb | ( | const void * | addr, |
int32_t | size | ||
) |
Function to write back cache lines.
addr | Start address of the cache line/s |
size | size (in bytes) of the memory to be written back |
void CacheP_Inv | ( | const void * | addr, |
int32_t | size | ||
) |
Function to invalidate cache lines.
addr | Start address of the cache line/s |
size | size (in bytes) of the memory to invalidate |
void CacheP_wbInv | ( | const void * | addr, |
int32_t | size | ||
) |
Function to write back and invalidate cache lines.
addr | Start address of the cache line/s |
size | size (in bytes) of the memory to be written back and invalidate |
void CacheP_fenceCpu2Dma | ( | uintptr_t | addr, |
uint32_t | size, | ||
Osal_CacheP_isCoherent | isCoherent | ||
) |
Function to call before handing over the memory buffer to DMA from CPU.
addr | Start address of the cache line/s |
size | size (in bytes) of the memory to be written back and invalidate |
isCoherent | if the cache is coherent on that CPU or not, see Osal_CacheP_isCoherent |
void CacheP_fenceDma2Cpu | ( | uintptr_t | addr, |
uint32_t | size, | ||
Osal_CacheP_isCoherent | isCoherent | ||
) |
Function to call before reading the memory to CPU after DMA operations.
addr | Start address of the cache line/s |
size | size (in bytes) of the memory to be written back and invalidate |
isCoherent | if the cache is coherent on that CPU or not, see Osal_CacheP_isCoherent |
void CacheP_setMar | ( | void * | baseAddr, |
uint32_t | size, | ||
uint32_t | value | ||
) |
Set MAR attribute for a memory range.
[C66x Only] The API will set the MAR attribute for the range, start_addr = floor(baseAddr, 16MB) .. end_addr = ceil(baseAddr+size, 16MB)
baseAddr | Region start address. Recommended to be 16MB aligned |
size | Region size in bytes. Recommended to be multiple of 16MB aligned |
value | value for setting MAR register CacheP_Mar |
uint32_t CacheP_getMar | ( | void * | baseAddr | ) |
Get MAR attribute for a region of 16MB.
[C66x Only] The API will return the MAR attribute of the region with start addr as start_addr = floor(baseAddr, 16MB)
baseAddr | region start address, recommended to be 16MB aligned |