Introduction

Maximum number of MPU regions available in R5F SS.

#define	SDL_ARM_R5F_MPU_REGIONS_MAX ((uint32_t) 16U)
	Number of R5 MPU region. More...

Arm R5F MPU sub-region disable control.
Mask for R5 MPU sub-region disable.
#define	SDL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL ((uint32_t) 0x0U)
	Enable all sub-regions. More...

#define	SDL_ARM_R5_MPU_SUB_REGION_0_DISABLE ((uint32_t) 0x1U)
	Disable sub-region 0. More...

#define	SDL_ARM_R5_MPU_SUB_REGION_1_DISABLE ((uint32_t) 0x2U)
	Disable sub-region 1. More...

#define	SDL_ARM_R5_MPU_SUB_REGION_2_DISABLE ((uint32_t) 0x4U)
	Disable sub-region 2. More...

#define	SDL_ARM_R5_MPU_SUB_REGION_3_DISABLE ((uint32_t) 0x8U)
	Disable sub-region 3. More...

#define	SDL_ARM_R5_MPU_SUB_REGION_4_DISABLE ((uint32_t) 0x10U)
	Disable sub-region 4. More...

#define	SDL_ARM_R5_MPU_SUB_REGION_5_DISABLE ((uint32_t) 0x20U)
	Disable sub-region 5. More...

#define	SDL_ARM_R5_MPU_SUB_REGION_6_DISABLE ((uint32_t) 0x40U)
	Disable sub-region 6. More...

#define	SDL_ARM_R5_MPU_SUB_REGION_8_DISABLE ((uint32_t) 0x80U)
	Disable sub-region 7. More...

Arm R5F MPU region access permissions.
Access permissions for R5 MPU regions.
#define	SDL_ARM_R5_ACC_PERM_NO_ACCESS ((uint32_t) 0x0U)
	No accesses are permitted to MPU region. More...

#define	SDL_ARM_R5_ACC_PERM_PRIV_RD_WR ((uint32_t) 0x1U)
	Privileged accesses only. More...

#define	SDL_ARM_R5_ACC_PERM_PRIV_RD_WR_USR_RD ((uint32_t) 0x2U)
	Privileged read/write accesses and user read only. More...

#define	SDL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR ((uint32_t) 0x3U)
	Full access to privileged and user modes. More...

#define	SDL_ARM_R5_ACC_PERM_PRIV_RD_ONLY ((uint32_t) 0x5U)
	Privileged read accesses only. More...

#define	SDL_ARM_R5_ACC_PERM_PRIV_USR_RD ((uint32_t) 0x6U)
	Read only accesses to privileged and user modes. More...

Arm R5F MPU region cache policy.
Inner and outer cache policy for R5 MPU region.
#define	SDL_ARM_R5_CACHE_POLICY_NON_CACHEABLE ((uint32_t) 0x0U)
	Cache Policy: Non-cacheable. More...

#define	SDL_ARM_R5_CACHE_POLICY_WB_WA ((uint32_t) 0x1U)
	Cache Policy: Write-back, write-allocate. More...

#define	SDL_ARM_R5_CACHE_POLICY_WT_NO_WA ((uint32_t) 0x2U)
	Cache Policy: Write-through, no write-allocate. More...

#define	SDL_ARM_R5_CACHE_POLICY_WB_NO_WA ((uint32_t) 0x3U)
	Cache Policy: Write-back, no write-allocate. More...

Arm R5F MPU region attributes.
Memory attributes: TEX[2:0], C, and B encodings.
#define	SDL_ARM_R5_MEM_ATTR_STRONGLY_ORDERED ((uint32_t) 0x0U)
	Memory type and cache policies: Strongly-ordered. More...

#define	SDL_ARM_R5_MEM_ATTR_SHAREABLE ((uint32_t) 0x1U)
	Memory type and cache policies: Shareable. More...

#define	SDL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA ((uint32_t) 0x2U)
	Memory type and cache policies: Outer and Inner write-through, no write-allocate. More...

#define	SDL_ARM_R5_MEM_ATTR_CACHED_WB_NO_WA ((uint32_t) 0x3U)
	Memory type and cache policies: Outer and Inner write-back, no write-allocate. More...

#define	SDL_ARM_R5_MEM_ATTR_STRONGLY_NON_CACHED ((uint32_t) 0x4U)
	Memory type and cache policies: Non cacheable. More...

#define	SDL_ARM_R5_MEM_ATTR_CACHED_WB_WA ((uint32_t) 0x5U)
	Memory type and cache policies: Outer and Inner write-back, write-allocate. More...

#define	SDL_ARM_R5_MEM_ATTR_NON_SHAREABLE ((uint32_t) 0x6U)
	Memory type and cache policies: Non-shareable Device. More...

#define	SDL_ARM_R5_MEM_ATTR_MAX ((uint32_t) 0x7U)
	This should be passed to configuration. More...

Macro Definition Documentation

◆ SDL_ARM_R5F_MPU_REGIONS_MAX

#define SDL_ARM_R5F_MPU_REGIONS_MAX ((uint32_t) 16U)

Number of R5 MPU region.

◆ SDL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL

#define SDL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL ((uint32_t) 0x0U)

Enable all sub-regions.

◆ SDL_ARM_R5_MPU_SUB_REGION_0_DISABLE

#define SDL_ARM_R5_MPU_SUB_REGION_0_DISABLE ((uint32_t) 0x1U)

Disable sub-region 0.

◆ SDL_ARM_R5_MPU_SUB_REGION_1_DISABLE

#define SDL_ARM_R5_MPU_SUB_REGION_1_DISABLE ((uint32_t) 0x2U)

Disable sub-region 1.

◆ SDL_ARM_R5_MPU_SUB_REGION_2_DISABLE

#define SDL_ARM_R5_MPU_SUB_REGION_2_DISABLE ((uint32_t) 0x4U)

Disable sub-region 2.

◆ SDL_ARM_R5_MPU_SUB_REGION_3_DISABLE

#define SDL_ARM_R5_MPU_SUB_REGION_3_DISABLE ((uint32_t) 0x8U)

Disable sub-region 3.

◆ SDL_ARM_R5_MPU_SUB_REGION_4_DISABLE

#define SDL_ARM_R5_MPU_SUB_REGION_4_DISABLE ((uint32_t) 0x10U)

Disable sub-region 4.

◆ SDL_ARM_R5_MPU_SUB_REGION_5_DISABLE

#define SDL_ARM_R5_MPU_SUB_REGION_5_DISABLE ((uint32_t) 0x20U)

Disable sub-region 5.

◆ SDL_ARM_R5_MPU_SUB_REGION_6_DISABLE

#define SDL_ARM_R5_MPU_SUB_REGION_6_DISABLE ((uint32_t) 0x40U)

Disable sub-region 6.

◆ SDL_ARM_R5_MPU_SUB_REGION_8_DISABLE

#define SDL_ARM_R5_MPU_SUB_REGION_8_DISABLE ((uint32_t) 0x80U)

Disable sub-region 7.

◆ SDL_ARM_R5_ACC_PERM_NO_ACCESS

#define SDL_ARM_R5_ACC_PERM_NO_ACCESS ((uint32_t) 0x0U)

No accesses are permitted to MPU region.

◆ SDL_ARM_R5_ACC_PERM_PRIV_RD_WR

#define SDL_ARM_R5_ACC_PERM_PRIV_RD_WR ((uint32_t) 0x1U)

Privileged accesses only.

◆ SDL_ARM_R5_ACC_PERM_PRIV_RD_WR_USR_RD

#define SDL_ARM_R5_ACC_PERM_PRIV_RD_WR_USR_RD ((uint32_t) 0x2U)

Privileged read/write accesses and user read only.

◆ SDL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR

#define SDL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR ((uint32_t) 0x3U)

Full access to privileged and user modes.

◆ SDL_ARM_R5_ACC_PERM_PRIV_RD_ONLY

#define SDL_ARM_R5_ACC_PERM_PRIV_RD_ONLY ((uint32_t) 0x5U)

Privileged read accesses only.

◆ SDL_ARM_R5_ACC_PERM_PRIV_USR_RD

#define SDL_ARM_R5_ACC_PERM_PRIV_USR_RD ((uint32_t) 0x6U)

Read only accesses to privileged and user modes.

◆ SDL_ARM_R5_CACHE_POLICY_NON_CACHEABLE

#define SDL_ARM_R5_CACHE_POLICY_NON_CACHEABLE ((uint32_t) 0x0U)

Cache Policy: Non-cacheable.

◆ SDL_ARM_R5_CACHE_POLICY_WB_WA

#define SDL_ARM_R5_CACHE_POLICY_WB_WA ((uint32_t) 0x1U)

Cache Policy: Write-back, write-allocate.

◆ SDL_ARM_R5_CACHE_POLICY_WT_NO_WA

#define SDL_ARM_R5_CACHE_POLICY_WT_NO_WA ((uint32_t) 0x2U)

Cache Policy: Write-through, no write-allocate.

◆ SDL_ARM_R5_CACHE_POLICY_WB_NO_WA

#define SDL_ARM_R5_CACHE_POLICY_WB_NO_WA ((uint32_t) 0x3U)

Cache Policy: Write-back, no write-allocate.

◆ SDL_ARM_R5_MEM_ATTR_STRONGLY_ORDERED

#define SDL_ARM_R5_MEM_ATTR_STRONGLY_ORDERED ((uint32_t) 0x0U)

Memory type and cache policies: Strongly-ordered.

◆ SDL_ARM_R5_MEM_ATTR_SHAREABLE

#define SDL_ARM_R5_MEM_ATTR_SHAREABLE ((uint32_t) 0x1U)

Memory type and cache policies: Shareable.

◆ SDL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA

#define SDL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA ((uint32_t) 0x2U)

Memory type and cache policies: Outer and Inner write-through, no write-allocate.

◆ SDL_ARM_R5_MEM_ATTR_CACHED_WB_NO_WA

#define SDL_ARM_R5_MEM_ATTR_CACHED_WB_NO_WA ((uint32_t) 0x3U)

Memory type and cache policies: Outer and Inner write-back, no write-allocate.

◆ SDL_ARM_R5_MEM_ATTR_STRONGLY_NON_CACHED

#define SDL_ARM_R5_MEM_ATTR_STRONGLY_NON_CACHED ((uint32_t) 0x4U)

Memory type and cache policies: Non cacheable.

◆ SDL_ARM_R5_MEM_ATTR_CACHED_WB_WA

#define SDL_ARM_R5_MEM_ATTR_CACHED_WB_WA ((uint32_t) 0x5U)

Memory type and cache policies: Outer and Inner write-back, write-allocate.

◆ SDL_ARM_R5_MEM_ATTR_NON_SHAREABLE

#define SDL_ARM_R5_MEM_ATTR_NON_SHAREABLE ((uint32_t) 0x6U)

Memory type and cache policies: Non-shareable Device.

◆ SDL_ARM_R5_MEM_ATTR_MAX

#define SDL_ARM_R5_MEM_ATTR_MAX ((uint32_t) 0x7U)

This should be passed to configuration.