94 #include "Eth_Types.h" 95 #include "Eth_LL_Types.h" 96 #include "Udma_Types.h" 97 #include "EthIf_Cbk.h" 107 #define ETH_VERSION_INFO_API (STD_ON) 110 #define ETH_GLOBALTIMESUPPORT_API (STD_ON) 113 #define ETH_DEV_ERROR_DETECT (STD_ON) 116 #define ETH_GET_COUNTER_VALUES_API (STD_ON) 119 #define ETH_GET_RX_STATS_API (STD_ON) 122 #define ETH_GET_TX_STATS_API (STD_ON) 125 #define ETH_GET_TX_ERROR_COUNTERSVALUES_API (STD_ON) 129 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP (STD_OFF) 132 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4 (STD_OFF) 135 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP (STD_OFF) 138 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP (STD_OFF) 142 #define ETH_ENABLE_MII_API (STD_ON) 145 #define ETH_UPDATE_PHYS_ADDR_FILTER_API (STD_ON) 148 #define ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API (STD_OFF) 151 #define ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API (STD_OFF) 154 #define ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API (STD_OFF) 157 #define ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API (STD_OFF) 160 #define ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API (STD_OFF) 163 #define ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API (STD_OFF) 166 #define ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF) 169 #define ETH_VIRTUALMAC_ADD_UNICAST_MACADDR_API (STD_OFF) 172 #define ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API (STD_OFF) 175 #define ETH_VIRTUALMAC_DEL_MACADDR_API (STD_OFF) 178 #define ETH_VIRTUALMAC_SEND_CUSTOM_NOTIFY_API (STD_OFF) 181 #define ETH_VIRTUALMAC_ADD_VLAN_API (STD_OFF) 184 #define ETH_VIRTUALMAC_DEL_VLAN_API (STD_OFF) 188 #define ETH_ISR_TYPE (ETH_ISR_CAT2) 190 #define ETH_OS_COUNTER_ID ((CounterType)OsCounter_0) 192 #define ETH_OS_COUNTER_FREQ (1000000000U) 195 #define ETH_VIRTUALMAC_SUPPORT (STD_OFF) 197 #define ETH_VIRTUALMAC_FWINFO_TIMEOUT (0U) 203 #define EthConf_EthCtrlConfig_EthCtrlIdx_0 (0U) 210 #define ETH_PRE_COMPILE_VARIANT (STD_ON) 211 #define ETH_LINK_TIME_VARIANT (STD_OFF) 212 #define ETH_POST_BUILD_VARIANT (STD_OFF) 218 #define ETH_CTRL_ID_MAX (1u) 224 #define ETH_DMA_IR_SUPPORT (STD_ON) 225 #define ETH_DMA_CQ_RING_SUPPORT (STD_ON) 226 #define ETH_DMA_TEARDOWN_SUPPORT (STD_ON) 233 #define UDMA_DEVICE_ID_RING (235U) 234 #define UDMA_DEVICE_ID_UDMA (236U) 235 #define UDMA_DEVICE_ID_PSIL (232U) 236 #define UDMA_DEVICE_ID_IA (233U) 237 #define UDMA_DEVICE_ID_IR (237U) 238 #define UDMA_DEVICE_ID_CORE (250U) 245 #define UDMA_TX_CHANNEL_PEER_OFFSET (0xf000U) 246 #define UDMA_RX_CHANNEL_PEER_OFFSET (0x7000U) 247 #define UDMA_SOURCE_THREAD_OFFSET (0x6000U) 248 #define UDMA_DEST_THREAD_OFFSET (0xe000U) 255 #define ETH_DMA_TX_BASE_REG (0x2aa00000U) 256 #define ETH_DMA_RX_BASE_REG (0x2a800000U) 257 #define ETH_DMA_RINGRT_BASE (0x2b800000U) 258 #define ETH_DMA_RINGCFG_BASE (0x28440000U) 259 #define ETH_DMA_INTAGGR_INTR_BASE (0x2a700000U) 266 #define ETH_DMA_TXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U)) 267 #define ETH_DMA_TXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U)) 268 #define ETH_DMA_RXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U)) 269 #define ETH_DMA_RXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U)) 271 #define ETH_DMA_RINGRT_RING_FDB(RING) (0x00000010U + ((RING) * 0x1000U)) 272 #define ETH_DMA_RINGRT_RING_FOCC(RING) (0x00000018U + ((RING) * 0x1000U)) 273 #define ETH_DMA_RINGRT_RING_RDB(RING) (0x00000010U + ((RING) * 0x1000U)) 274 #define ETH_DMA_RINGRT_RING_ROCC(RING) (0x00000018U + ((RING) * 0x1000U)) 275 #define ETH_DMA_RINGCFG_RING_SIZE(RING) (0x00000048U + ((RING) * 0x100U)) 277 #define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000008U + ((VINT) * 0x1000U)) 278 #define ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000010U + ((VINT) * 0x1000U)) 279 #define ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000018U + ((VINT) * 0x1000U)) 280 #define ETH_DMA_INTAGGR_INTR_VINT_STATUSM(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000020U + ((VINT) * 0x1000U)) 282 #define Eth_GetRingFDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FDB((RingNum))) 283 #define Eth_GetRingFOCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FOCC((RingNum))) 284 #define Eth_GetRingRDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_RDB((RingNum))) 285 #define Eth_GetRingROCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_ROCC((RingNum))) 286 #define Eth_GetRingSizeReg(RingNum) (ETH_DMA_RINGCFG_BASE + ETH_DMA_RINGCFG_RING_SIZE((RingNum))) 288 #define Eth_GetTxChannelCtlRegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_CTL((ChanId))) 289 #define Eth_GetTxChannelPeer8RegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_PEER8((ChanId))) 290 #define Eth_GetRxChannelCtlRegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_CTL((ChanId))) 291 #define Eth_GetRxChannelPeer8RegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_PEER8((ChanId))) 297 #define UDMA_WAIT_TEARDOWN_COUNTER (10000u) 304 #define Eth_GetDem_E_HARDWARE_ERROR(CtrlIndex) ( ETH_DEM_NO_EVENT ) 305 #define Eth_GetDem_E_LATECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) 306 #define Eth_GetDem_E_MULTIPLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) 307 #define Eth_GetDem_E_SINGLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) 308 #define Eth_GetDem_E_ALIGNMENT(CtrlIndex) ( ETH_DEM_NO_EVENT ) 309 #define Eth_GetDem_E_OVERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT ) 310 #define Eth_GetDem_E_UNDERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT ) 311 #define Eth_GetDem_E_CRC(CtrlIndex) ( ETH_DEM_NO_EVENT ) 312 #define Eth_GetDem_E_RX_FRAMES_LOST(CtrlIndex) ( ETH_DEM_NO_EVENT ) 313 #define Eth_GetDem_E_ACCESS(CtrlIndex) ( ETH_DEM_NO_EVENT ) 314 #define Eth_GetDem_E_TX_INTERNAL(CtrlIndex) ( ETH_DEM_NO_EVENT ) 321 #define Eth_IsVirtualMacModeEnable(CtrlIndex) ( FALSE ) 322 #define Eth_GetTxChannelThreadOffset(CtrlIndex) ( 0xf000U ) 323 #define Eth_VirtMacGetEthFwRpcComChannelId(CtrlIndex) ( 0U ) 324 #define Eth_VirtMacGetEthPollRecvMsgInEthMain(CtrlIndex) ( FALSE ) 325 #define Eth_VirtMacGetRpcCmdCompleteFuncPtr(CtrlIndex) ( (Eth_RpcCmdComplete)NULL_PTR ) 326 #define Eth_VirtMacGetFwRegisterFuncPtr(CtrlIndex) ( (Eth_RpcFwRegistered)NULL_PTR ) 328 #define Eth_GetTxEnableInterrupt(CtrlIndex) ( TRUE ) 329 #define Eth_GetRxEnableInterrupt(CtrlIndex) ( TRUE ) 330 #define Eth_GetEnetType(CtrlIndex) ( ETH_ENETTYPE_CPSW2G ) 331 #define Eth_GetMacPortNum(CtrlIndex) ( ETH_PORT_MAC_PORT_1 ) 332 #define Eth_GetMacAddressHigh(CtrlIndex) ( 0xaabbccddU ) 333 #define Eth_GetMacAddressLow(CtrlIndex) ( 0xeeffU ) 334 #define Eth_UseDefaultMacAddress(CtrlIndex) ( TRUE ) 335 #define Eth_GetMiiConnectionType(CtrlIndex) ( ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL ) 336 #define Eth_GetLoopBackMode(CtrlIndex) ( FALSE ) 337 #define Eth_GetHardwareLoopTimeout(CtrlIndex) ( 32000U ) 338 #define Eth_GetEnableCacheOps(CtrlIndex) ( TRUE ) 339 #define Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ( &EthApp_wbInvCache ) 340 #define Eth_GetCacheWritebackFuncPtr(CtrlIndex) ( &EthApp_wbCache ) 341 #define Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ( &EthApp_invCache ) 342 #define Eth_DescriptorGetCacheWritebackInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ) 343 #define Eth_DescriptorGetCacheWritebackFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackFuncPtr(CtrlIndex) ) 344 #define Eth_DescriptorGetCacheInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ) 345 #define Eth_RingGetCacheWritebackInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ) 346 #define Eth_RingGetCacheWritebackFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackFuncPtr(CtrlIndex) ) 347 #define Eth_RingGetCacheInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ) 349 #define Eth_Cpsw_GetPhyMacRegAddr() ( 0x40f00200U ) 350 #define Eth_Cpsw_GetAleRegAddr() ( 0x4603e000U ) 351 #define Eth_Cpsw_GetCptsRegAddr() ( 0x4603d000U ) 352 #define Eth_Cpsw_GetMdioRegAddr() ( 0x46000f00U ) 353 #define Eth_Cpsw_GetCtrlRegAddr() ( 0x46020000U ) 354 #define Eth_Cpsw_GetCptsRefClockFreq() ( 1U ) 355 #define Eth_Cpsw_GetCppiClockFreq() ( 333333333U ) 357 #define Eth_Cpsw_GetMdioBusClockFreq(CtrlIndex) ( 2200000U ) 358 #define Eth_Cpsw_GetMdioOpMode(CtrlIndex) ( ETH_MDIO_OPMODE_MANUAL ) 360 #define Eth_GetRxMtuLength(CtrlIndex) ( 1522U ) 361 #define Eth_GetTxChanStartNum(CtrlIndex) ( 30U ) 362 #define Eth_GetRxChanStartNum(CtrlIndex) ( 30U ) 363 #define Eth_GetEgressFifoTotalNum(CtrlIndex) ( 1U ) 364 #define Eth_GetIngressFifoTotalNum(CtrlIndex) ( 1U ) 365 #define Eth_GetRingTotalNum(CtrlIndex) ( 6U ) 366 #define Eth_GetTxChanTotalNum(CtrlIndex) ( 1U ) 367 #define Eth_GetRxChanTotalNum(CtrlIndex) ( 1U ) 368 #define Eth_GetFlowTotalNumber(CtrlIndex) ( 1U ) 369 #define Eth_GetEventTotalNum(CtrlIndex) ( 2U ) 370 #define Eth_GetRingEventTotalNum(CtrlIndex) ( 2U ) 372 #define Eth_GetEgressFifoPacketNum(CtrlIndex, FifoIdx) ( 128U ) 373 #define Eth_GetEgressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U ) 375 #define Eth_GetIngressFifoPacketNum(CtrlIndex, FifoIdx) ( 128U ) 376 #define Eth_GetIngressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U ) 378 #define Eth_GetEgressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)] ) 379 #define Eth_GetEgressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)].bufferInfo ) 380 #define Eth_GetEgressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_BufferMem_0[(DescIdx) * 1536U] ) 381 #define Eth_GetEgressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Egress_Queue_0 ) 382 #define Eth_GetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] ) 383 #define Eth_SetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] = Val ) 385 #define Eth_GetIngressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)] ) 386 #define Eth_GetIngressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)].bufferInfo ) 387 #define Eth_GetIngressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_BufferMem_0[(DescIdx) * 1536U] ) 388 #define Eth_GetIngressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Ingress_Queue_0 ) 389 #define Eth_GetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] ) 390 #define Eth_SetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] = Val ) 392 #define Eth_GetEgressFifoCqIdx(CtrlIndex, FifoIdx) ( 0U ) 393 #define Eth_GetEgressFifoFqIdx(CtrlIndex, FifoIdx) ( 2U ) 394 #define Eth_GetIngressFifoCqIdx(CtrlIndex, FifoIdx) ( 1U ) 395 #define Eth_GetIngressFifoFqIdx(CtrlIndex, FifoIdx) ( 3U ) 397 #define Eth_GetTxChanId(CtrlIndex, ChIdx) ( 30U ) 398 #define Eth_GetTxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 4U ) 399 #define Eth_GetTxChanDepth(CtrlIndex, ChIdx) ( 128U ) 401 #define Eth_GetRxChanId(CtrlIndex, ChIdx) ( 30U ) 402 #define Eth_GetRxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 5U ) 403 #define Eth_GetRxChanFlowTotalNum(CtrlIndex, ChIdx) ( 1U ) 404 #define Eth_GetRxChanFlowStartNum(CtrlIndex, ChIdx) ( 60U ) 406 #define Eth_GetFlowId(CtrlIndex, FlowIdx) ( 60U ) 407 #define Eth_GetFlowCqRingIdx(CtrlIndex, FlowIdx) ( 1U ) 408 #define Eth_GetFlowFqRingIdx(CtrlIndex, FlowIdx) ( 3U ) 410 #define Eth_GetDynRingElemAddress(CtrlIndex, RingIdx) ( &Eth_RingDyn_Ctrl_0[(RingIdx)] ) 412 #define Eth_GetRingHwId(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].hwId ) 413 #define Eth_GetRingTotalElemNum(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].size ) 414 #define Eth_GetRingPriority(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].priority ) 415 #define Eth_GetRingMemBaseAddress(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].memPtr ) 417 #define Eth_GetRingEventRingIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].ringIdx ) 418 #define Eth_GetRingEventGlobalEventNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].globalEvent ) 419 #define Eth_GetRingEventVirtBitNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].virtBitNum ) 420 #define Eth_GetRingEventEventIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].eventIdx ) 421 #define Eth_GetRingEventSrcOffsetNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].srcOffset ) 423 #define Eth_GetEventCoreIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum ) 424 #define Eth_GetEventVirtIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum ) 425 #define Eth_GetEventIrIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum ) 449 typedef struct Eth_CpswConfigType_s
467 typedef struct Eth_Udma_RingCfgType_s
479 typedef struct Eth_Udma_EventCfgType_s
493 typedef struct Eth_Udma_RingEventCfgType_s
511 typedef struct Eth_FifoRingMapCfgType_s
523 typedef struct Eth_ChannelCfgType_s
535 typedef struct Eth_FlowCfgType_s
549 typedef struct Eth_ChannelFlowCfgType_s
561 typedef struct Eth_FifoHandleType_s
583 typedef struct Eth_Udma_CfgType_s
637 typedef struct Eth_VirtualMacConfigType_s
653 typedef struct Eth_ControlerConfigType_s
719 typedef struct Eth_ConfigType_s
729 #define ETH_START_SEC_CONST_UNSPECIFIED 730 #include "Eth_MemMap.h" 736 #define ETH_STOP_SEC_CONST_UNSPECIFIED 737 #include "Eth_MemMap.h" 739 #define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128 740 #include "Eth_MemMap.h" 742 extern VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[196608U];
743 extern VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_Descriptor_0[128U];
745 extern VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Ingress_BufferMem_0[196608U];
746 extern VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Ingress_Descriptor_0[128U];
748 #define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128 749 #include "Eth_MemMap.h" 751 #define ETH_START_SEC_VAR_NO_INIT_8 752 #include "Eth_MemMap.h" 754 extern VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_BufferState_0[128U];
755 extern VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Ingress_BufferState_0[128U];
757 #define ETH_STOP_SEC_VAR_NO_INIT_8 758 #include "Eth_MemMap.h" 760 #define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED 761 #include "Eth_MemMap.h" 763 extern VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_Queue_0[1U];
764 extern VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Ingress_Queue_0[1U];
766 extern VAR(Eth_Udma_RingDynType, ETH_VAR_NO_INIT) Eth_RingDyn_Ctrl_0[6U];
768 #define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED 769 #include "Eth_MemMap.h" 779 #define ETH_START_SEC_CODE 780 #include "Eth_MemMap.h" 789 #define ETH_STOP_SEC_CODE 790 #include "Eth_MemMap.h" uint32 IrIntrNum
Definition: Eth_Cfg.h:485
Eth_PortType macPort
Definition: Eth_Cfg.h:659
uint32 size
Definition: Eth_Cfg.h:473
boolean loopback
Definition: Eth_Cfg.h:669
Eth controller configuration type Configuration related to Eth controller configuration.
Definition: Eth_Cfg.h:653
uint64 * memPtr
Definition: Eth_Cfg.h:469
Eth_FifoHandleType * ingressFifoCfgPtr
Definition: Eth_Cfg.h:595
uint8 totalTxChanNum
Definition: Eth_Cfg.h:623
uint8 virtBitNum
Definition: Eth_Cfg.h:499
Eth_ChannelCfgType * rxChanCfgPtr
Definition: Eth_Cfg.h:603
Eth_Udma_CfgType * dmaCfgPtr
Definition: Eth_Cfg.h:711
boolean enableRxIrq
Definition: Eth_Cfg.h:679
Eth_FifoRingMapCfgType * ingressFifoRingMapCfgPtr
Definition: Eth_Cfg.h:599
Eth_Udma_EventCfgType * eventCfgPtr
Definition: Eth_Cfg.h:585
Eth_CpswConfigType * cpswCfg
Definition: Eth_Cfg.h:709
boolean pollRecvMsgInEthMain
Definition: Eth_Cfg.h:643
uint32 coreIntrNum
Definition: Eth_Cfg.h:481
uint32 ctrlIdx
Definition: Eth_Cfg.h:655
Eth_VirtualMacConfigType * virtualMacCfg
Definition: Eth_Cfg.h:705
uint32 hwId
Definition: Eth_Cfg.h:471
const Eth_Udma_RingEventCfgType Eth_RingEventCfg_Ctrl_0[2U]
Eth flow configuration type Configuration related to flow.
Definition: Eth_Cfg.h:535
Eth_CacheWb cacheWb
Definition: Eth_Cfg.h:685
Eth_EnetType enetType
Definition: Eth_Cfg.h:657
Eth_CacheInv descCacheInv
Definition: Eth_Cfg.h:693
Eth_CacheWbInv descCacheWbInv
Definition: Eth_Cfg.h:689
Eth configuration type Configuration data of all controller.
Definition: Eth_Cfg.h:719
uint8 cqRingIdx
Definition: Eth_Cfg.h:513
uint8 * bufferState
Definition: Eth_Cfg.h:569
Eth_CacheInv ringCacheInv
Definition: Eth_Cfg.h:699
boolean useDefaultMac
Definition: Eth_Cfg.h:665
Eth_DescType * descPtr
Definition: Eth_Cfg.h:565
Eth driver virtual mac configuration data Configuration related to virtual MAC configuration.
Definition: Eth_Cfg.h:637
uint16 demEventNum
Definition: Eth_Cfg.h:703
boolean enableCacheOps
Definition: Eth_Cfg.h:681
Eth_FifoRingMapCfgType * egressFifoRingMapCfgPtr
Definition: Eth_Cfg.h:597
uint32 ctrlAddr
Definition: Eth_Cfg.h:459
const Eth_Udma_EventCfgType Eth_EventCfg_Ctrl_0[2U]
uint16 * demEventCfg
Definition: Eth_Cfg.h:707
#define ETH_CTRL_ID_MAX
Eth max controller ID.
Definition: Eth_Cfg.h:218
uint16 startTxNum
Definition: Eth_Cfg.h:609
uint8 totalRingEventNum
Definition: Eth_Cfg.h:617
Eth_CacheWbInv cacheWbInv
Definition: Eth_Cfg.h:683
Eth_Udma_RingCfgType * ringCfgPtr
Definition: Eth_Cfg.h:587
Eth_QueueType * queuePtr
Definition: Eth_Cfg.h:567
Eth_RpcFwRegistered fwRegisteredCb
Definition: Eth_Cfg.h:645
uint32 cptsAddr
Definition: Eth_Cfg.h:455
uint8 cqRingIdx
Definition: Eth_Cfg.h:537
uint16 rxMtuLength
Definition: Eth_Cfg.h:629
Eth_ChannelFlowCfgType * rxChanFlowCfgPtr
Definition: Eth_Cfg.h:605
Definition: Eth_Cfg.h:479
Eth_Udma_RingDynType * ringDynPtr
Definition: Eth_Cfg.h:589
uint16 startRxNum
Definition: Eth_Cfg.h:611
uint8 * fifoBufferPtr
Definition: Eth_Cfg.h:563
uint32 srcOffset
Definition: Eth_Cfg.h:503
Eth_MdioOperModeType
MDIO operating mode.
Definition: Eth_Cfg.h:437
uint16 elemSize
Definition: Eth_Cfg.h:573
Eth_ChannelCfgType * txChanCfgPtr
Definition: Eth_Cfg.h:601
uint32 ethfwRpcComChId
Definition: Eth_Cfg.h:639
Eth Fifo ring map configuration type Configuration related to fifo map to ring.
Definition: Eth_Cfg.h:511
uint16 flowId
Definition: Eth_Cfg.h:541
Eth_CacheInv cacheInv
Definition: Eth_Cfg.h:687
Definition: Eth_Cfg.h:441
uint8 totalFlowNum
Definition: Eth_Cfg.h:627
const Eth_Udma_RingCfgType Eth_Udma_RingCfg_0[6U]
Eth channel flow configuration type Configuration related to channel flow.
Definition: Eth_Cfg.h:549
boolean enableVirtualMac
Definition: Eth_Cfg.h:701
uint32 globalEvent
Definition: Eth_Cfg.h:501
uint32 cptsRefClockFreq
Definition: Eth_Cfg.h:461
uint32 macAddrLow
Definition: Eth_Cfg.h:663
Eth Fifo configuration type Configuration related to Fifo.
Definition: Eth_Cfg.h:561
uint8 ringIdx
Definition: Eth_Cfg.h:495
Eth_CacheWbInv ringCacheWbInv
Definition: Eth_Cfg.h:695
Eth_MacConnectionType connType
Definition: Eth_Cfg.h:667
Eth Cpsw Configurations type Configuration related to Cpsw data.
Definition: Eth_Cfg.h:449
uint32 cppiClockFreqHz
Definition: Eth_Cfg.h:463
Eth_CacheWb ringCacheWb
Definition: Eth_Cfg.h:697
uint8 totalRxChanNum
Definition: Eth_Cfg.h:625
Eth ring event configuration type Configuration related to ring event.
Definition: Eth_Cfg.h:493
uint8 totalEgressFifoNum
Definition: Eth_Cfg.h:619
Eth_MdioOperModeType mdioOpMode
Definition: Eth_Cfg.h:675
boolean enableTxIrq
Definition: Eth_Cfg.h:677
uint32 virtIntrNum
Definition: Eth_Cfg.h:483
void EthApp_invCache(uint8 *buf, uint16 len)
Function to invalidate cache.
uint8 fqRingIdx
Definition: Eth_Cfg.h:515
uint8 fifoNum
Definition: Eth_Cfg.h:571
Eth channel configuration type Configuration related to channel.
Definition: Eth_Cfg.h:523
VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[196608U]
uint32 mdioBusFreqHz
Definition: Eth_Cfg.h:673
uint32 macAddrHigh
Definition: Eth_Cfg.h:661
void EthApp_wbCache(uint8 *buf, uint16 len)
Function to write-back cache.
Eth_FlowCfgType * flowCfgPtr
Definition: Eth_Cfg.h:607
Definition: Eth_Cfg.h:439
uint8 eventIdx
Definition: Eth_Cfg.h:497
uint8 totalIngressFifoNum
Definition: Eth_Cfg.h:621
Eth_FifoHandleType * egressFifoCfgPtr
Definition: Eth_Cfg.h:593
uint32 totalSize
Definition: Eth_Cfg.h:575
void EthApp_wbInvCache(uint8 *buf, uint16 len)
Function to write-back and invalidate cache.
Eth_Udma_RingEventCfgType * ringEvenCfgPtr
Definition: Eth_Cfg.h:591
uint32 mdioAddr
Definition: Eth_Cfg.h:457
uint32 phyMacAddr
Definition: Eth_Cfg.h:451
uint8 totalRingNum
Definition: Eth_Cfg.h:615
Eth_RpcCmdComplete rpcCmdComplete
Definition: Eth_Cfg.h:641
uint8 totalEventNum
Definition: Eth_Cfg.h:613
uint8 flowNum
Definition: Eth_Cfg.h:551
uint16 chId
Definition: Eth_Cfg.h:527
uint8 tdCqRingIdx
Definition: Eth_Cfg.h:525
uint8 fqRingIdx
Definition: Eth_Cfg.h:539
uint32 aleAddr
Definition: Eth_Cfg.h:453
uint16 startFlowId
Definition: Eth_Cfg.h:553
Definition: Eth_Cfg.h:467
Eth Udma configuration type Configuration related to Udma.
Definition: Eth_Cfg.h:583
uint32 hwLoopTimeout
Definition: Eth_Cfg.h:671
uint32 priority
Definition: Eth_Cfg.h:475
Eth_CacheWb descCacheWb
Definition: Eth_Cfg.h:691