2.1. Release Notes - 08_04_00

2.1.1. Introduction

This release notes provides important information that will assist you in using the PDK software package for the Jacinto family of devices. This document provides the product information and known issues that are specific to the PDK software package.

New features added / supported is listed below and defects fixed are highlighted in Fixed Issues. Also please check Upgrade and Compatibility for backward compatibility

2.1.2. What’s New

ID Description Module Supported Platforms
PDK-11091 PDK shall support running SafeRTOS Integration Tests running on C7x OSAL J721E
PDK-9535 PDK shall support running SafeRTOS Integration Tests running on C66 OSAL J721E
PDK-11707 SafeRTOS Support on C6x for CPU OSAL J721E
PDK-9547 SafeRTOS Support on C7x for CPU OSAL J721E
PDK-9546 SafeRTOS Support on R5 for CPU OSAL J721E

2.1.3. Upgrade and Compatibility SBL

  • We have modified the CPU IDs for all cores due to an increase in the number of cores in latest Jacinto device. E.g. CPU Id of mcu1_0 has been updated from 4 to 8.
  • Hence user needs to generate the new app image with the current release to use the latest SBL.
  • CPU IDs corresponding to each core can be found here: <pdk_base>/packages/ti/build/makerules/platform.mk. SPI

  • Previously SPI_open supported only 5 instances of McSPI(3 MCU instances and 2 Main Instances). Now separate APIs are implemented for McSPI and OSPI in order to support all the instances, user needs to use specific APIs as per the peripheral. E.g. User should use SPI_open() for McSPI and OSPI_open() for OSPI. FreeRTOS

  • On C66x CPU, interrupt router configurations for OS ticks is now handled in the OS_init() by FreeRTOS OSAL layer. Previously this configuration was done by application which is no longer needed.

2.1.4. Device Support

  • J721E SR1.1, J721E-HS SR1.1 (BOARD=j721e_evm)

  • Associated TIFS versions:

    TIFS name J721E SR revision
    tifs.bin SR1.0 & SR1.1 GP
    tifs-hs-enc.bin SR1.0 HS
    tifs-sr1.1-hs-enc.bin SR1.1 HS

2.1.5. Validation Information

For details on the validated examples refer to the platform specific test report available here.

2.1.6. Tool Chain Information

Component Version
FreeRTOS Kernel 10.4.3
lwIP stack 2.1.2
lwIP-contrib 2.1.0
PRU code generation tools 2.3.3
GCC ARM code generation tools ARCH64 9.2-2019.12
CGT XML Processing Scripts 2.61.00
System Analyzer (UIA Target) 2_30_01_02
Component Version
TI C6x code generation tools 8.3.7
TI C7x code generation tools 3.0.0.STS

2.1.7. Change Request

ID Head Line Original Fix Version New Fix Version

2.1.8. Fixed Issues

ID Head Line Module Affected Versions Affected Platforms
PDK-8407 J721E: MCU Timer 0 is not usable from application (sysbios) with SBL OSAL, SBL 07.01.00 J721E
PDK-10314 [DSS]: Add support for lane speed for the DSI output DSS 07.03.00 J721E
PDK-11152 SPI driver does not support all instances with SPI_open McSPI 08.02.00 J721E, J7200
PDK-11388 [SBL] SBL should not copy build folder contents to board folder during packaging SBL 08.01.00 J721E, J7200
PDK-11093 ACK/NACK is send for TISCI messages without AOP flag Sciclient 08.01.00 J721E, J7200, J721S2
PDK-11227 UART instances 3-9 does not work on MAIN R5 in interrupt mode UART 08.01.00 J721E, J7200, J721S2
PDK-11004 DMA Utils examples are broken with SDK UDMA 08.00.00 J721E
PDK-11022 Sciclient_pmSetModuleClkFreq returns fail when called from SBL_SlaveCoreBoot for c66 SBL 08.00.00 J721E
PDK-11130 M2M colour space conversion from RGB24 to YUV420SP fails DSS 08.02.00 J721E
PDK-11158 CSL: Sierra SerDes Instance 1 Lane Control is Incorrect CSL 08.01.00 J721E
PDK-11238 DSS M2M testapp fails when run for scaling DSS 08.02.00 J721E
PDK-11270 Facing issue with resolution change in DSS_M2M node DSS 08.01.00 J721E
PDK-11460 Fix FreeRTOS Static Analysis Issues OSAL 08.02.00 J721E
PDK-11559 Timer Frequency is hard coded in OSAL layer OSAL 08.02.00 J721E, J721S2
PDK-11861 Unable to program PVU CSL 08.02.00 J721E, J7200
PDK-11975 OCMC RAM used by Sciserver FreeRTOS Testapp may cause memory conflict SCICLIENT 08.02.00 J721E, J7200, J721S2
PDK-11996 Issue with UNIFLASH 7.2.0 with J7ES UNIFLASH 08.02.00 J721E
PDK-12001 CSITX transmitted frames dont match the Received frame. CSI2TX 08.04.00 J721E
PDK-12022 C7x Compiler is not packaged correctly in Windows Installer COMMON 08.02.00 J721E
PDK-12030 UART DMA hangs on mcu1_1 UART 08.00.00 J721E
PDK-12050 CCS can not resolve source to various PDK components COMMON 08.02.00 J721E
PDK-12112 freertos: c7x: _stack array defined in freertos portable layer is of insufficent size OSAL 08.00.00 J721E, J721S2
PDK-12140 DSS frame freeze detection happens only on 1 video pipe at a time DSS 08.02.00 J721E, J721S2

2.1.9. Known Issues

ID Head Line Module Reported in Release Affected Platforms Impact Workaround in this release
PDK-6975 Pulsar (R5F) : High priority interrupt is missed by VIM CSL, OSAL 07.00.00 J721E, J7200 Baremetal implementation is pending Use RTOS instead of baremetal
PDK-9676 UART : Potential interrupt storm UART 07.02.00 J7200, J721E Error interrupt resulting in hang. None
PDK-9696 [SPI] DMA mode does not work for SPI5 McSPI 07.01.00 J721E Cannot use DMA with SPI5 Disable DMA for SPI5 OR use another instance of SPI
PDK-9571 [SPI] Transfer stalls when transfer length is not multiple of FIFO length in DMA mode McSPI 07.02.00 J721E Cannot transfer data if data size is not multiple of FIFO length in DMA mode Use transfer size in multiple of FIFO length
PDK-8300 UDMA MCU NAVSS Channel Num 5 is not functional, when booting the application using the SBL bootloader. UDMA 07.01.00 J721E Low Impact. UDMA MCU NAVSS Channel 5 can’t be used when booting the application using the SBL bootloader. Use any other channel. In the defaultBoardCfg Channel no. 5 is not used. The issue will be seen only when the boardcfg is updated to use channel 5.
PDK-6789 MCU/Main NAVSS UDMA memcpy from L2SRAM fails UDMA 07.00.00 J721E Transfer works fine when source buffer, destination buffer and TRPD buffers are in L2SRAM. The issue happens only when the ring memory is in L2SRAM location Use ring memory from non-L2SRAM location
PDK-5228 Output mismatch when each region requiring 3 TRs VHWA 01.00.00 J721E In multi-region mode with more then 3 TR per region can’t be used In multi-region mode for each region less than 3 TR should be used
PDK-9528 SBL prebuild binary for J721E HS doesn’t work from package SBL 07.03.00 J721E-HS None Cleanup the SBL library and re-build the SBL image for HS. Commands: - Clean sbl_lib_uart (make sbl_lib_uart_clean) - Build for HS (make -sj sbl_uart_img_hs)
PDK-10292 Sciclient Firewall Testapp Fails on HS Device SCICLIENT 07.03.00 J721E-HS None None
PDK-10925 IPC Performance Test hangs after loading the binary IPC 08.01.00 J721E, J7200 The app won’t work for this release None
PDK-11085 SPI instance should be decided by SPI driver and not Board Module OSPI 08.01.00 J721E, J7200 None None
PDK-11240 keywriter: smek gets generated even when argument not specified Security 08.01.00 J721E, J7200 None None
PDK-11457 MCU Only Mode: IPC attachment with remote cores fail LPM 08.02.00 J721E None None
PDK-11458 MCU Only Mode - Linux boot fails on A72 core LPM 08.02.00 J721E None None
PDK-11237 CSI-Rx UT hangs when run on mcu2_0 CSI2RX 08.02.00 J721E, J721S2 None None
PDK-11854 USART: Spurious DMA Interrupts UART 08.04.00 J721E, J7200, J721S2 None None
PDK-11973 USART: Erroneous clear/trigger of timeout interrupt UART 08.02.00 J721E, J7200, J721S2 None None
PDK-12023 Heap OSAL hangs if previous allocation has buffer overflow OSAL 08.02.00 J721E, J721S2 None None
PDK-12060 Main Domain GPIO does not service interrupts GPIO 08.04.00 J721E, J7200 None None
PDK-12065 [CSIRX]: RAW12 packed output format is not working CSI2RX 08.02.00 J721E, J721S2 None None
PDK-12080 taskFxn parameter is not pointer to function in TaskP_create OSAL 08.02.00 J721E, J721S2 None None
PDK-12107 DM: UART Traces are not working with Linux SDK PM 08.02.00 J721E, J7200 None None
PDK-12154 SBL: HS boot flow should unlock ROM firewalls SBL 08.02.00 J721E None None
PDK-12164 Incorrect DDR End Address with ECC enabled BOARD 08.02.00 J721E, J7200 None None

2.1.10. Limitations PDK

  • PDK examples do not support SMP mode. Some of examples still support build in SMP mode but these binaries are not supported or validated.
  • TI Clang compiler does not enable O3 optimization level and Thumb2 mode which were enabled by default with TI ARM CGT compiler. This has an impact on driver throughput. E.g. Ethernet performance has reduced by ~20% on J721E ENET

  • lwIP stack integration doesn’t support checksum hardware-offload feature.