TI Deep Learning Product User Guide
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This structure defines the system memory handles in TIDL There are total four handles: 0: L1, 1:L2, 2:L3 and 3:DDR.
This is scratch memory and it can be used while implementing custom layer. The life of this memory is only within the context of the specific custom layer and shall not be assumed to be available after completion of processing for that custom layer
base | Base address of system memory |
size | Size of the system memory |
offset | Offset up to which system memory is already occupied |
Data Fields | |
void * | base |
int32_t | size |
int32_t | offset |
void* sTIDL_sysMemHandle_t::base |
int32_t sTIDL_sysMemHandle_t::size |
int32_t sTIDL_sysMemHandle_t::offset |