TI Deep Learning Product User Guide
sTIDL_sysMemHandle_t Struct Reference

Detailed Description

This structure defines the system memory handles in TIDL There are total four handles: 0: L1, 1:L2, 2:L3 and 3:DDR.

This is scratch memory and it can be used while implementing custom layer. The life of this memory is only within the context of the specific custom layer and shall not be assumed to be available after completion of processing for that custom layer

Parameters
baseBase address of system memory
sizeSize of the system memory
offsetOffset up to which system memory is already occupied

Data Fields

void * base
 
int32_t size
 
int32_t offset
 

Field Documentation

◆ base

void* sTIDL_sysMemHandle_t::base

◆ size

int32_t sTIDL_sysMemHandle_t::size

◆ offset

int32_t sTIDL_sysMemHandle_t::offset