SDL API Guide for J721E
Macros
sdl_esm_core.h File Reference

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Macros

#define SDL_MCU_ESM_HI_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_HI_LVL_0
 
#define SDL_MCU_ESM_LO_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_LOW_LVL_0
 
#define SDL_MCU_ESM_CFG_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_CFG_LVL_0
 
#define SDL_WKUP_ESM_HI_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_HI_LVL_0
 
#define SDL_WKUP_ESM_LO_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_LOW_LVL_0
 
#define SDL_WKUP_ESM_CFG_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_CFG_LVL_0
 
#define SDL_MAIN_ESM_HI_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_HI_LVL_0
 
#define SDL_MAIN_ESM_LO_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_LOW_LVL_0
 
#define SDL_MAIN_ESM_CFG_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_CFG_LVL_0
 
#define SDL_ESM_MCU_R5_CORE0_SEC_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0
 
#define SDL_ESM_MCU_R5_CORE0_DED_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
 
#define SDL_ESM_MCU_R5_CORE1_SEC_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0
 
#define SDL_ESM_MCU_R5_CORE1_DED_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0
 
#define SDL_ESM_MCU_RTI0_WWD_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_RTI0_INTR_WWD_0
 
#define SDL_ESM_MCU_RTI1_WWD_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_RTI1_INTR_WWD_0
 
#define SDL_ESM_MAIN_ESM_ERROR_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_GLUELOGIC_ESM_MAIN_ERR_GLUE_ERR_I_N_0
 
#define SDL_ESM_MCU_R5_SELFTEST_ERR_INT   SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_SELFTEST_ERR_PULSE_0
 
#define SDL_ESM_MCU_R5_CPU_BUS_CMP_ERR   SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMPARE_ERR_PULSE_0
 
#define SDL_ESM_MCU_R5_INACTIVITY_ERR_INT   SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_BUS_MONITOR_ERR_PULSE_0
 
#define SDL_ESM_MCU_R5_VIM_BUS_CMP_ERR_INT   SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_VIM_COMPARE_ERR_PULSE_0
 
#define SDL_ESM_MCU_R5_CCM_STAT_ERR_INT   SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0
 
#define SDL_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_0
 
#define SDL_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_1
 
#define SDL_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_2
 
#define SDL_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_3
 
#define SDL_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_4
 
#define SDL_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_5
 
#define SDL_ESM_MAIN_A72_ECC_AGGR0_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_7
 
#define SDL_ESM_MAIN_A72_ECC_AGGR0_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_8
 
#define SDL_ESM_MAIN_A72_ECC_AGGR1_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_9
 
#define SDL_ESM_MAIN_A72_ECC_AGGR1_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_10
 
#define SDL_ESM_MAIN_A72_ECC_AGGR2_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_11
 
#define SDL_ESM_MAIN_A72_ECC_AGGR2_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_12
 
#define SDL_ESM_MCU_CBASS_ECC_AGGR_SEC_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0
 
#define SDL_ESM_MCU_CBASS_ECC_AGGR_DED_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0
 

Macro Definition Documentation

◆ SDL_MCU_ESM_HI_INTNO

#define SDL_MCU_ESM_HI_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_HI_LVL_0

◆ SDL_MCU_ESM_LO_INTNO

#define SDL_MCU_ESM_LO_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_LOW_LVL_0

◆ SDL_MCU_ESM_CFG_INTNO

#define SDL_MCU_ESM_CFG_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_CFG_LVL_0

◆ SDL_WKUP_ESM_HI_INTNO

#define SDL_WKUP_ESM_HI_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_HI_LVL_0

◆ SDL_WKUP_ESM_LO_INTNO

#define SDL_WKUP_ESM_LO_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_LOW_LVL_0

◆ SDL_WKUP_ESM_CFG_INTNO

#define SDL_WKUP_ESM_CFG_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_CFG_LVL_0

◆ SDL_MAIN_ESM_HI_INTNO

#define SDL_MAIN_ESM_HI_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_HI_LVL_0

◆ SDL_MAIN_ESM_LO_INTNO

#define SDL_MAIN_ESM_LO_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_LOW_LVL_0

◆ SDL_MAIN_ESM_CFG_INTNO

#define SDL_MAIN_ESM_CFG_INTNO   SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_CFG_LVL_0

◆ SDL_ESM_MCU_R5_CORE0_SEC_INT

#define SDL_ESM_MCU_R5_CORE0_SEC_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0

◆ SDL_ESM_MCU_R5_CORE0_DED_INT

#define SDL_ESM_MCU_R5_CORE0_DED_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0

◆ SDL_ESM_MCU_R5_CORE1_SEC_INT

#define SDL_ESM_MCU_R5_CORE1_SEC_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0

◆ SDL_ESM_MCU_R5_CORE1_DED_INT

#define SDL_ESM_MCU_R5_CORE1_DED_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0

◆ SDL_ESM_MCU_RTI0_WWD_INT

#define SDL_ESM_MCU_RTI0_WWD_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_RTI0_INTR_WWD_0

◆ SDL_ESM_MCU_RTI1_WWD_INT

#define SDL_ESM_MCU_RTI1_WWD_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_RTI1_INTR_WWD_0

◆ SDL_ESM_MAIN_ESM_ERROR_INT

#define SDL_ESM_MAIN_ESM_ERROR_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_GLUELOGIC_ESM_MAIN_ERR_GLUE_ERR_I_N_0

◆ SDL_ESM_MCU_R5_SELFTEST_ERR_INT

#define SDL_ESM_MCU_R5_SELFTEST_ERR_INT   SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_SELFTEST_ERR_PULSE_0

◆ SDL_ESM_MCU_R5_CPU_BUS_CMP_ERR

#define SDL_ESM_MCU_R5_CPU_BUS_CMP_ERR   SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMPARE_ERR_PULSE_0

◆ SDL_ESM_MCU_R5_INACTIVITY_ERR_INT

#define SDL_ESM_MCU_R5_INACTIVITY_ERR_INT   SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_BUS_MONITOR_ERR_PULSE_0

◆ SDL_ESM_MCU_R5_VIM_BUS_CMP_ERR_INT

#define SDL_ESM_MCU_R5_VIM_BUS_CMP_ERR_INT   SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_VIM_COMPARE_ERR_PULSE_0

◆ SDL_ESM_MCU_R5_CCM_STAT_ERR_INT

#define SDL_ESM_MCU_R5_CCM_STAT_ERR_INT   SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0

◆ SDL_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT

#define SDL_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_0

◆ SDL_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT

#define SDL_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_1

◆ SDL_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT

#define SDL_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_2

◆ SDL_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT

#define SDL_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_3

◆ SDL_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT

#define SDL_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_4

◆ SDL_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT

#define SDL_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_5

◆ SDL_ESM_MAIN_A72_ECC_AGGR0_DED_INT

#define SDL_ESM_MAIN_A72_ECC_AGGR0_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_7

◆ SDL_ESM_MAIN_A72_ECC_AGGR0_SEC_INT

#define SDL_ESM_MAIN_A72_ECC_AGGR0_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_8

◆ SDL_ESM_MAIN_A72_ECC_AGGR1_DED_INT

#define SDL_ESM_MAIN_A72_ECC_AGGR1_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_9

◆ SDL_ESM_MAIN_A72_ECC_AGGR1_SEC_INT

#define SDL_ESM_MAIN_A72_ECC_AGGR1_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_10

◆ SDL_ESM_MAIN_A72_ECC_AGGR2_DED_INT

#define SDL_ESM_MAIN_A72_ECC_AGGR2_DED_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_11

◆ SDL_ESM_MAIN_A72_ECC_AGGR2_SEC_INT

#define SDL_ESM_MAIN_A72_ECC_AGGR2_SEC_INT   SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_12

◆ SDL_ESM_MCU_CBASS_ECC_AGGR_SEC_INT

#define SDL_ESM_MCU_CBASS_ECC_AGGR_SEC_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0

◆ SDL_ESM_MCU_CBASS_ECC_AGGR_DED_INT

#define SDL_ESM_MCU_CBASS_ECC_AGGR_DED_INT   SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0