sdl_ecc_soc.h File Reference

Go to the source code of this file.

Macros
#define	SDL_ECC_WIDTH_UNDEFINED   0x1
#define	SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)
#define	SDL_MAIN_AC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES   (7U)
#define	SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (32U)
#define	SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)
#define	SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (68U)
#define	SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (20U)
#define	SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (7U)
#define	SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (7U)
#define	SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (26U)
#define	SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES   (7U)
#define	SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)
#define	SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (10U)
#define	SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (34U)
#define	SDL_MCU_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES   (7U)
#define	SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_NAVSS0_NBSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_IDOM1_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_IDOM1_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)
#define	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)
#define	SDL_MCU_I3C1_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (14U)
#define	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES   (5U)
#define	SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES   (7U)
#define	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (59U)
#define	SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (24U)
#define	SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (24U)
#define	SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)
#define	SDL_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (72U)
#define	SDL_MAIN_RC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)
#define	SDL_MAIN_HC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)
#define	SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_NAVSS_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (6U)
#define	SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (20U)
#define	SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)
#define	SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION   (2U)
#define	SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES   (SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR+1u)
#define	SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES
#define	SDL_ECC_AGGREGATOR_MAX_ENTRIES

Variables
static const SDL_MemConfig_t	SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries [SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_MemEntries [SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries [SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_groupEntries [SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PCIE2_ECC_AGGR_CORE_0_MemEntries [SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_MemEntries [SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries [SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_MemEntries [SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_groupEntries [SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_MemEntries [SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PCIE2_ECC_AGGR_CORE_AXI_0_MemEntries [SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries [SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MemEntries [SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_MemEntries [SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_I3C0_I3C_S_ECC_AGGR_MemEntries [SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_MemEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_MemEntries [SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries [SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries [SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries [SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_MemEntries [SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries [SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_MemEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries [SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries [SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PCIE0_ECC_AGGR_CORE_0_MemEntries [SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries [SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries [SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PCIE0_ECC_AGGR_CORE_AXI_0_MemEntries [SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries [SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_I3C0_I3C_S_ECC_AGGR_MemEntries [SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_VPAC0_ECC_AGGR_MemEntries [SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries [SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries [SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_groupEntries [SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries [SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_MemEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_groupEntries [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries [SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PCIE1_ECC_AGGR_CORE_0_MemEntries [SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries [SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries [SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_MemEntries [SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries [SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries [SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_MemEntries [SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PCIE1_ECC_AGGR_CORE_AXI_0_MemEntries [SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries [SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries [SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries [SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_MemEntries [SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_groupEntries [SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_I3C1_I3C_S_ECC_AGGR_MemEntries [SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries [SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_MemEntries [SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_MemEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries [SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_MemEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_MemEntries [SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries [SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PCIE3_ECC_AGGR_CORE_0_MemEntries [SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_MemEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MemEntries [SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries [SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_MemEntries [SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_MemEntries [SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_groupEntries [SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_MemEntries [SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_groupEntries [SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MemEntries [SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries [SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries [SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries [SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PCIE3_ECC_AGGR_CORE_AXI_0_MemEntries [SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries [SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries [SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries [SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_CBASS_ECC_AGGR0_MemEntries [SDL_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_groupEntries [SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_groupEntries [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_DMPAC0_ECC_AGGR_MemEntries [SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries [SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries [SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MemEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_VPAC0_LDC_ECC_AGGR_MemEntries [SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries [SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries [SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries [SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MemEntries [SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_CBASS_ECC_AGGR0_MemEntries [SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_groupEntries [SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_VPAC0_VISS_ECC_AGGR_MemEntries [SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MemEntries [SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0_groupEntries [SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries [SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MemEntries [SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_RAMIdEntry_t	SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable [SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MAIN_AC_ECC_AGGR0_RamIdTable [SDL_MAIN_AC_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RamIdTable [SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RamIdTable [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE2_ECC_AGGR_CORE_0_RamIdTable [SDL_PCIE2_ECC_AGGR_CORE_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RamIdTable [SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RamIdTable [SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RamIdTable [SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RamIdTable [SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RamIdTable [SDL_PCIE2_ECC_AGGR_CORE_AXI_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RamIdTable [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RamIdTable [SDL_MCU_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RamIdTable [SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_I3C0_I3C_S_ECC_AGGR_RamIdTable [SDL_MCU_I3C0_I3C_S_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable [SDL_NAVSS0_UDMASS_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RamIdTable [SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable [SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable [SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RamIdTable [SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_NAVSS0_MODSS_ECC_AGGR0_RamIdTable [SDL_NAVSS0_MODSS_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable [SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE0_ECC_AGGR_CORE_0_RamIdTable [SDL_PCIE0_ECC_AGGR_CORE_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable [SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable [SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RamIdTable [SDL_PCIE0_ECC_AGGR_CORE_AXI_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_I3C0_I3C_S_ECC_AGGR_RamIdTable [SDL_I3C0_I3C_S_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_VPAC0_ECC_AGGR_RamIdTable [SDL_VPAC0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_NAVSS0_VIRTSS_ECC_AGGR0_RamIdTable [SDL_NAVSS0_VIRTSS_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_I3C0_I3C_P_ECC_AGGR_RamIdTable [SDL_MCU_I3C0_I3C_P_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE1_ECC_AGGR_CORE_0_RamIdTable [SDL_PCIE1_ECC_AGGR_CORE_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable [SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RamIdTable [SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_NAVSS0_NBSS_ECC_AGGR0_RamIdTable [SDL_NAVSS0_NBSS_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RamIdTable [SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM1_ECC_AGGR0_RamIdTable [SDL_IDOM1_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM1_ECC_AGGR1_RamIdTable [SDL_IDOM1_ECC_AGGR1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_RamIdTable [SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RamIdTable [SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RamIdTable [SDL_PCIE1_ECC_AGGR_CORE_AXI_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable [SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable [SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RamIdTable [SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RamIdTable [SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_I3C1_I3C_S_ECC_AGGR_RamIdTable [SDL_MCU_I3C1_I3C_S_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_I3C1_I3C_P_ECC_AGGR_RamIdTable [SDL_MCU_I3C1_I3C_P_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RamIdTable [SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RamIdTable [SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable [SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RamIdTable [SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RamIdTable [SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RamIdTable [SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE3_ECC_AGGR_CORE_0_RamIdTable [SDL_PCIE3_ECC_AGGR_CORE_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable [SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RamIdTable [SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RamIdTable [SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RamIdTable [SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RamIdTable [SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RamIdTable [SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable [SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable [SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RamIdTable [SDL_PCIE3_ECC_AGGR_CORE_AXI_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_I3C0_I3C_P_ECC_AGGR_RamIdTable [SDL_I3C0_I3C_P_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable [SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CBASS_ECC_AGGR0_RamIdTable [SDL_CBASS_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MAIN_RC_ECC_AGGR0_RamIdTable [SDL_MAIN_RC_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RamIdTable [SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RamIdTable [SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RamIdTable [SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DMPAC0_ECC_AGGR_RamIdTable [SDL_DMPAC0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MAIN_HC_ECC_AGGR0_RamIdTable [SDL_MAIN_HC_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RamIdTable [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RamIdTable [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RamIdTable [SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_VPAC0_LDC_ECC_AGGR_RamIdTable [SDL_VPAC0_LDC_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable [SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_NAVSS_VIRTSS_ECC_AGGR0_RamIdTable [SDL_NAVSS_VIRTSS_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RamIdTable [SDL_MCU_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_CBASS_ECC_AGGR0_RamIdTable [SDL_MCU_CBASS_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_VPAC0_VISS_ECC_AGGR_RamIdTable [SDL_VPAC0_VISS_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_RamIdTable [SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable [SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RamIdTable [SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_NUM_RAMS]
static SDL_ecc_aggrRegs *const	SDL_ECC_aggrBaseAddressTable [SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES]
	This structure holds the base addresses for each memory subtype in MCU domain More...
static uint64_t const	SDL_ECC_aggrHighBaseAddressTable [SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]
SDL_ecc_aggrRegs *	SDL_ECC_aggrHighBaseAddressTableTrans [SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]
static const SDL_EccAggrEntry_t	SDL_ECC_aggrTable [SDL_ECC_MEMTYPE_MAX]

Macro Definition Documentation

SDL_ECC_WIDTH_UNDEFINED

#define SDL_ECC_WIDTH_UNDEFINED   0x1

SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)

SDL_MAIN_AC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MAIN_AC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RAM_IDS_TOTAL_ENTRIES

#define SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES   (7U)

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (32U)

SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES

#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RAM_IDS_TOTAL_ENTRIES

#define SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES

#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)

SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (68U)

SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (20U)

SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (7U)

SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (7U)

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (26U)

SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES   (7U)

SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)

SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (10U)

SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (34U)

SDL_MCU_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES   (7U)

SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_NAVSS0_NBSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_NAVSS0_NBSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_IDOM1_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM1_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_IDOM1_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM1_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)

SDL_MCU_I3C1_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_I3C1_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES

#define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (14U)

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES

#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES   (5U)

SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES

#define SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES   (7U)

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (59U)

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (24U)

SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (24U)

SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)

SDL_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (72U)

SDL_MAIN_RC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MAIN_RC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RAM_IDS_TOTAL_ENTRIES

#define SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)

SDL_MAIN_HC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MAIN_HC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)

SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_NAVSS_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_NAVSS_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (6U)

SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (20U)

SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)

SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION

#define SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION   (2U)

---

This structure holds the memory config for each memory subtype SDL_MCU_R5FSS0_CORE0_ECC_AGGR

SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES

#define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES   (SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR+1u)

SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES

#define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES

Value:

(SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR - \
                                           SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)

SDL_ECC_AGGREGATOR_MAX_ENTRIES

#define SDL_ECC_AGGREGATOR_MAX_ENTRIES

Value:

(SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES + \
                                        SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES)

Variable Documentation

SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL RAM ID

SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_RAM_ID, 0u,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR

SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0 RAM ID

SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_groupEntries[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_PCIE2_ECC_AGGR_CORE_0_MemEntries

const SDL_MemConfig_t SDL_PCIE2_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PCIE2_ECC_AGGR_CORE_0

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_MemEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC RAM ID

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0 RAM ID

SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0 RAM ID

SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_MemEntries

const SDL_MemConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_MemEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_groupEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0 RAM ID

SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM

SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_PCIE2_ECC_AGGR_CORE_AXI_0_MemEntries

const SDL_MemConfig_t SDL_PCIE2_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PCIE2_ECC_AGGR_CORE_AXI_0

SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL RAM ID

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_MemEntries

const SDL_MemConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_MemEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_LB_TPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_LB_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_LB_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_S_TPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_S_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_S_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_D_TPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_D_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_D_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_OB0_TPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_OB0_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_OB0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_LB_TPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_LB_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_LB_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_S_TPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_S_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_S_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_D_TPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_D_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_D_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_OB0_TPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_OB0_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_OB0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC

SDL_MCU_I3C0_I3C_S_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_I3C0_I3C_S_ECC_AGGR_MemEntries[SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBI_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBI_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBI_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_I3C0_I3C_S_ECC_AGGR

SDL_NAVSS0_UDMASS_ECC_AGGR0_MemEntries

const SDL_MemConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_MemEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_NAVSS0_UDMASS_ECC_AGGR0

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_MemEntries[SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR

SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS1_CORE1_ECC_AGGR

SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL RAM ID

SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL RAM ID

SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL RAM ID

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0 RAM ID

SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR

SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0 RAM ID

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_MemEntries

const SDL_MemConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_MemEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_NAVSS0_MODSS_ECC_AGGR0

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1 RAM ID

SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_CORE0_ECC_AGGR

SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL RAM ID

SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL RAM ID

SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL RAM ID

SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL RAM ID

SDL_PCIE0_ECC_AGGR_CORE_0_MemEntries

const SDL_MemConfig_t SDL_PCIE0_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PCIE0_ECC_AGGR_CORE_0

SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries[SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM

SDL_PCIE0_ECC_AGGR_CORE_AXI_0_MemEntries

const SDL_MemConfig_t SDL_PCIE0_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PCIE0_ECC_AGGR_CORE_AXI_0

SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0 RAM ID

SDL_I3C0_I3C_S_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_I3C0_I3C_S_ECC_AGGR_MemEntries[SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_ID, 0u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_SIZE, 4u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_ID, 0u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_SIZE, 4u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_ID, 0u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_SIZE, 4u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_ID, 0u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_SIZE, 4u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBI_RAM_ID, 0u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBI_RAM_SIZE, 4u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBI_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_ID, 0u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_SIZE, 4u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_ID, 0u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_SIZE, 4u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_ID, 0u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_SIZE, 4u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_ID, 0u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_SIZE, 4u,
      SDL_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_I3C0_I3C_S_ECC_AGGR

SDL_VPAC0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_VPAC0_ECC_AGGR_MemEntries[SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_VPAC0_ECC_AGGR

SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0 RAM ID

SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0 RAM ID

SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0 RAM ID

SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_MemEntries

const SDL_MemConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_MemEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_NAVSS0_VIRTSS_ECC_AGGR0

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_0_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_1_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_2_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_3_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_4_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_5_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0 RAM ID

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1 RAM ID

SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries[SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0 RAM ID

SDL_PCIE1_ECC_AGGR_CORE_0_MemEntries

const SDL_MemConfig_t SDL_PCIE1_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PCIE1_ECC_AGGR_CORE_0

SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS1_CORE0_ECC_AGGR

SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL RAM ID

SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL RAM ID

SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL RAM ID

SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL RAM ID

SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_MemEntries[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_RAM_ID, 0u,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR

SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0 RAM ID

SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL RAM ID

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_PCIE1_ECC_AGGR_CORE_AXI_0_MemEntries

const SDL_MemConfig_t SDL_PCIE1_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PCIE1_ECC_AGGR_CORE_AXI_0

SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0 RAM ID

SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries[SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries[SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID, 0u,
      SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID, 0u,
      SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR

SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_MemEntries[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_RAM_ID, 0u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_RAM_SIZE, 4u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR

SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0 RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCU_I3C1_I3C_S_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_I3C1_I3C_S_ECC_AGGR_MemEntries[SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBI_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBI_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBI_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD1_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_TX_DATA_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD0_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_RX_DATA_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_I3C1_I3C_S_ECC_AGGR

SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries[SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0 RAM ID

SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_MemEntries

const SDL_MemConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_MemEntries[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_MemEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_RAM_ID, 0u,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_RAM_SIZE, 4u,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_RAM_ID, 0u,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_RAM_SIZE, 4u,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7 RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries[SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_MemEntries

const SDL_MemConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_MemEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_MCU_NAVSS0_MODSS_ECC_AGGR0

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1 RAM ID

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_MemEntries

const SDL_MemConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_MemEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_RAM_ID, 0u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY

SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries[SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0 RAM ID

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_PCIE3_ECC_AGGR_CORE_0_MemEntries

const SDL_MemConfig_t SDL_PCIE3_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PCIE3_ECC_AGGR_CORE_0

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_MemEntries

const SDL_MemConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_MemEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1 RAM ID

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_RAM_ID, 0u,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0 RAM ID

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_MemEntries[SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR

SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_MemEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR

SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0 RAM ID

SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_MemEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR

SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1 RAM ID

SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_RAM_ID, 0u,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR

SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0 RAM ID

SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM

SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries[SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID, 0u,
      SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID, 0u,
      SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR

SDL_PCIE3_ECC_AGGR_CORE_AXI_0_MemEntries

const SDL_MemConfig_t SDL_PCIE3_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PCIE3_ECC_AGGR_CORE_AXI_0

SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0 RAM ID

SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries[SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0 RAM ID

SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR

SDL_CBASS_ECC_AGGR0_MemEntries

const SDL_MemConfig_t SDL_CBASS_ECC_AGGR0_MemEntries[SDL_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_CBASS_ECC_AGGR0

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3 RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS RAM ID

SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS RAM ID

SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL RAM ID

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0 RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS RAM ID

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_11_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2 RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2 RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2 RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2 RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC RAM ID

SDL_DMPAC0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_DMPAC0_ECC_AGGR_MemEntries[SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID, 0u,
      SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_SIZE, 4u,
      SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_ROW_WIDTH, ((bool)false) },
    { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID, 0u,
      SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_SIZE, 4u,
      SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_ROW_WIDTH, ((bool)false) },
    { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_RAM_ID, 0u,
      SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_RAM_SIZE, 4u,
      SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_ROW_WIDTH, ((bool)false) },
    { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID, 0u,
      SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_SIZE, 4u,
      SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_ROW_WIDTH, ((bool)false) },
    { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID, 0u,
      SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_SIZE, 4u,
      SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_DMPAC0_ECC_AGGR

SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries[SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0 RAM ID

SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9 RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC RAM ID

SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MemEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_8_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_9_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_10_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC RAM ID

SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_VPAC0_LDC_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_VPAC0_LDC_ECC_AGGR_MemEntries[SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_VPAC0_LDC_ECC_AGGR

SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_CORE1_ECC_AGGR

SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL RAM ID

SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL RAM ID

SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC RAM ID

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_MCU_R5FSS0_CORE1_ECC_AGGR

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCU_CBASS_ECC_AGGR0_MemEntries

const SDL_MemConfig_t SDL_MCU_CBASS_ECC_AGGR0_MemEntries[SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_ID, 0u,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_ID, 0u,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_RAM_ID, 0u,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_RAM_ID, 0u,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_RAM_ID, 0u,
      SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_RAM_ID, 0u,
      SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_CBASS_ECC_AGGR0

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS RAM ID

SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3 RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL RAM ID

SDL_VPAC0_VISS_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_VPAC0_VISS_ECC_AGGR_MemEntries[SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_VPAC0_VISS_ECC_AGGR

SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MemEntries[SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)false) },
    { SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_CTRL_BUSECC_RAM_ID, 0u,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_CTRL_BUSECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR

SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0 RAM ID

SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries[SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR

SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MemEntries[SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_ID, 0u,
      SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_SIZE, 4u,
      SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR

SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR

SDL_MAIN_AC_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_MAIN_AC_ECC_AGGR0_RamIdTable[SDL_MAIN_AC_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MAIN_AC_ECC_AGGR0

SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_RAM_ID,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_INJECT_TYPE,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_RAM_ID,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_INJECT_TYPE,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_ECC_TYPE,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries },
    { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_RAM_ID,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_INJECT_TYPE,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_ECC_TYPE,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RamIdTable

const SDL_RAMIdEntry_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RamIdTable[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL

SDL_PCIE2_ECC_AGGR_CORE_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE2_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE2_ECC_AGGR_CORE_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE2_ECC_AGGR_CORE_0

SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR

SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RamIdTable

const SDL_RAMIdEntry_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RamIdTable[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_NUM_RAMS]

static

Initial value:

=
{
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_RAM_ID,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_INJECT_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_RAM_ID,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_INJECT_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_RAM_ID,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_INJECT_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_ECC_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE

SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM

SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE2_ECC_AGGR_CORE_AXI_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE2_ECC_AGGR_CORE_AXI_0

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RamIdTable

const SDL_RAMIdEntry_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RamIdTable[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG

SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_R5FSS0_CORE0_ECC_AGGR

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RamIdTable

const SDL_RAMIdEntry_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RamIdTable[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC

SDL_MCU_I3C0_I3C_S_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_I3C0_I3C_S_ECC_AGGR_RamIdTable[SDL_MCU_I3C0_I3C_S_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_I3C0_I3C_S_ECC_AGGR

SDL_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_UDMASS_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_NAVSS0_UDMASS_ECC_AGGR0

SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RamIdTable[SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR

SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS1_CORE1_ECC_AGGR

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR

SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_NAVSS0_MODSS_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_NAVSS0_MODSS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_MODSS_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_NAVSS0_MODSS_ECC_AGGR0

SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_CORE0_ECC_AGGR

SDL_PCIE0_ECC_AGGR_CORE_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE0_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE0_ECC_AGGR_CORE_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE0_ECC_AGGR_CORE_0

SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable[SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM

SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE0_ECC_AGGR_CORE_AXI_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE0_ECC_AGGR_CORE_AXI_0

SDL_I3C0_I3C_S_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_I3C0_I3C_S_ECC_AGGR_RamIdTable[SDL_I3C0_I3C_S_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_I3C0_I3C_S_ECC_AGGR

SDL_VPAC0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_VPAC0_ECC_AGGR_RamIdTable[SDL_VPAC0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_VPAC0_ECC_AGGR

SDL_NAVSS0_VIRTSS_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_NAVSS0_VIRTSS_ECC_AGGR0

SDL_MCU_I3C0_I3C_P_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_I3C0_I3C_P_ECC_AGGR_RamIdTable[SDL_MCU_I3C0_I3C_P_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_RAM_ID,
      SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_I3C0_I3C_P_ECC_AGGR

SDL_PCIE1_ECC_AGGR_CORE_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE1_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE1_ECC_AGGR_CORE_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE1_ECC_AGGR_CORE_0

SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS1_CORE0_ECC_AGGR

SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RamIdTable[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_RAM_ID,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_INJECT_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_RAM_ID,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_INJECT_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_ECC_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM

SDL_NAVSS0_NBSS_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_NAVSS0_NBSS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_NBSS_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_NAVSS0_NBSS_ECC_AGGR0

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM

SDL_IDOM1_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM1_ECC_AGGR0_RamIdTable[SDL_IDOM1_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM1_ECC_AGGR0

SDL_IDOM1_ECC_AGGR1_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM1_ECC_AGGR1_RamIdTable[SDL_IDOM1_ECC_AGGR1_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM1_ECC_AGGR1

SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_RamIdTable[SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_SENS_CTRL_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR

SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RamIdTable[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR

SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE1_ECC_AGGR_CORE_AXI_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE1_ECC_AGGR_CORE_AXI_0

SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable[SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable[SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID,
      SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_INJECT_TYPE,
      SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID,
      SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_INJECT_TYPE,
      SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR

SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RamIdTable[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_RAM_ID,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_INJECT_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_ECC_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_groupEntries },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_RAM_ID,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_RAM_ID,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_INJECT_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR

SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RamIdTable[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR

SDL_MCU_I3C1_I3C_S_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_I3C1_I3C_S_ECC_AGGR_RamIdTable[SDL_MCU_I3C1_I3C_S_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_I3C1_I3C_S_ECC_AGGR

SDL_MCU_I3C1_I3C_P_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_I3C1_I3C_P_ECC_AGGR_RamIdTable[SDL_MCU_I3C1_I3C_P_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_RAM_ID,
      SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_I3C1_I3C_P_ECC_AGGR

SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RamIdTable

const SDL_RAMIdEntry_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RamIdTable[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_NUM_RAMS]

static

Initial value:

=
{
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
      SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE

SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RamIdTable[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR

SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable[SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR

SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RamIdTable[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_NAVSS0_MODSS_ECC_AGGR0

SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RamIdTable

const SDL_RAMIdEntry_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RamIdTable[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_NUM_RAMS]

static

Initial value:

=
{
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_RAM_ID,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_INJECT_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_RAM_ID,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_INJECT_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_RAM_ID,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_INJECT_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_RAM_ID,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_INJECT_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_RAM_ID,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_INJECT_TYPE,
      SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY

SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RamIdTable

const SDL_RAMIdEntry_t SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RamIdTable[SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS]

static

Initial value:

=
{
    { SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_RAM_ID,
      SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_INJECT_TYPE,
      SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_ECC_TYPE,
      SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_PCIE3_ECC_AGGR_CORE_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE3_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE3_ECC_AGGR_CORE_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE3_ECC_AGGR_CORE_0

SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_RAM_ID,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR

SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RamIdTable[SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_RAM_ID,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_RAM_ID,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_RAM_ID,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_RAM_ID,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR

SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR

SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR

SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_RAM_ID,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR

SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM

SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable[SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID,
      SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_INJECT_TYPE,
      SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID,
      SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_INJECT_TYPE,
      SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR

SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE3_ECC_AGGR_CORE_AXI_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE3_ECC_AGGR_CORE_AXI_0

SDL_I3C0_I3C_P_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_I3C0_I3C_P_ECC_AGGR_RamIdTable[SDL_I3C0_I3C_P_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_RAM_ID,
      SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_INJECT_TYPE,
      SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_ECC_TYPE,
      SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_I3C0_I3C_P_ECC_AGGR

SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR

SDL_CBASS_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_CBASS_ECC_AGGR0_RamIdTable[SDL_CBASS_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CBASS_ECC_AGGR0

SDL_MAIN_RC_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_MAIN_RC_ECC_AGGR0_RamIdTable[SDL_MAIN_RC_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MAIN_RC_ECC_AGGR0

SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RamIdTable

const SDL_RAMIdEntry_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RamIdTable[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_NUM_RAMS]

static

Initial value:

=
{
    { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_RAM_ID,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_INJECT_TYPE,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_ECC_TYPE,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS

SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RamIdTable[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR

SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR

SDL_DMPAC0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_DMPAC0_ECC_AGGR_RamIdTable[SDL_DMPAC0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DMPAC0_ECC_AGGR

SDL_MAIN_HC_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_MAIN_HC_ECC_AGGR0_RamIdTable[SDL_MAIN_HC_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MAIN_HC_ECC_AGGR0

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RamIdTable[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_NUM_RAMS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_RAM_ID,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_ECC_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_MAX_NUM_CHECKERS,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_groupEntries },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_RAM_ID,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_ECC_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_MAX_NUM_CHECKERS,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_groupEntries },
    { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RamIdTable[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1

SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RamIdTable[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0

SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_VPAC0_LDC_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_VPAC0_LDC_ECC_AGGR_RamIdTable[SDL_VPAC0_LDC_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_VPAC0_LDC_ECC_AGGR

SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_CORE1_ECC_AGGR

SDL_NAVSS_VIRTSS_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_NAVSS_VIRTSS_ECC_AGGR0_RamIdTable[SDL_NAVSS_VIRTSS_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_NAVSS_VIRTSS_ECC_AGGR0

SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_R5FSS0_CORE1_ECC_AGGR

SDL_MCU_CBASS_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_CBASS_ECC_AGGR0_RamIdTable[SDL_MCU_CBASS_ECC_AGGR0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_CBASS_ECC_AGGR0

SDL_VPAC0_VISS_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_VPAC0_VISS_ECC_AGGR_RamIdTable[SDL_VPAC0_VISS_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_VPAC0_VISS_ECC_AGGR

SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_RamIdTable[SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
    { SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0_RAM_ID,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_EDC_CTRL_0_groupEntries },
    { SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_CTRL_BUSECC_RAM_ID,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_CTRL_BUSECC_INJECT_TYPE,
      SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR_CTRL_BUSECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR

SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable[SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR

SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RamIdTable[SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_ID,
      SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_INJECT_TYPE,
      SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR

SDL_ECC_aggrBaseAddressTable

SDL_ecc_aggrRegs* const SDL_ECC_aggrBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES]

static

This structure holds the base addresses for each memory subtype in MCU domain

---

SDL_ECC_aggrHighBaseAddressTable

uint64_t const SDL_ECC_aggrHighBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]

static

Initial value:

=
{
    (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_ECC_AGGR_VBUS_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_ECC_AGGR_CTL_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_ECC_AGGR_CFG_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BASE,
}

SDL_ECC_aggrHighBaseAddressTableTrans

SDL_ecc_aggrRegs* SDL_ECC_aggrHighBaseAddressTableTrans[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]

SDL_ECC_aggrTable

const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]

static