47 #ifndef INCLUDE_SDL_ECC_H_ 48 #define INCLUDE_SDL_ECC_H_ 53 #include "sdl_common.h" 54 #include <src/ip/sdl_ip_ecc.h> 156 #define SDL_ECC_MEMTYPE_MCU_R5F0_CORE (0u) 157 #define SDL_ECC_MEMTYPE_MCU_R5F1_CORE (1u) 158 #define SDL_ECC_MEMTYPE_MCU_ADC0 (2u) 159 #define SDL_ECC_MEMTYPE_MCU_ADC1 (3u) 160 #define SDL_ECC_MEMTYPE_MCU_CPSW0 (4u) //meta data information not available 161 #define SDL_ECC_MEMTYPE_MCU_FSS0_HPB0 (5u) //no memory information 162 #define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI0 (6u) //no memory information 163 #define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI1 (7u) //no memory information 165 #define SDL_ECC_MEMTYPE_MCU_MCAN0 (8u) 166 #define SDL_ECC_MEMTYPE_MCU_MCAN1 (9u) 167 #define SDL_ECC_MEMTYPE_MCU_MSRAM0 (10u) 168 #define SDL_ECC_MEMTYPE_MCU_NAVSS0 (11u) 170 #define SDL_ECC_MEMTYPE_MCU_PSRAM0 (12u)//meta data information not available 171 #define SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0 (13u) 173 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (14u) 174 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (15u) 175 #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (16u) 176 #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (17u) 177 #define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR (18u) 178 #define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR (19u) 179 #define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR (20u) 180 #define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR (21u) 181 #define SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR (22u) 182 #define SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR (23u) 183 #define SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR (24u) 184 #define SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR (25u) 185 #define SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR (26u) 186 #define SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR (27u) 188 #define SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR (28u) 189 #define SDL_PCIE0_ECC_AGGR_CORE_0 (29u) 190 #define SDL_PCIE0_ECC_AGGR_CORE_AXI_0 (30u) 191 #define SDL_PCIE1_ECC_AGGR_CORE_0 (31u) 192 #define SDL_PCIE1_ECC_AGGR_CORE_AXI_0 (32u) 193 #define SDL_PCIE2_ECC_AGGR_CORE_0 (33u) 194 #define SDL_PCIE2_ECC_AGGR_CORE_AXI_0 (34u) 195 #define SDL_PCIE3_ECC_AGGR_CORE_0 (35u) 196 #define SDL_PCIE3_ECC_AGGR_CORE_AXI_0 (36u) 198 #define SDL_I3C0_I3C_S_ECC_AGGR (37u) 199 #define SDL_I3C0_I3C_P_ECC_AGGR (38u) 200 #define SDL_MCU_I3C0_I3C_P_ECC_AGGR (39u) 201 #define SDL_MCU_I3C0_I3C_S_ECC_AGGR (40u) 202 #define SDL_MCU_I3C1_I3C_P_ECC_AGGR (41u) 203 #define SDL_MCU_I3C1_I3C_S_ECC_AGGR (42u) 204 #define SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR (43u) 205 #define SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR (44u) 207 #define SDL_CBASS_ECC_AGGR0 (45u) 208 #define SDL_MAIN_RC_ECC_AGGR0 (46u) 211 #define SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR (47u) 212 #define SDL_DMPAC0_ECC_AGGR (48u) 213 #define SDL_MAIN_HC_ECC_AGGR0 (49u) 214 #define SDL_VPAC0_ECC_AGGR (50u) 215 #define SDL_VPAC0_VISS_ECC_AGGR (51u) 216 #define SDL_VPAC0_LDC_ECC_AGGR (52u) 217 #define SDL_R5FSS0_CORE0_ECC_AGGR (53u) 218 #define SDL_R5FSS1_CORE0_ECC_AGGR (54u) 219 #define SDL_R5FSS0_CORE1_ECC_AGGR (55u) 220 #define SDL_R5FSS1_CORE1_ECC_AGGR (56u) 221 #define SDL_NAVSS_VIRTSS_ECC_AGGR0 (57u) 222 #define SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR (58u) // Base address not available 224 #define SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (59u) 225 #define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (60u) 227 #define SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR (61u) 228 #define SDL_MAIN_AC_ECC_AGGR0 (62u) 230 #define SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR (63u) 231 #define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM (64u) 232 #define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM (65u) 233 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (66u) 234 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (67u) 235 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM (68u) 236 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM (69u) 237 #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE (70u) 238 #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY (71u) 239 #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC (72u) 240 #define SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR (73u) 241 #define SDL_CSI_RX_IF0_ECC_AGGR_0 (74u) 242 #define SDL_CSI_RX_IF1_ECC_AGGR_0 (75u) 243 #define SDL_NAVSS0_MODSS_ECC_AGGR0 (76u) 244 #define SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR (77u) 245 #define SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR (78u) 246 #define SDL_NAVSS0_VIRTSS_ECC_AGGR0 (79u) 247 #define SDL_NAVSS0_NBSS_ECC_AGGR0 (80u) 248 #define SDL_IDOM1_ECC_AGGR0 (81u) 249 #define SDL_IDOM1_ECC_AGGR1 (82u) 250 #define SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR (83u) 251 #define SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR (84u) 252 #define SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR (85u) 253 #define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR (86u) 254 #define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE (87u) 255 #define SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR (88u) 256 #define SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS (89u) 257 #define SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0 (90u) 258 #define SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR (91u) 259 #define SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR (92u) 262 #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 (93u) 263 #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1 (94u) 264 #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2 (95u) 265 #define SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR (96u) 266 #define SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR (97u) 267 #define SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR (98u) 268 #define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_VBUS (99u) 269 #define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CTL (100u) 270 #define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CFG (101u) 271 #define SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR (102u) 273 #define SDL_ECC_MEMTYPE_MAX (SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR + 1U) 287 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID) 289 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID) 291 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID) 293 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID) 295 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID) 297 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID) 299 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID) 318 typedef struct SDL_ECC_InitConfig_s
331 typedef struct SDL_ECC_InjectErrorConfig_s
345 typedef struct SDL_ECC_ErrorInfo_s
422 uint32_t selfTestTimeOut);
548 uint64_t bitErrorOffset,
549 uint32_t bitErrorGroup);
SDL_ECC_AggregatorType
This enumerator defines the different ECC aggregator types
Definition: sdl_ecc.h:96
int32_t SDL_ECC_init(SDL_ECC_MemType eccMemType, const SDL_ECC_InitConfig_t *pECCInitConfig)
Initializes ECC module for ECC detection.
SDL_ESM_Inst
Defines the different ESM instance types
Definition: ip/sdl_esm.h:167
int32_t SDL_ECC_initMemory(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType)
Initializes Memory to be ready for ECC error detection. Assumes ECC is already enabled.
uint32_t SDL_Ecc_AggrEDCErrorSubType
This enumerator defines the types of possible EDC errors.
Definition: sdl_ip_ecc.h:187
Definition: sdl_ecc.h:119
Definition: sdl_ecc.h:113
int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc, SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType)
Retrieves the ECC error information for the specified ESM error. If it isn't an ECC error or the ECC ...
uint32_t bitErrorGroup
Definition: sdl_ecc.h:357
SDL_ECC_MemSubType memSubType
Definition: sdl_ecc.h:349
void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType, uint32_t errorSrc, uint32_t address, uint32_t ramId, uint64_t bitErrorOffset, uint32_t bitErrorGroup)
Application provided external callback function for ECC handling Called inside the reference function...
uint32_t chkGrp
Definition: sdl_ecc.h:337
This structure defines the inject error configuration
Definition: sdl_ecc.h:331
int32_t SDL_ECC_initEsm(const SDL_ESM_Inst esmInstType)
Initializes an module for usage with ECC module.
SDL_Ecc_AggrIntrSrc intrSrc
Definition: sdl_ecc.h:351
int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig)
Injects ECC error at specified location Assumes ECC is already enabled.
This structure contains the static register group for Ecc aggregator used by the SDL_ecc_aggrReadStat...
Definition: sdl_ip_ecc.h:348
uint32_t numRams
Definition: sdl_ecc.h:320
This structure defines the error status information
Definition: sdl_ecc.h:345
SDL_ECC_RamIdType
This enumerator defines the different ECC RAM ID types
Definition: sdl_ecc.h:135
uint32_t SDL_ECC_MemType
This enumerator indicate ECC memory type.
Definition: sdl_ecc.h:154
int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_ECC_ErrorInfo_t *pErrorInfo)
Retrieves the ECC error information for the specified memtype and interrupt source.
SDL_ECC_MemSubType * pMemSubTypeList
Definition: sdl_ecc.h:323
uint64_t bitErrorOffset
Definition: sdl_ecc.h:359
void SDL_ECC_registerVIMDEDHandler(SDL_ECC_VIMDEDVector_t VIMDEDHandler)
Register Handler for VIM DED ECC error.
This structure defines the elements of ECC Init configuration
Definition: sdl_ecc.h:318
int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc)
Acknowledge the ECC interrupt.
Definition: sdl_ecc.h:117
Definition: sdl_ecc.h:136
uint32_t flipBitMask
Definition: sdl_ecc.h:335
int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig, uint32_t selfTestTimeOut)
Runs self test by injecting and error and monitor response Assumes ECC is already enabled.
void(* SDL_ECC_VIMDEDVector_t)(void)
Definition: sdl_ecc.h:305
Header file contains enumerations, structure definitions and function declarations for SDL Error Sign...
uint32_t * pErrMem
Definition: sdl_ecc.h:333
uint32_t SDL_ECC_MemSubType
This enumerator indicate ECC memory Sub Type.
Definition: sdl_ecc.h:280
SDL_ECC_MemType eccMemType
Definition: sdl_ecc.h:347
int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents)
Clears N pending interrupts for the specified memtype, subtype and interrupt source.
Definition: sdl_ecc.h:127
Definition: sdl_ecc.h:111
uint32_t SDL_Ecc_AggrIntrSrc
This enumerator defines the types of possible ECC errors.
Definition: sdl_ip_ecc.h:106
Definition: sdl_ecc.h:125
int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType, SDL_ECC_staticRegs *pStaticRegs)
Gets the static registers for the specified ECC instance.
Definition: sdl_ecc.h:115
Definition: sdl_ecc.h:123
uint32_t bitErrCnt
Definition: sdl_ecc.h:353
Definition: sdl_ecc.h:121
Definition: sdl_ecc.h:138
void(* SDL_ECC_ErrorCallback_t)(uint32_t errorSrc, uint32_t address)
Definition: sdl_ecc.h:302
SDL_ECC_InjectErrorType
ECC Inject error types.
Definition: sdl_ecc.h:109
uint32_t injectBitErrCnt
Definition: sdl_ecc.h:355