PDK API Guide for J721E
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D-PHY configuration structure.
Data Fields | |
uint32_t | inst |
uint32_t | psmClkFreqDiv |
uint32_t | leftLaneBandSpeed |
uint32_t | rightLaneBandSpeed |
uint32_t | bandGapTimerVal |
uint32_t Csirx_DPhyCfg::inst |
CSIRX istance. See CSIRX_InstanceId for details
uint32_t Csirx_DPhyCfg::psmClkFreqDiv |
PMA state machine clock frequency divider control. Valid values: 1 to 255
uint32_t Csirx_DPhyCfg::leftLaneBandSpeed |
Data rates for left lane band control. See Csirx_LaneBandSpeed for details
uint32_t Csirx_DPhyCfg::rightLaneBandSpeed |
Data rates for left lane band control. See Csirx_LaneBandSpeed for details
uint32_t Csirx_DPhyCfg::bandGapTimerVal |
PMA state machine clock frequency divider control. Valid values: 0 to 255