Detailed Description

Holds CPSW control register contents.

Data Fields
Uint32	fifoLb

Uint32	vlanAware

Uint32	p0Enable

Uint32	p0PassPriTag

Uint32	p1PassPriTag

Uint32	p2PassPriTag

Uint32	p3PassPriTag

Uint32	p4PassPriTag

Uint32	p5PassPriTag

Uint32	p6PassPriTag

Uint32	p7PassPriTag

Uint32	p8PassPriTag

Uint32	p0TxCrcRemove

Uint32	p0RxPad

Uint32	p0RxPassCrcErr

Uint32	eeeEnable

Field Documentation

◆ fifoLb

Uint32 CSL_CPSW_CONTROL::fifoLb

FIFO loopback mode

◆ vlanAware

Uint32 CSL_CPSW_CONTROL::vlanAware

Vlan aware mode

◆ p0Enable

Uint32 CSL_CPSW_CONTROL::p0Enable

Port 0 Enable

◆ p0PassPriTag

Uint32 CSL_CPSW_CONTROL::p0PassPriTag

Port 0 Pass Priority Tagged

◆ p1PassPriTag

Uint32 CSL_CPSW_CONTROL::p1PassPriTag

Port 1 Pass Priority Tagged

◆ p2PassPriTag

Uint32 CSL_CPSW_CONTROL::p2PassPriTag

Port 2 Pass Priority Tagged

◆ p3PassPriTag

Uint32 CSL_CPSW_CONTROL::p3PassPriTag

Port 3 Pass Priority Tagged

◆ p4PassPriTag

Uint32 CSL_CPSW_CONTROL::p4PassPriTag

Port 4 Pass Priority Tagged

◆ p5PassPriTag

Uint32 CSL_CPSW_CONTROL::p5PassPriTag

Port 5 Pass Priority Tagged

◆ p6PassPriTag

Uint32 CSL_CPSW_CONTROL::p6PassPriTag

Port 6 Pass Priority Tagged

◆ p7PassPriTag

Uint32 CSL_CPSW_CONTROL::p7PassPriTag

Port 7 Pass Priority Tagged

◆ p8PassPriTag

Uint32 CSL_CPSW_CONTROL::p8PassPriTag

Port 8 Pass Priority Tagged

◆ p0TxCrcRemove

Uint32 CSL_CPSW_CONTROL::p0TxCrcRemove

Port 0 Transmit CRC remove

◆ p0RxPad

Uint32 CSL_CPSW_CONTROL::p0RxPad

Port 0 Receive Short Packet Pad 0 - short packets are dropped 1 - short packets are padded to 64-bytes (with pad and added CRC) if the CRC is not passed in. Short packets are dropped if the CRC is passed (in the Info0 word).

◆ p0RxPassCrcErr

Uint32 CSL_CPSW_CONTROL::p0RxPassCrcErr

Port 0 Pass Received CRC errors

◆ eeeEnable

Uint32 CSL_CPSW_CONTROL::eeeEnable

Energy Efficient Ethernet enable