CSL_CPGMAC_SL_FIFOSTATUS Struct Reference

Detailed Description

Holds the Enet_Pn_FIFO_Status register contents.

Data Fields
Uint32	estBufAct
Uint32	estAddErr
Uint32	estCntErr
Uint32	txExpressMacAllow
Uint32	txPriActive

Field Documentation

estBufAct

Uint32 CSL_CPGMAC_SL_FIFOSTATUS::estBufAct

EST RAM active buffer . Indicates the active 64-word fetch buffer when pn_est_onebuf is cleared to zero. Indicates the fetch ram address MSB when pn_est_onebuf set to one.

estAddErr

Uint32 CSL_CPGMAC_SL_FIFOSTATUS::estAddErr

EST Address Error Indicates that the fetch ram was read again after the previous maximum buffer address read (the previous fetch from the maximum address is reused).

estCntErr

Uint32 CSL_CPGMAC_SL_FIFOSTATUS::estCntErr

EST Fetch Count Error Indicates that insufficient clocks were programmed into the fetch count and that another fetch was commanded before the previous fetch finished.

txExpressMacAllow

Uint32 CSL_CPGMAC_SL_FIFOSTATUS::txExpressMacAllow

EST transmit mac allow Bus that indicates the actual priorities assigned to the express queue (and inversely the priorities assigned to the prempt queue). The pn_mac_prempt[7:0] field in the Enet_Pn_IET_Control register indicates which priorities should be assigned to the express/prempt queues. The switch between queues happens only when the priority is empty and the actual assignment is shown in this field.

txPriActive

Uint32 CSL_CPGMAC_SL_FIFOSTATUS::txPriActive

EST Transmit Priority Active Bus that indicates which priorities have packets (non-empty) at the time of the register read.