PDK API Guide for J721E
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DPHY Clock and Data Lane mode status
Data Fields | |
uint8_t | cl_StopState |
uint8_t | cl_ULPSActiveNot |
uint8_t | cl_RxULPSClkNot |
uint8_t | dlStopState [CSIRX_MAX_NUM_OF_STREAMS] |
uint8_t | dlULPSActiveNot [CSIRX_MAX_NUM_OF_STREAMS] |
uint8_t | dlRxULPSEsc [CSIRX_MAX_NUM_OF_STREAMS] |
uint8_t CSIRX_DphyStatus::cl_StopState |
DPHY Clock lane Stop State
uint8_t CSIRX_DphyStatus::cl_ULPSActiveNot |
DPHY Clock lane ULPSActiveNot
uint8_t CSIRX_DphyStatus::cl_RxULPSClkNot |
DPHY Clock lane RxULPSClkNot
uint8_t CSIRX_DphyStatus::dlStopState[CSIRX_MAX_NUM_OF_STREAMS] |
DPHY Data lane Stop State
uint8_t CSIRX_DphyStatus::dlULPSActiveNot[CSIRX_MAX_NUM_OF_STREAMS] |
DPHY Data lane ULPSActiveNot
uint8_t CSIRX_DphyStatus::dlRxULPSEsc[CSIRX_MAX_NUM_OF_STREAMS] |
DPHY Data lane ULPS Esc