PDK API Guide for J721E
CSIRX_DphyStatus Struct Reference

Detailed Description

DPHY Clock and Data Lane mode status

Data Fields

uint8_t cl_StopState
 
uint8_t cl_ULPSActiveNot
 
uint8_t cl_RxULPSClkNot
 
uint8_t dlStopState [CSIRX_MAX_NUM_OF_STREAMS]
 
uint8_t dlULPSActiveNot [CSIRX_MAX_NUM_OF_STREAMS]
 
uint8_t dlRxULPSEsc [CSIRX_MAX_NUM_OF_STREAMS]
 

Field Documentation

◆ cl_StopState

uint8_t CSIRX_DphyStatus::cl_StopState

DPHY Clock lane Stop State

◆ cl_ULPSActiveNot

uint8_t CSIRX_DphyStatus::cl_ULPSActiveNot

DPHY Clock lane ULPSActiveNot

◆ cl_RxULPSClkNot

uint8_t CSIRX_DphyStatus::cl_RxULPSClkNot

DPHY Clock lane RxULPSClkNot

◆ dlStopState

uint8_t CSIRX_DphyStatus::dlStopState[CSIRX_MAX_NUM_OF_STREAMS]

DPHY Data lane Stop State

◆ dlULPSActiveNot

uint8_t CSIRX_DphyStatus::dlULPSActiveNot[CSIRX_MAX_NUM_OF_STREAMS]

DPHY Data lane ULPSActiveNot

◆ dlRxULPSEsc

uint8_t CSIRX_DphyStatus::dlRxULPSEsc[CSIRX_MAX_NUM_OF_STREAMS]

DPHY Data lane ULPS Esc