sciclient_fmwMsgParams.h

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/*
 *  Copyright (C) 2018 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#ifndef SCICLIENT_FMWMSGPARAMS_H_
#define SCICLIENT_FMWMSGPARAMS_H_

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <stdint.h>
#include <ti/csl/soc.h>

#ifdef __cplusplus
extern "C" {
#endif

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

#define TISCI_PARAM_UNDEF                                        (0xFFFFFFFFU)

/* ABI Major revision - Major revision changes
*       indicate backward compatibility breakage */
#define SCICLIENT_FIRMWARE_ABI_MAJOR                     (3U)
/* ABI Minor revision - Minor revision changes
*       indicate backward compatibility is maintained,
*       however, new messages OR extensions to existing
*       messages might have been adde */
#define SCICLIENT_FIRMWARE_ABI_MINOR                     (1U)
/* @} */

#define SCICLIENT_CONTEXT_R5_NONSEC_0 (0U)

#define SCICLIENT_CONTEXT_R5_SEC_0 (1U)

#define SCICLIENT_CONTEXT_R5_NONSEC_1 (2U)

#define SCICLIENT_CONTEXT_R5_SEC_1 (3U)

#define SCICLIENT_CONTEXT_A72_SEC_0 (4U)

#define SCICLIENT_CONTEXT_A72_SEC_1 (5U)

#define SCICLIENT_CONTEXT_A72_NONSEC_0 (6U)

#define SCICLIENT_CONTEXT_A72_NONSEC_1 (7U)

#define SCICLIENT_CONTEXT_A72_NONSEC_2 (8U)

#define SCICLIENT_CONTEXT_C7X_SEC_0 (9U)

#define SCICLIENT_CONTEXT_C7X_NONSEC_0 (10U)

#define SCICLIENT_CONTEXT_C6X_0_SEC_0 (11U)

#define SCICLIENT_CONTEXT_C6X_0_NONSEC_0 (12U)

#define SCICLIENT_CONTEXT_C6X_1_SEC_0 (13U)

#define SCICLIENT_CONTEXT_C6X_1_NONSEC_0 (14U)

#define SCICLIENT_CONTEXT_GPU_NONSEC_0 (15U)

#define SCICLIENT_CONTEXT_MAIN_0_R5_NONSEC_0 (16U)

#define SCICLIENT_CONTEXT_MAIN_0_R5_SEC_0 (17U)

#define SCICLIENT_CONTEXT_MAIN_0_R5_NONSEC_1 (18U)

#define SCICLIENT_CONTEXT_MAIN_0_R5_SEC_1 (19U)

#ifdef SOC_J721E
#define SCICLIENT_CONTEXT_MAIN_1_R5_NONSEC_0 (20U)

#define SCICLIENT_CONTEXT_MAIN_1_R5_SEC_0 (21U)

#define SCICLIENT_CONTEXT_MAIN_1_R5_NONSEC_1 (22U)

#define SCICLIENT_CONTEXT_MAIN_1_R5_SEC_1 (23U)

#define SCICLIENT_CONTEXT_ICSSG_NONSEC_0 (24U)

#define SCICLIENT_CONTEXT_MAX_NUM                        (25U)
#else
#define SCICLIENT_CONTEXT_MAX_NUM                        (20U)
#endif
/* @} */

#define SCICLIENT_PROC_ID_A72SS0_CORE0 (0x20U)

#define SCICLIENT_PROC_ID_A72SS0_CORE1 (0x21U)

#define SCICLIENT_PROC_ID_C71SS0 (0x30U)

#define SCICLIENT_PROC_ID_C66SS0_CORE0 (0x03U)

#define SCICLIENT_PROC_ID_C66SS1_CORE0 (0x04U)

#define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x06U)

#define SCICLIENT_PROC_ID_R5FSS0_CORE1 (0x07U)

#define SCICLIENT_PROC_ID_R5FSS1_CORE0 (0x08U)

#define SCICLIENT_PROC_ID_R5FSS1_CORE1 (0x09U)

#define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0 (0x01U)

#define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE1 (0x02U)

#define SCICLIENT_SOC_NUM_PROCESSORS (0x0BU)
/* @} */

#define TISCI_MSG_VALUE_RM_NULL_RING_TYPE     (0xFFFFu)

#define TISCI_MSG_VALUE_RM_NULL_RING_INDEX    (0xFFFFFFFFu)

#define TISCI_MSG_VALUE_RM_NULL_RING_ADDR     (0xFFFFFFFFu)

#define TISCI_MSG_VALUE_RM_NULL_RING_COUNT    (0xFFFFFFFFu)

#define TISCI_MSG_VALUE_RM_NULL_RING_MODE     (0xFFu)

#define TISCI_MSG_VALUE_RM_NULL_RING_SIZE     (0xFFu)

#define TISCI_MSG_VALUE_RM_NULL_ORDER_ID      (0xFFu)

#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE                  (0xFFu)

#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX                 (0xFFFFFFFFu)

#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_devices.h>
/* @} */

#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_clocks.h>
/* @} */

#define TISCI_ISC_CC_ID                (160U)

#define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START        (0U)
#define TISCI_RINGACC0_MON_IRQ_SRC_IDX_START        (1024U)
#define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START       (2048U)
#define TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START       (0U)
#define TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START      (512U)
#define TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START       (1024U)
#define TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START      (1280U)
#define TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START (1536U)
/* @} */

#define SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U)
#define SCICLIENT_C7X_SECURE_INTERRUPT_NUM     (10U)

#define SCICLIENT_DEV_MCU_R5FSS0_CORE0  (TISCI_DEV_MCU_R5FSS0_CORE0)
#define SCICLIENT_DEV_MCU_R5FSS0_CORE1  (TISCI_DEV_MCU_R5FSS0_CORE1)
/* @} */

#define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID  \
    (SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0)
#define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID  \
    (SCICLIENT_PROC_ID_MCU_R5FSS0_CORE1)
/* @} */

#define SCICLIENT_ALLOWED_BOARDCFG_BASE_START (CSL_MCU_MSRAM_1MB0_RAM_BASE)

#define SCICLIENT_ALLOWED_BOARDCFG_BASE_END   (CSL_MCU_MSRAM_1MB0_RAM_BASE + CSL_MCU_MSRAM_1MB0_RAM_SIZE)

/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */

/* None */

#ifdef __cplusplus
}
#endif

#endif /* #ifndef SCICLIENT_FMWMSGPARAMS_H_ */