Introduction

This is IPC documentation specific to J7 SoC

Files
file	ipc_soc.h
	IPC Low Level Driver J7 SOC specific file.

Macros
#define	IPC_VRING_BUFFER_SIZE (0x1C00000U)
	VRing Buffer Size required for all core combinations. More...

#define	SUPPORT_C66X_BIT0

#define	IPC_MPU1_0 (0U)
	Core definitions. More...

#define	IPC_MCU1_0 (1U)

#define	IPC_MCU1_1 (2U)

#define	IPC_MCU2_0 (3U)

#define	IPC_MCU2_1 (4U)

#define	IPC_MAILBOX_CLUSTER_CNT (12U)

#define	IPC_MAILBOX_USER_CNT (4U)

#define	MAIN_NAVSS_MAILBOX_INPUTINTR_MAX (440U)

#define	MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX (512U)

#define	NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET (182U)

#define	NAVSS512_MCU1R5F0_INPUT_MAILBOX_OFFSET (400U)

#define	NAVSS512_MCU1R5F1_INPUT_MAILBOX_OFFSET (404U)

#define	NAVSS512_MCU2R5F0_INPUT_MAILBOX_OFFSET (216U)

#define	NAVSS512_MCU2R5F1_INPUT_MAILBOX_OFFSET (248U)

#define	NAVSS512_MCU3R5F0_INPUT_MAILBOX_OFFSET (280U)

#define	NAVSS512_MCU3R5F1_INPUT_MAILBOX_OFFSET (312U)

#define	NAVSS512_C66X1_INPUT_MAILBOX_OFFSET (344U) /* C66x_intrRouter_0 : 96 */

#define	NAVSS512_C66X2_INPUT_MAILBOX_OFFSET (376U) /* C66x_intrRouter_1 : 96 */

#define	NAVSS512_C7X1_INPUT_MAILBOX_OFFSET (188U)

#define	IPC_MCU_NAVSS0_INTR0_CFG_BASE (CSL_NAVSS_MAIN_INTR_ROUTER_CFG_REGS_0_BASE)

#define	IPC_C66X_RAT_BASE (0x07ff0030U)

#define	IPC_C66X_INTR_VA_BASE (0x18000000U)

#define	IPC_C66X_1_INTR_PA_BASE (CSL_C66SS0_INTROUTER0_INTR_ROUTER_CFG_BASE)

#define	IPC_C66X_2_INTR_PA_BASE (CSL_C66SS1_INTROUTER0_INTR_ROUTER_CFG_BASE)

#define	C66X1_MBINTR_INPUT_BASE (74U)

#define	C66X1_MBINTR_OFFSET (84U)

#define	C66X1_MBINTR_OUTPUT_BASE (96U)

#define	C66X2_MBINTR_INPUT_BASE (74U)

#define	C66X2_MBINTR_OUTPUT_BASE (96U)

#define	C66X2_MBINTR_OFFSET (84U)

#define	C7X_CLEC_BASE_ADDR (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE)

#define	IPC_C7X_COMPUTE_CLUSTER_OFFSET (CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_128)

#define	C7X1_CLEC_BASE_GR2_NAVSS (1664U)

#define	C7X1_MBINTR_OFFSET (2U)

Macro Definition Documentation

◆ IPC_VRING_BUFFER_SIZE

#define IPC_VRING_BUFFER_SIZE (0x1C00000U)

VRing Buffer Size required for all core combinations.

◆ SUPPORT_C66X_BIT0

#define SUPPORT_C66X_BIT0

◆ IPC_MPU1_0

#define IPC_MPU1_0 (0U)

Core definitions.

ARM A72 - VM0

◆ IPC_MCU1_0

#define IPC_MCU1_0 (1U)

ARM MCU R5F - core0

◆ IPC_MCU1_1

#define IPC_MCU1_1 (2U)

ARM MCU R5F - core1

◆ IPC_MCU2_0

#define IPC_MCU2_0 (3U)

ARM Main R5F - core0

◆ IPC_MCU2_1

#define IPC_MCU2_1 (4U)

ARM Main R5F - core1

◆ IPC_MAILBOX_CLUSTER_CNT

#define IPC_MAILBOX_CLUSTER_CNT (12U)

◆ IPC_MAILBOX_USER_CNT

#define IPC_MAILBOX_USER_CNT (4U)

◆ MAIN_NAVSS_MAILBOX_INPUTINTR_MAX

#define MAIN_NAVSS_MAILBOX_INPUTINTR_MAX (440U)

◆ MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX

#define MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX (512U)

◆ NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET

#define NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET (182U)

◆ NAVSS512_MCU1R5F0_INPUT_MAILBOX_OFFSET

#define NAVSS512_MCU1R5F0_INPUT_MAILBOX_OFFSET (400U)

◆ NAVSS512_MCU1R5F1_INPUT_MAILBOX_OFFSET

#define NAVSS512_MCU1R5F1_INPUT_MAILBOX_OFFSET (404U)

◆ NAVSS512_MCU2R5F0_INPUT_MAILBOX_OFFSET

#define NAVSS512_MCU2R5F0_INPUT_MAILBOX_OFFSET (216U)

◆ NAVSS512_MCU2R5F1_INPUT_MAILBOX_OFFSET

#define NAVSS512_MCU2R5F1_INPUT_MAILBOX_OFFSET (248U)

◆ NAVSS512_MCU3R5F0_INPUT_MAILBOX_OFFSET

#define NAVSS512_MCU3R5F0_INPUT_MAILBOX_OFFSET (280U)

◆ NAVSS512_MCU3R5F1_INPUT_MAILBOX_OFFSET

#define NAVSS512_MCU3R5F1_INPUT_MAILBOX_OFFSET (312U)

◆ NAVSS512_C66X1_INPUT_MAILBOX_OFFSET

#define NAVSS512_C66X1_INPUT_MAILBOX_OFFSET (344U) /* C66x_intrRouter_0 : 96 */

◆ NAVSS512_C66X2_INPUT_MAILBOX_OFFSET

#define NAVSS512_C66X2_INPUT_MAILBOX_OFFSET (376U) /* C66x_intrRouter_1 : 96 */

◆ NAVSS512_C7X1_INPUT_MAILBOX_OFFSET

#define NAVSS512_C7X1_INPUT_MAILBOX_OFFSET (188U)

◆ IPC_MCU_NAVSS0_INTR0_CFG_BASE

#define IPC_MCU_NAVSS0_INTR0_CFG_BASE (CSL_NAVSS_MAIN_INTR_ROUTER_CFG_REGS_0_BASE)

◆ IPC_C66X_RAT_BASE

#define IPC_C66X_RAT_BASE (0x07ff0030U)

◆ IPC_C66X_INTR_VA_BASE

#define IPC_C66X_INTR_VA_BASE (0x18000000U)

◆ IPC_C66X_1_INTR_PA_BASE

#define IPC_C66X_1_INTR_PA_BASE (CSL_C66SS0_INTROUTER0_INTR_ROUTER_CFG_BASE)

◆ IPC_C66X_2_INTR_PA_BASE

#define IPC_C66X_2_INTR_PA_BASE (CSL_C66SS1_INTROUTER0_INTR_ROUTER_CFG_BASE)

◆ C66X1_MBINTR_INPUT_BASE

#define C66X1_MBINTR_INPUT_BASE (74U)

◆ C66X1_MBINTR_OFFSET

#define C66X1_MBINTR_OFFSET (84U)

◆ C66X1_MBINTR_OUTPUT_BASE

#define C66X1_MBINTR_OUTPUT_BASE (96U)

◆ C66X2_MBINTR_INPUT_BASE

#define C66X2_MBINTR_INPUT_BASE (74U)

◆ C66X2_MBINTR_OUTPUT_BASE

#define C66X2_MBINTR_OUTPUT_BASE (96U)

◆ C66X2_MBINTR_OFFSET

#define C66X2_MBINTR_OFFSET (84U)

◆ C7X_CLEC_BASE_ADDR

#define C7X_CLEC_BASE_ADDR (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE)

◆ IPC_C7X_COMPUTE_CLUSTER_OFFSET

#define IPC_C7X_COMPUTE_CLUSTER_OFFSET (CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_NAVSS0_INTR_ROUTER_0_OUTL_INTR_128)

◆ C7X1_CLEC_BASE_GR2_NAVSS

#define C7X1_CLEC_BASE_GR2_NAVSS (1664U)

◆ C7X1_MBINTR_OFFSET

#define C7X1_MBINTR_OFFSET (2U)