Introduction

Macros
#define	CSL_DRU_MAX_CH (512U)
	Maximum number of channels supported by DRU. This is just the maximum registers supported for programming. The actual channel supported is given by CSL_DRU_NUM_CH macro. More...

#define	CSL_DRU_NUM_CH (64U)
	Number of channels supported by the DRU. More...

#define	CSL_DRU_MAX_QUEUE (8U)
	Maximum number of queues supported by DRU. This is just the maximum registers supported for programming. The actual channel supported is given by CSL_DRU_NUM_QUEUE macro. More...

#define	CSL_DRU_NUM_QUEUE (5U)
	Number of queues supported by the DRU. More...

#define	CSL_DRU_MAX_CORE (4U)
	Maximum number of core submission set supported by the DRU. This is just the maximum registers supported for programming. The actual channel supported is given by CSL_DRU_NUM_CORE macro. More...

#define	CSL_DRU_NUM_CORE (3U)
	Number of core submission set supported by the DRU. More...

DRU Owner - Direct TR submission or UDMA-C TR submission
DRU owner.
#define	CSL_DRU_OWNER_DIRECT_TR ((uint64_t) 0x0000U)
	Direct TR - SUBMISSION registers must be written to submit TR. More...

#define	CSL_DRU_OWNER_UDMAC_TR ((uint64_t) 0x0001U)
	UDMA-C TR - TR will be received through PSIL. More...

DRU Queue ID
DRU queue ID. 0th queue is a priority queue. All others are round robin queues.
#define	CSL_DRU_QUEUE_ID_0 ((uint32_t) 0x0000U)

#define	CSL_DRU_QUEUE_ID_1 ((uint32_t) 0x0001U)

#define	CSL_DRU_QUEUE_ID_2 ((uint32_t) 0x0002U)

#define	CSL_DRU_QUEUE_ID_3 ((uint32_t) 0x0003U)

#define	CSL_DRU_QUEUE_ID_4 ((uint32_t) 0x0004U)

#define	CSL_DRU_QUEUE_ID_5 ((uint32_t) 0x0005U)

#define	CSL_DRU_QUEUE_ID_6 ((uint32_t) 0x0006U)

#define	CSL_DRU_QUEUE_ID_7 ((uint32_t) 0x0007U)

DRU Core ID
DRU core ID used to submit non-atomic TR submission. Note: There are only three core ID set present in the AM65xx and J721E SOC.
#define	CSL_DRU_CORE_ID_0 ((uint32_t) 0x0000U)

#define	CSL_DRU_CORE_ID_1 ((uint32_t) 0x0001U)

#define	CSL_DRU_CORE_ID_2 ((uint32_t) 0x0002U)

#define	CSL_DRU_CORE_ID_3 ((uint32_t) 0x0003U)

Macro Definition Documentation

◆ CSL_DRU_MAX_CH

#define CSL_DRU_MAX_CH (512U)

Maximum number of channels supported by DRU. This is just the maximum registers supported for programming. The actual channel supported is given by CSL_DRU_NUM_CH macro.

◆ CSL_DRU_NUM_CH

#define CSL_DRU_NUM_CH (64U)

Number of channels supported by the DRU.

◆ CSL_DRU_MAX_QUEUE

#define CSL_DRU_MAX_QUEUE (8U)

Maximum number of queues supported by DRU. This is just the maximum registers supported for programming. The actual channel supported is given by CSL_DRU_NUM_QUEUE macro.

◆ CSL_DRU_NUM_QUEUE

#define CSL_DRU_NUM_QUEUE (5U)

Number of queues supported by the DRU.

◆ CSL_DRU_MAX_CORE

#define CSL_DRU_MAX_CORE (4U)

Maximum number of core submission set supported by the DRU. This is just the maximum registers supported for programming. The actual channel supported is given by CSL_DRU_NUM_CORE macro.

◆ CSL_DRU_NUM_CORE

#define CSL_DRU_NUM_CORE (3U)

Number of core submission set supported by the DRU.

◆ CSL_DRU_OWNER_DIRECT_TR

#define CSL_DRU_OWNER_DIRECT_TR ((uint64_t) 0x0000U)

Direct TR - SUBMISSION registers must be written to submit TR.

◆ CSL_DRU_OWNER_UDMAC_TR

#define CSL_DRU_OWNER_UDMAC_TR ((uint64_t) 0x0001U)

UDMA-C TR - TR will be received through PSIL.

◆ CSL_DRU_QUEUE_ID_0

#define CSL_DRU_QUEUE_ID_0 ((uint32_t) 0x0000U)

◆ CSL_DRU_QUEUE_ID_1

#define CSL_DRU_QUEUE_ID_1 ((uint32_t) 0x0001U)

◆ CSL_DRU_QUEUE_ID_2

#define CSL_DRU_QUEUE_ID_2 ((uint32_t) 0x0002U)

◆ CSL_DRU_QUEUE_ID_3

#define CSL_DRU_QUEUE_ID_3 ((uint32_t) 0x0003U)

◆ CSL_DRU_QUEUE_ID_4

#define CSL_DRU_QUEUE_ID_4 ((uint32_t) 0x0004U)

◆ CSL_DRU_QUEUE_ID_5

#define CSL_DRU_QUEUE_ID_5 ((uint32_t) 0x0005U)

◆ CSL_DRU_QUEUE_ID_6

#define CSL_DRU_QUEUE_ID_6 ((uint32_t) 0x0006U)

◆ CSL_DRU_QUEUE_ID_7

#define CSL_DRU_QUEUE_ID_7 ((uint32_t) 0x0007U)

◆ CSL_DRU_CORE_ID_0

#define CSL_DRU_CORE_ID_0 ((uint32_t) 0x0000U)

◆ CSL_DRU_CORE_ID_1

#define CSL_DRU_CORE_ID_1 ((uint32_t) 0x0001U)

◆ CSL_DRU_CORE_ID_2

#define CSL_DRU_CORE_ID_2 ((uint32_t) 0x0002U)

◆ CSL_DRU_CORE_ID_3

#define CSL_DRU_CORE_ID_3 ((uint32_t) 0x0003U)