sdl_ecc.h

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/*
 * SDL ECC
 *
 * Software Diagnostics Library module for ECC
 *
 *  Copyright (c) Texas Instruments Incorporated 2018-2021
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#ifndef INCLUDE_SDL_ECC_H_
#define INCLUDE_SDL_ECC_H_

#include <stdint.h>
#include <stdbool.h>

#include "sdl_common.h"
#include <src/ip/sdl_ip_ecc.h>
#include <src/ip/sdl_esm.h>

#ifdef __cplusplus
extern "C" {
#endif

typedef enum {
    SDL_ECC_AGGR_TYPE_INJECT_ONLY = 1,
    SDL_ECC_AGGR_TYPE_FULL_FUNCTION = 2,
} SDL_ECC_AggregatorType;


typedef enum {
    SDL_INJECT_ECC_NO_ERROR = 0,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE = 1,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE = 2,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE = 3,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE = 4,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT = 5,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT = 6,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT = 7,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT = 8,
} SDL_ECC_InjectErrorType;


typedef enum {
    SDL_ECC_RAM_ID_TYPE_WRAPPER = 0,
    SDL_ECC_RAM_ID_TYPE_INTERCONNECT = 1,
} SDL_ECC_RamIdType;

/* @} */

typedef uint32_t SDL_ECC_MemType;


#define SDL_ECC_MEMTYPE_MCU_R5F0_CORE (0u)

#define SDL_ECC_MEMTYPE_MCU_R5F1_CORE (1u)

#define SDL_ECC_MEMTYPE_MCU_ADC0 (2u)

#define SDL_ECC_MEMTYPE_MCU_ADC1 (3u)

#define SDL_ECC_MEMTYPE_MCU_CPSW0 (4u)

#define SDL_ECC_MEMTYPE_MCU_FSS0_HPB0 (5u)

#define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI0 (6u)

#define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI1 (7u)

#define SDL_ECC_MEMTYPE_MCU_MCAN0 (8u)

#define SDL_ECC_MEMTYPE_MCU_MCAN1 (9u)

#define SDL_ECC_MEMTYPE_MCU_MSRAM0 (10u)

#define SDL_ECC_MEMTYPE_MCU_NAVSS0 (11u)

#define SDL_ECC_MEMTYPE_MCU_PDMA0 (12u)

#define SDL_ECC_MEMTYPE_MCU_PDMA1 (13u)

#define SDL_ECC_MEMTYPE_MCU_PSRAM0 (14u)

#define SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0 (15u)


/* These aggregators require using RAT to map into memory space */

#define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 (16u)

#define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1 (17u)

#define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2 (18u)

#define SDL_ECC_MEMTYPE_MAIN_A72_AGGR0 (19u)

#define SDL_ECC_MEMTYPE_MAX (SDL_ECC_MEMTYPE_MAIN_A72_AGGR0 + 1U)

typedef uint32_t SDL_ECC_MemSubType;

/* The following are the memory sub type for Memory type
   SDL_ECC_MEMTYPE_MCU_R5F0_CORE & SDL_ECC_MEMTYPE_MCU_R5F1_CORE */

#define SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM0_VECTOR_ID (0U)

#define SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM1_VECTOR_ID (1U)

#define SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM2_VECTOR_ID (2U)

#define SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM3_VECTOR_ID (3U)

#define SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK0_VECTOR_ID (4U)

#define SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK1_VECTOR_ID (5U)

#define SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK2_VECTOR_ID (6U)

#define SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK3_VECTOR_ID (7U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM0_VECTOR_ID (8U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM1_VECTOR_ID (9U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM2_VECTOR_ID (10U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM3_VECTOR_ID (11U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DDIRTY_RAM_VECTOR_ID (12U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM0_VECTOR_ID (13U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM1_VECTOR_ID (14U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM2_VECTOR_ID (15U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM3_VECTOR_ID (16U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM4_VECTOR_ID (17U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM5_VECTOR_ID (18U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM6_VECTOR_ID (19U)

#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM7_VECTOR_ID (20U)

#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (21U)

#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (22U)

#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (23U)

#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (24U)

#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (25U)

#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (26U)

#define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (27U)

#define SDL_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID (28U)

#define SDL_ECC_R5F_MEM_SUBTYPE_AXI2VBUSM_MEM_MST_WRITE_EDC_VECTOR_ID (29U)

#define SDL_ECC_R5F_MEM_SUBTYPE_AXI2VBUSM_MEM_MST_READ_EDC_VECTOR_ID (30U)

#define SDL_ECC_R5F_MEM_SUBTYPE_AXI2VBUSM_PERIPH_MST_WRITE_EDC_VECTOR_ID (31U)

#define SDL_ECC_R5F_MEM_SUBTYPE_AXI2VBUSM_PERIPH_MST_READ_EDC_VECTOR_ID (32U)

#define SDL_ECC_R5F_MEM_SUBTYPE_AHB2VBUSP_EDC_VECTOR_ID (33U)

#define SDL_ECC_R5F_MEM_SUBTYPE_SCRP_EDC_VECTOR_ID (34U)

#define SDL_ECC_R5F_MEM_SUBTYPE_ECC_AGGR_EDC_ID (35U)

#define SDL_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE  (20) /* SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID */

#define SDL_ECC_MAIN_MSMC_CACHE_TAG_MEM_INTERCONN_SUBTYPE  (85) /*SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_RAM_ID */

#define SDL_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE  (100) /* SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID */

#define SDL_ECC_MAIN_MSMC_MEM_CLEC_EDC_CTRL_BUSECC_SUBTYPE  (107)/* SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_RAM_ID */

/* The following are the memory sub type for Memory type
   SDL_ECC_MEMTYPE_MCU_CBASS */

#define SDL_ECC_MCU_CBASS_MEM_SUBTYPE_WR_RAMECC_ID (0U)

#define SDL_ECC_MCU_CBASS_MEM_SUBTYPE_RD_RAMECC_ID (1U)

#define SDL_ECC_MCU_CBASS_MEM_SUBTYPE_EDC_CTRL_ID (2U)

typedef void (*SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address);

typedef void (*SDL_ECC_VIMDEDVector_t) (void);

/* @} */

typedef struct SDL_ECC_InitConfig_s
{
    uint32_t numRams;
    SDL_ECC_MemSubType *pMemSubTypeList;
} SDL_ECC_InitConfig_t;

typedef struct SDL_ECC_InjectErrorConfig_s
{
    uint32_t *pErrMem;
    uint32_t flipBitMask;
    uint32_t chkGrp;
}  SDL_ECC_InjectErrorConfig_t;

typedef struct SDL_ECC_ErrorInfo_s
{
    SDL_ECC_MemType eccMemType;
    SDL_ECC_MemSubType memSubType;
    SDL_Ecc_AggrIntrSrc intrSrc;
    uint32_t bitErrCnt;
    uint32_t injectBitErrCnt;
    uint64_t bitErrorOffset;
    uint32_t bitErrorGroup;
} SDL_ECC_ErrorInfo_t;

/* @} */

int32_t SDL_ECC_initEsm (const SDL_ESM_Inst esmInstType);

int32_t SDL_ECC_init (SDL_ECC_MemType eccMemType,
                        const SDL_ECC_InitConfig_t *pECCInitConfig);

int32_t SDL_ECC_initMemory (SDL_ECC_MemType eccMemType,
                               SDL_ECC_MemSubType memSubType);

int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType,
                            SDL_ECC_MemSubType memSubType,
                            SDL_ECC_InjectErrorType errorType,
                            const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig,
                            uint32_t selfTestTimeOut);

int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType,
                               SDL_ECC_MemSubType memSubType,
                               SDL_ECC_InjectErrorType errorType,
                               const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig);

int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType,
                                   SDL_ECC_staticRegs *pStaticRegs);

int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType,
                                SDL_Ecc_AggrIntrSrc intrSrc,
                                SDL_ECC_ErrorInfo_t *pErrorInfo);

int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType,
                        SDL_Ecc_AggrIntrSrc intrSrc);

int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc,
                                SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType);

int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType,
                                  SDL_Ecc_AggrIntrSrc intrSrc,
                                  SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents);

void SDL_ECC_registerVIMDEDHandler(SDL_ECC_VIMDEDVector_t VIMDEDHandler);

void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType,
                                         uint32_t errorSrc,
                                         uint32_t address,
                                         uint32_t ramId,
                                         uint64_t bitErrorOffset,
                                         uint32_t bitErrorGroup);

/* @} */

#ifdef __cplusplus
}
#endif  /* extern "C" */

#endif /* INCLUDE_SDL_ECC_H_ */