PDK API Guide for J721E
csitx_soc.h
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1 /*
2  * Copyright (c) Texas Instruments Incorporated 2020
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * Redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer.
11  *
12  * Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the
15  * distribution.
16  *
17  * Neither the name of Texas Instruments Incorporated nor the names of
18  * its contributors may be used to endorse or promote products derived
19  * from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
48 #ifndef CSITX_SOC_H_
49 #define CSITX_SOC_H_
50 
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
54 
55 /* None */
56 
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60 
61 /* ========================================================================== */
62 /* Macros & Typedefs */
63 /* ========================================================================== */
72 #define CSITX_INSTANCE_ID_0 ((uint32_t) 0x0U)
73 
74 #define CSITX_INSTANCE_ID_MAX ((uint32_t)CSITX_INSTANCE_ID_0 + 1U)
75 /* @} */
76 
86 #define CSITX_NUM_STRMS_TX ((uint32_t) 1U)
87 
89 #define CSITX_NUM_STRMS_COLORBAR ((uint32_t) 1U)
90 
91 #define CSITX_NUM_STRMS_LPBK ((uint32_t) 2U)
92 
93 #define CSITX_NUM_CH_TX ((uint32_t) 32U)
94 
95 #define CSITX_NUM_CH_LPBK ((uint32_t) 1U)
96 
97 #define CSITX_NUM_CH_TX_MAX ((uint32_t) (CSITX_NUM_CH_TX *\
98  CSITX_INSTANCE_ID_MAX))
99 
100 #define CSITX_NUM_CH_COLORBAR_MAX ((uint32_t) 1U)
101 
105 #define CSITX_NUM_CH_LPBK_MAX ((uint32_t) (CSITX_NUM_CH_LPBK * \
106  CSITX_NUM_STRMS_LPBK))
107 
110 #define CSITX_NUM_CH_MAX ((uint32_t) (CSITX_NUM_CH_TX +\
111  CSITX_NUM_CH_COLORBAR_MAX +\
112  CSITX_NUM_CH_LPBK_MAX))
113 
115 #define CSITX_TX_DATA_LANES_MAX ((uint32_t)4U)
116 
118 #define CSITX_TX_CLK_LANES_MAX ((uint32_t)1U)
119 
120 #define CSITX_TX_VC_CFG_MAX ((uint32_t)16U)
121 
122 #define CSITX_TX_DT_CFG_MAX ((uint32_t)16U)
123 
124 #define CSITX_TX_STRM_NUM_MAX ((uint32_t)4U)
125 
127 #define CSITX_TX_STRM_FIFO_FILL_LVL ((uint32_t)960U)
128 
129 #define CSITX_NUM_STRMS_TX_ID ((uint32_t) 0U)
130 
131 #define CSITX_NUM_STRMS_TX_COLORBAR ((uint32_t) 1U)
132 
133 #define CSITX_NUM_STRMS_TX_RETRANS_0 ((uint32_t) 2U)
134 
135 #define CSITX_NUM_STRMS_TX_RETRANS_1 ((uint32_t) 3U)
136 /* @} */
137 
146 #define CSITX_LANE_BAND_SPEED_80_TO_100_MBPS ((uint32_t) 0x00U)
147 
148 #define CSITX_LANE_BAND_SPEED_100_TO_120_MBPS ((uint32_t) 0x01U)
149 
150 #define CSITX_LANE_BAND_SPEED_120_TO_160_MBPS ((uint32_t) 0x02U)
151 
152 #define CSITX_LANE_BAND_SPEED_160_TO_200_MBPS ((uint32_t) 0x03U)
153 
154 #define CSITX_LANE_BAND_SPEED_200_TO_240_MBPS ((uint32_t) 0x04U)
155 
156 #define CSITX_LANE_BAND_SPEED_240_TO_320_MBPS ((uint32_t) 0x05U)
157 
158 #define CSITX_LANE_BAND_SPEED_320_TO_390_MBPS ((uint32_t) 0x06U)
159 
160 #define CSITX_LANE_BAND_SPEED_390_TO_450_MBPS ((uint32_t) 0x07U)
161 
162 #define CSITX_LANE_BAND_SPEED_450_TO_510_MBPS ((uint32_t) 0x08U)
163 
164 #define CSITX_LANE_BAND_SPEED_510_TO_560_MBPS ((uint32_t) 0x09U)
165 
166 #define CSITX_LANE_BAND_SPEED_560_TO_640_MBPS ((uint32_t) 0x0AU)
167 
168 #define CSITX_LANE_BAND_SPEED_640_TO_690_MBPS ((uint32_t) 0x0BU)
169 
170 #define CSITX_LANE_BAND_SPEED_690_TO_770_MBPS ((uint32_t) 0x0CU)
171 
172 #define CSITX_LANE_BAND_SPEED_770_TO_870_MBPS ((uint32_t) 0x0DU)
173 
174 #define CSITX_LANE_BAND_SPEED_870_TO_950_MBPS ((uint32_t) 0x0EU)
175 
176 #define CSITX_LANE_BAND_SPEED_950_TO_1000_MBPS ((uint32_t) 0x0FU)
177 
178 #define CSITX_LANE_BAND_SPEED_1000_TO_1200_MBPS ((uint32_t) 0x10U)
179 
180 #define CSITX_LANE_BAND_SPEED_1200_TO_1400_MBPS ((uint32_t) 0x11U)
181 
182 #define CSITX_LANE_BAND_SPEED_1400_TO_1600_MBPS ((uint32_t) 0x12U)
183 
184 #define CSITX_LANE_BAND_SPEED_1600_TO_1800_MBPS ((uint32_t) 0x13U)
185 
186 #define CSITX_LANE_BAND_SPEED_1800_TO_2000_MBPS ((uint32_t) 0x14U)
187 
188 #define CSITX_LANE_BAND_SPEED_2000_TO_2200_MBPS ((uint32_t) 0x15U)
189 
190 #define CSITX_LANE_BAND_SPEED_2200_TO_2500_MBPS ((uint32_t) 0x16U)
191 
192 #define CSITX_LANE_BAND_SPEED_RESERVED ((uint32_t) 0x17U)
193 /* @} */
194 
203 #define CSITX_CLK_MODE_CONTINUOUS ((uint32_t) 0x0U)
204 
205 #define CSITX_CLK_MODE_NON_CONTINUOUS ((uint32_t) 0x1U)
206 /* @} */
207 
216 #define CSITX_DPHY_MODE_ULP ((uint32_t) 0x0U)
217 
218 #define CSITX_DPHY_MODE_HIGH_SPEED ((uint32_t) 0x1U)
219 
220 #define CSITX_DPHY_MODE_LOW_POWER ((uint32_t) 0x2U)
221 /* @} */
222 
224 #define CSITX_NUM_STREAM (1U)
225 
233 #if defined (BUILD_MCU2_0) || defined (BUILD_MCU2_1)
234 
235 #define CSITX_CORE_INTR_NUM_MOD_0_TX_INTR (267U)
236 
237 #define CSITX_CORE_INTR_NUM_MOD_0_LVL_INTR (268U)
238 #endif
239 #if defined (BUILD_MPU1_0)
240 
241 #define CSITX_CORE_INTR_NUM_MOD_0_TX_INTR (180U)
242 
243 #define CSITX_CORE_INTR_NUM_MOD_0_LVL_INTR (181U)
244 #endif
245 /* @} */
246 
258 #define CSITX_STREAM_ID_INST_0_STRM_0 ((uint32_t) 0x0U)
259 
260 #define CSITX_STREAM_ID_INST_0_STRM_1 ((uint32_t) 0x1U)
261 
262 #define CSITX_STREAM_ID_INST_0_STRM_2 ((uint32_t) 0x2U)
263 
264 #define CSITX_STREAM_ID_INST_0_STRM_3 ((uint32_t) 0x3U)
265 /* @} */
266 /* ========================================================================== */
267 /* Structure Declarations */
268 /* ========================================================================== */
272 typedef struct
273 {
274  uint32_t inst;
277  uint32_t psmClkFreqDiv;
280  uint32_t pllByteClkDiv;
290  uint32_t pwmCtrlDivLow;
293  uint32_t pwmCtrlDivHigh;
299  uint32_t pllLockStart;
302  uint32_t pllIpDiv;
305  uint32_t pllOpDiv;
308  uint32_t pllFbDiv;
311  uint32_t pllPd;
314  uint32_t laneBandSpeed;
320  uint32_t waitBurstTime;
324  uint32_t txClkExitTime;
328  uint32_t dlWkupTime;
331  uint32_t clWkupTime;
334  uint32_t clkMode;
337  uint32_t dphyMode;
342  uint32_t clSlewRateCtrl;
351  uint32_t dlSlewRateCtrl;
360  uint32_t laneSpeedMbps;
369 } Csitx_DPhyCfg;
370 
371 /* ========================================================================== */
372 /* Global Variables */
373 /* ========================================================================== */
374 
375 /* None */
376 
377 /* ========================================================================== */
378 /* Function Declarations */
379 /* ========================================================================== */
396 /* ========================================================================== */
397 /* Static Function Definitions */
398 /* ========================================================================== */
399 
400 /* None */
401 
402 #ifdef __cplusplus
403 }
404 #endif
405 
406 #endif /* #ifndef CSITX_SOC_H_ */
407 
408 /* @} */
uint32_t pwmCtrlDivLow
Definition: csitx_soc.h:290
uint32_t txClkExitTime
Definition: csitx_soc.h:324
uint32_t pllLockStart
Definition: csitx_soc.h:299
uint32_t dlSlewRateCtrl
Definition: csitx_soc.h:351
uint32_t psmClkFreqDiv
Definition: csitx_soc.h:277
void Csitx_initDPhyCfgParams(Csitx_DPhyCfg *dphyCfg)
Csitx_DPhyCfg structure init function.
uint32_t pllLockThreshold
Definition: csitx_soc.h:296
uint32_t dphyMode
Definition: csitx_soc.h:337
uint32_t waitBurstTime
Definition: csitx_soc.h:320
uint32_t pllFbDiv
Definition: csitx_soc.h:308
uint32_t clkMode
Definition: csitx_soc.h:334
uint32_t pllOpDiv
Definition: csitx_soc.h:305
uint32_t pllPd
Definition: csitx_soc.h:311
uint32_t laneSpeedMbps
Definition: csitx_soc.h:360
uint32_t pwmCtrlDivHigh
Definition: csitx_soc.h:293
D-PHY configuration structure.
Definition: csitx_soc.h:272
uint32_t pllIpDiv
Definition: csitx_soc.h:302
uint32_t clSlewRateCtrl
Definition: csitx_soc.h:342
uint32_t laneBandSpeed
Definition: csitx_soc.h:314
uint32_t inst
Definition: csitx_soc.h:274
uint32_t pllByteClkDiv
Definition: csitx_soc.h:280
uint32_t dlWkupTime
Definition: csitx_soc.h:328
uint32_t clWkupTime
Definition: csitx_soc.h:331