This Module explains about PMIC WatchDog driver parameters and APIs usage. PMIC WatchDog Driver module covers all WatchDog features APIs. Like, set/get watchdog configuration, Enable or disable watchdog, Get watchdog error status, Get watchdog failcount, start watchdog QA sequence and start watchdog trigger mode.
Supported PMIC devices for Watchdog Module:
- TPS6594x (Leo PMIC Device)
- LP8764x (Hera PMIC Device)
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| file | pmic_wdg.h |
| | PMIC Low Level Driver API/interface file for WatchDog APIs.
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| |
◆ PMIC_WDG_DISABLE
| #define PMIC_WDG_DISABLE (bool)false |
◆ PMIC_WDG_ENABLE
| #define PMIC_WDG_ENABLE (bool)true |
◆ PMIC_WDG_RESET_DISABLE
| #define PMIC_WDG_RESET_DISABLE (0x0U) |
◆ PMIC_WDG_RESET_ENABLE
| #define PMIC_WDG_RESET_ENABLE (0x1U) |
◆ PMIC_WDG_RETLONGWIN_DISABLE
| #define PMIC_WDG_RETLONGWIN_DISABLE (bool)false |
◆ PMIC_WDG_RETLONGWIN_ENABLE
| #define PMIC_WDG_RETLONGWIN_ENABLE (bool)true |
◆ PMIC_WDG_PWRHOLD_DISABLE
| #define PMIC_WDG_PWRHOLD_DISABLE (0x0U) |
◆ PMIC_WDG_PWRHOLD_ENABLE
| #define PMIC_WDG_PWRHOLD_ENABLE (0x1U) |
◆ PMIC_WDG_TRIGGER_MODE
| #define PMIC_WDG_TRIGGER_MODE (0x0U) |
◆ PMIC_WDG_QA_MODE
| #define PMIC_WDG_QA_MODE (0x1U) |
◆ PMIC_WDG_RESET_THRESHOLD_COUNT_0
| #define PMIC_WDG_RESET_THRESHOLD_COUNT_0 (0x0U) |
◆ PMIC_WDG_RESET_THRESHOLD_COUNT_1
| #define PMIC_WDG_RESET_THRESHOLD_COUNT_1 (0x1U) |
◆ PMIC_WDG_RESET_THRESHOLD_COUNT_2
| #define PMIC_WDG_RESET_THRESHOLD_COUNT_2 (0x2U) |
◆ PMIC_WDG_RESET_THRESHOLD_COUNT_3
| #define PMIC_WDG_RESET_THRESHOLD_COUNT_3 (0x3U) |
◆ PMIC_WDG_RESET_THRESHOLD_COUNT_4
| #define PMIC_WDG_RESET_THRESHOLD_COUNT_4 (0x4U) |
◆ PMIC_WDG_RESET_THRESHOLD_COUNT_5
| #define PMIC_WDG_RESET_THRESHOLD_COUNT_5 (0x5U) |
◆ PMIC_WDG_RESET_THRESHOLD_COUNT_6
| #define PMIC_WDG_RESET_THRESHOLD_COUNT_6 (0x6U) |
◆ PMIC_WDG_RESET_THRESHOLD_COUNT_7
| #define PMIC_WDG_RESET_THRESHOLD_COUNT_7 (0x7U) |
◆ PMIC_WDG_FAIL_THRESHOLD_COUNT_0
| #define PMIC_WDG_FAIL_THRESHOLD_COUNT_0 (0x0U) |
◆ PMIC_WDG_FAIL_THRESHOLD_COUNT_1
| #define PMIC_WDG_FAIL_THRESHOLD_COUNT_1 (0x1U) |
◆ PMIC_WDG_FAIL_THRESHOLD_COUNT_2
| #define PMIC_WDG_FAIL_THRESHOLD_COUNT_2 (0x2U) |
◆ PMIC_WDG_FAIL_THRESHOLD_COUNT_3
| #define PMIC_WDG_FAIL_THRESHOLD_COUNT_3 (0x3U) |
◆ PMIC_WDG_FAIL_THRESHOLD_COUNT_4
| #define PMIC_WDG_FAIL_THRESHOLD_COUNT_4 (0x4U) |
◆ PMIC_WDG_FAIL_THRESHOLD_COUNT_5
| #define PMIC_WDG_FAIL_THRESHOLD_COUNT_5 (0x5U) |
◆ PMIC_WDG_FAIL_THRESHOLD_COUNT_6
| #define PMIC_WDG_FAIL_THRESHOLD_COUNT_6 (0x6U) |
◆ PMIC_WDG_FAIL_THRESHOLD_COUNT_7
| #define PMIC_WDG_FAIL_THRESHOLD_COUNT_7 (0x7U) |
◆ PMIC_WDG_QA_FEEDBACK_VALUE_0
| #define PMIC_WDG_QA_FEEDBACK_VALUE_0 (0x0U) |
◆ PMIC_WDG_QA_FEEDBACK_VALUE_1
| #define PMIC_WDG_QA_FEEDBACK_VALUE_1 (0x1U) |
◆ PMIC_WDG_QA_FEEDBACK_VALUE_2
| #define PMIC_WDG_QA_FEEDBACK_VALUE_2 (0x2U) |
◆ PMIC_WDG_QA_FEEDBACK_VALUE_3
| #define PMIC_WDG_QA_FEEDBACK_VALUE_3 (0x3U) |
◆ PMIC_WDG_QA_LFSR_VALUE_0
| #define PMIC_WDG_QA_LFSR_VALUE_0 (0x0U) |
◆ PMIC_WDG_QA_LFSR_VALUE_1
| #define PMIC_WDG_QA_LFSR_VALUE_1 (0x1U) |
◆ PMIC_WDG_QA_LFSR_VALUE_2
| #define PMIC_WDG_QA_LFSR_VALUE_2 (0x2U) |
◆ PMIC_WDG_QA_LFSR_VALUE_3
| #define PMIC_WDG_QA_LFSR_VALUE_3 (0x3U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_0
| #define PMIC_WDG_QA_QUES_SEED_VALUE_0 (0x0U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_1
| #define PMIC_WDG_QA_QUES_SEED_VALUE_1 (0x1U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_2
| #define PMIC_WDG_QA_QUES_SEED_VALUE_2 (0x2U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_3
| #define PMIC_WDG_QA_QUES_SEED_VALUE_3 (0x3U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_4
| #define PMIC_WDG_QA_QUES_SEED_VALUE_4 (0x4U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_5
| #define PMIC_WDG_QA_QUES_SEED_VALUE_5 (0x5U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_6
| #define PMIC_WDG_QA_QUES_SEED_VALUE_6 (0x6U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_7
| #define PMIC_WDG_QA_QUES_SEED_VALUE_7 (0x7U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_8
| #define PMIC_WDG_QA_QUES_SEED_VALUE_8 (0x8U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_9
| #define PMIC_WDG_QA_QUES_SEED_VALUE_9 (0x9U) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_10
| #define PMIC_WDG_QA_QUES_SEED_VALUE_10 (0xAU) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_11
| #define PMIC_WDG_QA_QUES_SEED_VALUE_11 (0xBU) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_12
| #define PMIC_WDG_QA_QUES_SEED_VALUE_12 (0xCU) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_13
| #define PMIC_WDG_QA_QUES_SEED_VALUE_13 (0xDU) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_14
| #define PMIC_WDG_QA_QUES_SEED_VALUE_14 (0xEU) |
◆ PMIC_WDG_QA_QUES_SEED_VALUE_15
| #define PMIC_WDG_QA_QUES_SEED_VALUE_15 (0xFU) |
◆ PMIC_CFG_WDG_LONGWINDURATION_VALID
| #define PMIC_CFG_WDG_LONGWINDURATION_VALID (0U) |
◆ PMIC_CFG_WDG_WIN1DURATION_VALID
| #define PMIC_CFG_WDG_WIN1DURATION_VALID (1U) |
◆ PMIC_CFG_WDG_WIN2DURATION_VALID
| #define PMIC_CFG_WDG_WIN2DURATION_VALID (2U) |
◆ PMIC_CFG_WDG_FAILTHRESHOLD_VALID
| #define PMIC_CFG_WDG_FAILTHRESHOLD_VALID (3U) |
◆ PMIC_CFG_WDG_RSTTHRESHOLD_VALID
| #define PMIC_CFG_WDG_RSTTHRESHOLD_VALID (4U) |
◆ PMIC_CFG_WDG_RSTENABLE_VALID
| #define PMIC_CFG_WDG_RSTENABLE_VALID (5U) |
◆ PMIC_CFG_WDG_WDGMODE_VALID
| #define PMIC_CFG_WDG_WDGMODE_VALID (6U) |
◆ PMIC_CFG_WDG_PWRHOLD_VALID
| #define PMIC_CFG_WDG_PWRHOLD_VALID (7U) |
◆ PMIC_CFG_WDG_RETLONGWIN_VALID
| #define PMIC_CFG_WDG_RETLONGWIN_VALID (8U) |
◆ PMIC_CFG_WDG_QA_FDBK_VALID
| #define PMIC_CFG_WDG_QA_FDBK_VALID (9U) |
◆ PMIC_CFG_WDG_QA_LFSR_VALID
| #define PMIC_CFG_WDG_QA_LFSR_VALID (10U) |
◆ PMIC_CFG_WDG_QA_QUES_SEED_VALID
| #define PMIC_CFG_WDG_QA_QUES_SEED_VALID (11U) |
◆ PMIC_WDG_WAIT_CNT_MIN_VAL
| #define PMIC_WDG_WAIT_CNT_MIN_VAL (30U) |
Minimum number of iterations to wait for a Good/Bad event.
◆ PMIC_CFG_WDG_LONGWINDURATION_VALID_SHIFT
| #define PMIC_CFG_WDG_LONGWINDURATION_VALID_SHIFT (1U << PMIC_CFG_WDG_LONGWINDURATION_VALID) |
◆ PMIC_CFG_WDG_WIN1DURATION_VALID_SHIFT
| #define PMIC_CFG_WDG_WIN1DURATION_VALID_SHIFT (1U << PMIC_CFG_WDG_WIN1DURATION_VALID) |
◆ PMIC_CFG_WDG_WIN2DURATION_VALID_SHIFT
| #define PMIC_CFG_WDG_WIN2DURATION_VALID_SHIFT (1U << PMIC_CFG_WDG_WIN2DURATION_VALID) |
◆ PMIC_CFG_WDG_FAILTHRESHOLD_VALID_SHIFT
| #define PMIC_CFG_WDG_FAILTHRESHOLD_VALID_SHIFT (1U << PMIC_CFG_WDG_FAILTHRESHOLD_VALID) |
◆ PMIC_CFG_WDG_RSTTHRESHOLD_VALID_SHIFT
| #define PMIC_CFG_WDG_RSTTHRESHOLD_VALID_SHIFT (1U << PMIC_CFG_WDG_RSTTHRESHOLD_VALID) |
◆ PMIC_CFG_WDG_RSTENABLE_VALID_SHIFT
| #define PMIC_CFG_WDG_RSTENABLE_VALID_SHIFT (1U << PMIC_CFG_WDG_RSTENABLE_VALID) |
◆ PMIC_CFG_WDG_WDGMODE_VALID_SHIFT
| #define PMIC_CFG_WDG_WDGMODE_VALID_SHIFT (1U << PMIC_CFG_WDG_WDGMODE_VALID) |
◆ PMIC_CFG_WDG_PWRHOLD_VALID_SHIFT
| #define PMIC_CFG_WDG_PWRHOLD_VALID_SHIFT (1U << PMIC_CFG_WDG_PWRHOLD_VALID) |
◆ PMIC_CFG_WDG_RETLONGWIN_VALID_SHIFT
| #define PMIC_CFG_WDG_RETLONGWIN_VALID_SHIFT (1U << PMIC_CFG_WDG_RETLONGWIN_VALID) |
◆ PMIC_CFG_WDG_QA_FDBK_VALID_SHIFT
| #define PMIC_CFG_WDG_QA_FDBK_VALID_SHIFT (1U << PMIC_CFG_WDG_QA_FDBK_VALID) |
◆ PMIC_CFG_WDG_QA_LFSR_VALID_SHIFT
| #define PMIC_CFG_WDG_QA_LFSR_VALID_SHIFT (1U << PMIC_CFG_WDG_QA_LFSR_VALID) |
◆ PMIC_CFG_WDG_QA_QUES_SEED_VALID_SHIFT
| #define PMIC_CFG_WDG_QA_QUES_SEED_VALID_SHIFT (1U << PMIC_CFG_WDG_QA_QUES_SEED_VALID) |
◆ PMIC_CFG_WD_LONGWIN_TIMEOUT_ERRSTAT_VALID
| #define PMIC_CFG_WD_LONGWIN_TIMEOUT_ERRSTAT_VALID (0U) |
◆ PMIC_CFG_WD_TIMEOUT_ERRSTAT_VALID
| #define PMIC_CFG_WD_TIMEOUT_ERRSTAT_VALID (1U) |
◆ PMIC_CFG_WD_TRIG_EARLY_ERRSTAT_VALID
| #define PMIC_CFG_WD_TRIG_EARLY_ERRSTAT_VALID (2U) |
◆ PMIC_CFG_WD_ANSW_EARLY_ERRSTAT_VALID
| #define PMIC_CFG_WD_ANSW_EARLY_ERRSTAT_VALID (3U) |
◆ PMIC_CFG_WD_SEQ_ERR_ERRSTAT_VALID
| #define PMIC_CFG_WD_SEQ_ERR_ERRSTAT_VALID (4U) |
◆ PMIC_CFG_WD_ANSW_ERR_ERRSTAT_VALID
| #define PMIC_CFG_WD_ANSW_ERR_ERRSTAT_VALID (5U) |
◆ PMIC_CFG_WD_FAIL_INT_ERRSTAT_VALID
| #define PMIC_CFG_WD_FAIL_INT_ERRSTAT_VALID (6U) |
◆ PMIC_CFG_WD_RST_INT_ERRSTAT_VALID
| #define PMIC_CFG_WD_RST_INT_ERRSTAT_VALID (7U) |
◆ PMIC_CFG_WD_LONGWIN_TIMEOUT_ERRSTAT_VALID_SHIFT
| #define PMIC_CFG_WD_LONGWIN_TIMEOUT_ERRSTAT_VALID_SHIFT (1U << PMIC_CFG_WD_LONGWIN_TIMEOUT_ERRSTAT_VALID) |
◆ PMIC_CFG_WD_TIMEOUT_ERRSTAT_VALID_SHIFT
| #define PMIC_CFG_WD_TIMEOUT_ERRSTAT_VALID_SHIFT (1U << PMIC_CFG_WD_TIMEOUT_ERRSTAT_VALID) |
◆ PMIC_CFG_WD_TRIG_EARLY_ERRSTAT_VALID_SHIFT
| #define PMIC_CFG_WD_TRIG_EARLY_ERRSTAT_VALID_SHIFT (1U << PMIC_CFG_WD_TRIG_EARLY_ERRSTAT_VALID) |
◆ PMIC_CFG_WD_ANSW_EARLY_ERRSTAT_VALID_SHIFT
| #define PMIC_CFG_WD_ANSW_EARLY_ERRSTAT_VALID_SHIFT (1U << PMIC_CFG_WD_ANSW_EARLY_ERRSTAT_VALID) |
◆ PMIC_CFG_WD_SEQ_ERR_ERRSTAT_VALID_SHIFT
| #define PMIC_CFG_WD_SEQ_ERR_ERRSTAT_VALID_SHIFT (1U << PMIC_CFG_WD_SEQ_ERR_ERRSTAT_VALID) |
◆ PMIC_CFG_WD_ANSW_ERR_ERRSTAT_VALID_SHIFT
| #define PMIC_CFG_WD_ANSW_ERR_ERRSTAT_VALID_SHIFT (1U << PMIC_CFG_WD_ANSW_ERR_ERRSTAT_VALID) |
◆ PMIC_CFG_WD_FAIL_INT_ERRSTAT_VALID_SHIFT
| #define PMIC_CFG_WD_FAIL_INT_ERRSTAT_VALID_SHIFT (1U << PMIC_CFG_WD_FAIL_INT_ERRSTAT_VALID) |
◆ PMIC_CFG_WD_RST_INT_ERRSTAT_VALID_SHIFT
| #define PMIC_CFG_WD_RST_INT_ERRSTAT_VALID_SHIFT (1U << PMIC_CFG_WD_RST_INT_ERRSTAT_VALID) |
◆ PMIC_WD_QA_INFINITE_SEQ
| #define PMIC_WD_QA_INFINITE_SEQ (0xFFFFFFFFU) |
Macro for PMIC Watchdog QA infinite sequence.
◆ Pmic_wdgEnable()
API to Enable Watchdog timer.
Requirement: REQ_TAG(PDK-5839), REQ_TAG(PDK-5854) Design: did_pmic_wdg_cfg_readback
This function is used to Enable the PMIC watchdog. User ensure
that, this function needs to be called to enable watchdog timer
before configuring or starting watchdog trigger or QA mode.
- Parameters
-
| pPmicCoreHandle | [IN] PMIC Interface Handle |
- Returns
- PMIC_ST_SUCCESS in case of success or appropriate error code For valid values Pmic_ErrorCodes
◆ Pmic_wdgDisable()
API to Disable Watchdog timer.
Requirement: REQ_TAG(PDK-5839), REQ_TAG(PDK-5854) Design: did_pmic_wdg_cfg_readback
This function is used to Disable the PMIC watchdog. User ensure
that, after using this function, complete watchdog functionality
and configuration will be deactivated.
- Parameters
-
| pPmicCoreHandle | [IN] PMIC Interface Handle |
- Returns
- PMIC_ST_SUCCESS in case of success or appropriate error code For valid values Pmic_ErrorCodes
◆ Pmic_wdgSetCfg()
API to set PMIC watchdog configurations.
Requirement: REQ_TAG(PDK-5839), REQ_TAG(PDK-5854) Design: did_pmic_wdg_cfg_readback
This function is used to configure the watchdog parameters
in the PMIC for trigger mode or Q&A(question and answer) mode,
when corresponding validParam bit fields are set in
Pmic_WdgCfg_t structure.
User has to call Pmic_wdgEnable() before set the configuration.
- Parameters
-
| pPmicCoreHandle | [IN] PMIC Interface Handle |
| wdgCfg | [IN] Watchdog configuration |
- Returns
- PMIC_ST_SUCCESS in case of success or appropriate error code For valid values Pmic_ErrorCodes
◆ Pmic_wdgGetCfg()
API to get PMIC watchdog configurations.
Requirement: REQ_TAG(PDK-5839), REQ_TAG(PDK-5854) Design: did_pmic_wdg_cfg_readback
This function is used to get configuration of the watchdog
from the PMIC for trigger mode or Q&A(question and answer) mode,
when corresponding validParam bit fields are set in
Pmic_WdgCfg_t structure.
User has to call Pmic_wdgEnable() before get the configuration.
- Parameters
-
| pPmicCoreHandle | [IN] PMIC Interface Handle |
| pWdgCfg | [OUT] Watchdog configuration pointer |
- Returns
- PMIC_ST_SUCCESS in case of success or appropriate error code For valid values Pmic_ErrorCodes
◆ Pmic_wdgStartQaSequence()
| int32_t Pmic_wdgStartQaSequence |
( |
Pmic_CoreHandle_t * |
pPmicCoreHandle, |
|
|
uint32_t |
num_of_sequences, |
|
|
uint32_t |
maxCnt |
|
) |
| |
API to Start watchdog QA mode.
Requirement: REQ_TAG(PDK-5839) Design: did_pmic_wdg_cfg_readback
This function is used to start watchdog sequence and continues
till the given num_of_sequences. User has to ensure, configure
all Watchdog QA parameters properly using Pmic_wdgSetCfg() API,
before starting QA sequence using this API.
Note: To perform QA sequences, user has to adjust Long window
time interval, Window1 time interval and Window2 time
inervals depends on errors given by API. If user gets
PMIC_ST_ERR_INV_WDG_WINDOW, then user has to increase the
Long window or window1 time interval. If user gets
PMIC_ST_ERR_WDG_EARLY_ANSWER, then user has to reduce
the Window1 time inerval.
- Parameters
-
| pPmicCoreHandle | [IN] PMIC Interface Handle |
| num_of_sequences | [IN] number of QA sequences If PMIC_WD_QA_INFINITE_SEQ is used, then API runs for infinite sequence. |
| maxCnt | [IN] Number of iterations to wait for an Good/Bad event. The value should be greater than or equal to PMIC_WDG_WAIT_CNT_MIN_VAL. |
- Returns
- PMIC_ST_SUCCESS in case of success or appropriate error code For valid values Pmic_ErrorCodes
◆ Pmic_wdgGetErrorStatus()
API to get PMIC watchdog error status.
Requirement: REQ_TAG(PDK-5839), REQ_TAG(PDK-5854) Design: did_pmic_wdg_cfg_readback
This function is used to get the watchdog error status from the
PMIC for trigger mode or Q&A(question and answer) mode,
when corresponding validParam bit fields are set in
Pmic_WdgErrStatus_t structure.
User has to call Pmic_wdgEnable() before getting the error status.
- Parameters
-
| pPmicCoreHandle | [IN] PMIC Interface Handle |
| pErrStatus | [OUT] Watchdog error status pointer |
- Returns
- PMIC_ST_SUCCESS in case of success or appropriate error code For valid values Pmic_ErrorCodes
◆ Pmic_wdgGetFailCount()
| int32_t Pmic_wdgGetFailCount |
( |
Pmic_CoreHandle_t * |
pPmicCoreHandle, |
|
|
uint8_t * |
pFailCount |
|
) |
| |
API to get PMIC watchdog fail count.
Requirement: REQ_TAG(PDK-5839), REQ_TAG(PDK-5854) Design: did_pmic_wdg_cfg_readback
This function is used to get the watchdog fail count from the PMIC
for trigger mode or Q&A(question and answer) mode.
User has to call Pmic_wdgEnable() before getting the fail count.
- Parameters
-
| pPmicCoreHandle | [IN] PMIC Interface Handle |
| pFailCount | [OUT] Watchdog fail count pointer |
- Returns
- PMIC_ST_SUCCESS in case of success or appropriate error code For valid values Pmic_ErrorCodes
◆ Pmic_wdgStartTriggerSequence()
API to Start watchdog Trigger mode.
Requirement: REQ_TAG(PDK-5854) Design: did_pmic_wdg_cfg_readback
This function is used to start watchdog trigger mode.
User has to ensure, configure all Watchdog trigger parameters
properly using Pmic_wdgSetCfg() API, before starting watchdog
trigger mode using this API. User can use Pmic_wdgSetCfg() API
to stop watchdog trigger mode.
Note: To perform watchdog trigger mode, user has to
adjust Long window time interval, Window1 time interval
and Window2 time inervals as below, depends on the
time-period of the trigger pulse provided by other
device.
1. Longwindow time interval must be greater than Trigger
pulse time period.
2. Window1 time interval must be less than T-off time of
the Trigger pulse time period.
3. Window2 time interval must be greater than T-on time
of the Trigger pulse time period.
4. (Window1 time interval + Window2 time interval)
approximately equal to the Trigger pulse time period.
- Parameters
-
| pPmicCoreHandle | [IN] PMIC Interface Handle |
- Returns
- PMIC_ST_SUCCESS in case of success or appropriate error code For valid values Pmic_ErrorCodes
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