Introduction

Data types used by TPS65941 PMIC device library.

Macros
#define	BOARD_TPS65941_GPIO1_CONF (0x31U)

#define	BOARD_TPS65941_GPIO2_CONF (0x32U)

#define	BOARD_TPS65941_GPIO3_CONF (0x33U)

#define	BOARD_TPS65941_GPIO4_CONF (0x34U)

#define	BOARD_TPS65941_GPIO5_CONF (0x35U)

#define	BOARD_TPS65941_GPIO6_CONF (0x36U)

#define	BOARD_TPS65941_GPIO7_CONF (0x37U)

#define	BOARD_TPS65941_GPIO8_CONF (0x38U)

#define	BOARD_TPS65941_GPIO9_CONF (0x39U)

#define	BOARD_TPS65941_GPIO10_CONF (0x3AU)

#define	BOARD_TPS65941_GPIO11_CONF (0x3BU)

#define	BOARD_TPS65941_NPWRON_CONF (0x3CU)

#define	BOARD_TPS65941_GPIO_OUT_1 (0x3DU)

#define	BOARD_TPS65941_GPIO_OUT_2 (0x3EU)

#define	BOARD_TPS65941_GPIO_IN_1 (0x3FU)

#define	BOARD_TPS65941_GPIO_IN_2 (0x40U)

#define	BOARD_TPS65941_BUCK1_CTRL (0x04U)

#define	BOARD_TPS65941_BUCK2_CTRL (0x06U)

#define	BOARD_TPS65941_BUCK3_CTRL (0x08U)

#define	BOARD_TPS65941_BUCK4_CTRL (0x0AU)

#define	BOARD_TPS65941_BUCK5_CTRL (0x0CU)

#define	BOARD_TPS65941_BUCK1_CONF (0x05U)

#define	BOARD_TPS65941_BUCK2_CONF (0x07U)

#define	BOARD_TPS65941_BUCK3_CONF (0x09U)

#define	BOARD_TPS65941_BUCK4_CONF (0x0BU)

#define	BOARD_TPS65941_BUCK5_CONF (0x0DU)

#define	BOARD_TPS65941_BUCK1_VOUT_1 (0x0EU)

#define	BOARD_TPS65941_BUCK1_VOUT_2 (0x0FU)

#define	BOARD_TPS65941_BUCK2_VOUT_1 (0x10U)

#define	BOARD_TPS65941_BUCK2_VOUT_2 (0x11U)

#define	BOARD_TPS65941_BUCK3_VOUT_1 (0x12U)

#define	BOARD_TPS65941_BUCK3_VOUT_2 (0x13U)

#define	BOARD_TPS65941_BUCK4_VOUT_1 (0x14U)

#define	BOARD_TPS65941_BUCK4_VOUT_2 (0x15U)

#define	BOARD_TPS65941_BUCK5_VOUT_1 (0x16U)

#define	BOARD_TPS65941_BUCK5_VOUT_2 (0x17U)

#define	BOARD_TPS65941_BUCK1_PG_WIN (0x18U)

#define	BOARD_TPS65941_BUCK2_PG_WIN (0x19U)

#define	BOARD_TPS65941_BUCK3_PG_WIN (0x1AU)

#define	BOARD_TPS65941_BUCK4_PG_WIN (0x1BU)

#define	BOARD_TPS65941_BUCK5_PG_WIN (0x1CU)

#define	BOARD_TPS65941_LDO1_CTRL (0x1DU)

#define	BOARD_TPS65941_LDO2_CTRL (0x1EU)

#define	BOARD_TPS65941_LDO3_CTRL (0x1FU)

#define	BOARD_TPS65941_LDO4_CTRL (0x20U)

#define	BOARD_TPS65941_LDO1_VOUT (0x23U)

#define	BOARD_TPS65941_LDO2_VOUT (0x24U)

#define	BOARD_TPS65941_LDO3_VOUT (0x25U)

#define	BOARD_TPS65941_LDO4_VOUT (0x26U)

#define	BOARD_TPS65941_LDO1_PG_WIN (0x27U)

#define	BOARD_TPS65941_LDO2_PG_WIN (0x28U)

#define	BOARD_TPS65941_LDO3_PG_WIN (0x29U)

#define	BOARD_TPS65941_LDO4_PG_WIN (0x2AU)

#define	BOARD_TPS65941_VCCA_VMON_CTRL (0x2BU)

#define	BOARD_TPS65941_VCCA_PG_WINDOW (0x2CU)

#define	BOARD_TPS65941_BUCK_MASK (0x49)

#define	BOARD_TPS65941_LDO_MASK (0x4C)

#define	BOARD_TPS65941_GPIO_MASK (0x4F)

#define	BOARD_TPS65941_STARTUP_MASK (0x52)

#define	BOARD_TPS65941_MISC_WARN_MASK (0x53)

#define	BOARD_TPS65941_MOD_ERR_MASK (0x54)

#define	BOARD_TPS65941_FSM_ERR_MASK (0x56)

#define	BOARD_TPS65941_INT_TOP (0x5A)

#define	BOARD_TPS65941_BUCK_INT (0x5C)

#define	BOARD_TPS65941_LDO_VMON_INT (0x60)

#define	BOARD_TPS65941_GPIO_INT (0x63)

#define	BOARD_TPS65941_STARTUP_INT (0x65)

#define	BOARD_TPS65941_MISC_INT (0x66)

#define	BOARD_TPS65941_MOD_ERR_INT (0x67)

#define	BOARD_TPS65941_SEV_ERR_INT (0x68)

#define	BOARD_TPS65941_FSM_ERR_INT (0x69)

#define	BOARD_TPS65941_STAT_MISC (0x74U)

#define	BOARD_TPS65941_STAT_MODERATE_ERR (0x75U)

#define	BOARD_TPS65941_STAT_SEVERE_ERR (0x76U)

#define	BOARD_TPS65941_PGOOD_1 (0x78U)

#define	BOARD_TPS65941_PGOOD_2 (0x79U)

#define	BOARD_TPS65941_PGOOD_3 (0x7AU)

#define	BOARD_TPS65941_PGOOD_4 (0x7BU)

#define	BOARD_TPS65941_CONFIG_1 (0x7DU)

#define	BOARD_TPS65941_CONFIG_2 (0x7EU)

#define	BOARD_TPS65941_ESM_MCU_START (0x8FU)

#define	BOARD_TPS65941_ESM_MCU_DELAY1 (0x90U)

#define	BOARD_TPS65941_ESM_MCU_DELAY2 (0x91U)

#define	BOARD_TPS65941_ESM_MCU_MODE_CFG (0x92U)

#define	BOARD_TPS65941_ESM_MCU_HMAX (0x93U)

#define	BOARD_TPS65941_ESM_MCU_HMIN (0x94U)

#define	BOARD_TPS65941_ESM_MCU_LMAX (0x95U)

#define	BOARD_TPS65941_ESM_MCU_LMIN (0x96U)

#define	BOARD_TPS65941_ESM_MCU_ERR_CNT (0x97U)

#define	BOARD_TPS65941_ESM_SOC_START (0x98U)

#define	BOARD_TPS65941_ESM_SOC_DELAY1 (0x99U)

#define	BOARD_TPS65941_ESM_SOC_DELAY2 (0x9AU)

#define	BOARD_TPS65941_ESM_SOC_MODE_CFG (0x9BU)

#define	BOARD_TPS65941_ESM_SOC_HMAX (0x9CU)

#define	BOARD_TPS65941_ESM_SOC_HMIN (0x9DU)

#define	BOARD_TPS65941_ESM_SOC_LMAX (0x9EU)

#define	BOARD_TPS65941_ESM_SOC_LMIN (0x9FU)

#define	BOARD_TPS65941_ESM_SOC_ERR_CNT (0xA0U)

#define	BOARD_TPS65941_RTC_SECONDS (0xB5U)

#define	BOARD_TPS65941_RTC_MINUTES (0xB6U)

#define	BOARD_TPS65941_RTC_HOURS (0xB7U)

#define	BOARD_TPS65941_RTC_DAYS (0xB8U)

#define	BOARD_TPS65941_RTC_MONTHS (0xB9U)

#define	BOARD_TPS65941_RTC_YEARS (0xBAU)

#define	BOARD_TPS65941_RTC_WEEKS (0xBBU)

#define	BOARD_TPS65941_ALARM_SECONDS (0xBCU)

#define	BOARD_TPS65941_ALARM_MINUTES (0xBDU)

#define	BOARD_TPS65941_ALARM_HOURS (0xBEU)

#define	BOARD_TPS65941_ALARM_DAYS (0xBFU)

#define	BOARD_TPS65941_ALARM_MONTHS (0xC0U)

#define	BOARD_TPS65941_ALARM_YEARS (0xC1U)

#define	BOARD_TPS65941_RTC_CTRL_1 (0xC2U)

#define	BOARD_TPS65941_RTC_CTRL_2 (0xC3U)

#define	BOARD_TPS65941_RTC_STATUS (0xC4U)

#define	BOARD_TPS65941_RTC_INTR (0xC5U)

#define	BOARD_TPS65941_WDT_ANSW_REG (0x01U)

#define	BOARD_TPS65941_WDT_QUES_ANSW_CNT (0x02U)

#define	BOARD_TPS65941_WDT_WIN1_CFG (0x03U)

#define	BOARD_TPS65941_WDT_WIN2_CFG (0x04U)

#define	BOARD_TPS65941_WDT_LONGWIN_CFG (0x05U)

#define	BOARD_TPS65941_WDT_MODE_REG (0x06U)

#define	BOARD_TPS65941_WDT_QA_CFG (0x07U)

#define	BOARD_TPS65941_WDT_ERR_STAT (0x08U)

#define	BOARD_TPS65941_WDT_THR_CFG (0x09U)

#define	BOARD_TPS65941_WDT_FAIL_CNT_REG (0x0AU)

#define	BOARD_TPS65941_GPIO_SEL_SHIFT (0x05U)

#define	BOARD_TPS65941_GPIO_DEGLITCH_EN_SHIFT (0x04U)

#define	BOARD_TPS65941_GPIO_PU_PD_EN_SHIFT (0x03U)

#define	BOARD_TPS65941_GPIO_PU_SEL_SHIFT (0x02U)

#define	BOARD_TPS65941_GPIO_OD_SHIFT (0x01U)

#define	BOARD_TPS65941_GPIO_DIR_SHIFT (0x00U)

#define	BOARD_TPS65941_NPWRON_SEL_SHIFT (0x06U)

#define	BOARD_TPS65941_NPWRON_POL_SHIFT (0x05U)

#define	BOARD_TPS65941_NPWRON_PU_PD_EN_SHIFT (0x03U)

#define	BOARD_TPS65941_NPWRON_PU_SEL_SHIFT (0x02U)

#define	BOARD_TPS65941_NPWRON_OD_SHIFT (0x00U)

#define	BOARD_TPS65941_GPIO1_IN_OUT_SHIFT (0x00U)

#define	BOARD_TPS65941_GPIO2_IN_OUT_SHIFT (0x01U)

#define	BOARD_TPS65941_GPIO3_IN_OUT_SHIFT (0x02U)

#define	BOARD_TPS65941_GPIO4_IN_OUT_SHIFT (0x03U)

#define	BOARD_TPS65941_GPIO5_IN_OUT_SHIFT (0x04U)

#define	BOARD_TPS65941_GPIO6_IN_OUT_SHIFT (0x05U)

#define	BOARD_TPS65941_GPIO7_IN_OUT_SHIFT (0x06U)

#define	BOARD_TPS65941_GPIO8_IN_OUT_SHIFT (0x07U)

#define	BOARD_TPS65941_GPIO9_IN_OUT_SHIFT (0x00U)

#define	BOARD_TPS65941_GPIO10_IN_OUT_SHIFT (0x01U)

#define	BOARD_TPS65941_GPIO11_IN_OUT_SHIFT (0x02U)

#define	BOARD_TPS65941_NPWRON_IN_OUT_SHIFT (0x03U)

#define	BOARD_TPS65941_BUCK_VSEL_SHIFT (0x03U)

#define	BOARD_TPS65941_BUCK_EN_SHIFT (0x00U)

#define	BOARD_TPS65941_BUCK_ILIM_SHIFT (0x03U)

#define	BOARD_TPS65941_LDO_EN_SHIFT (0x00U)

#define	BOARD_TPS65941_BUCK_VSET_SHIFT (0x00U)

#define	BOARD_TPS65941_LDO_123_VSET_SHIFT (0x01U)

#define	BOARD_TPS65941_LDO4_VSET_SHIFT (0x00U)

#define	BOARD_TPS65941_PWR_VMON_EN_SHIFT (0x04U)

#define	BOARD_TPS65941_PWR_UV_THR_SHIFT (0x03U)

#define	BOARD_TPS65941_PWR_OV_THR_SHIFT (0x00U)

#define	BOARD_TPS65941_BUCK1_PG_SEL_SHIFT (0x00U)

#define	BOARD_TPS65941_BUCK2_PG_SEL_SHIFT (0x02U)

#define	BOARD_TPS65941_BUCK3_PG_SEL_SHIFT (0x04U)

#define	BOARD_TPS65941_BUCK4_PG_SEL_SHIFT (0x06U)

#define	BOARD_TPS65941_BUCK5_PG_SEL_SHIFT (0x00U)

#define	BOARD_TPS65941_LDO1_PG_SEL_SHIFT (0x00U)

#define	BOARD_TPS65941_LDO2_PG_SEL_SHIFT (0x02U)

#define	BOARD_TPS65941_LDO3_PG_SEL_SHIFT (0x04U)

#define	BOARD_TPS65941_LDO4_PG_SEL_SHIFT (0x06U)

#define	BOARD_TPS65941_VCCA_VMON_EN_SHIFT (0x00U)

#define	BOARD_TPS65941_VCCA_PG_SET_SHIFT (0x06U)

#define	BOARD_TPS65941_VCCA_UV_THR_SHIFT (0x03U)

#define	BOARD_TPS65941_VCCA_OV_THR_SHIFT (0x00U)

#define	BOARD_TPS65941_TWARN_STAT_SHIFT (0x03U)

#define	BOARD_TPS65941_TSD_ORD_STAT_SHIFT (0x00U)

#define	BOARD_TPS65941_TSD_IMM_STAT_SHIFT (0x00U)

#define	BOARD_TPS65941_PGOOD_WINDOW_SHIFT (0x07U)

#define	BOARD_TPS65941_PGOOD_POL_SHIFT (0x06U)

#define	BOARD_TPS65941_PGOOD_NRSTOUT_SOC_SHIFT (0x05U)

#define	BOARD_TPS65941_PGOOD_NRSTOUT_SHIFT (0x04U)

#define	BOARD_TPS65941_PGOOD_TDIE_WARN_SHIFT (0x03U)

#define	BOARD_TPS65941_PGOOD_VCCA_SEL_SHIFT (0x00U)

#define	BOARD_TPS65941_TWARN_LVL_SHIFT (0x00U)

#define	BOARD_TPS65941_ESM_START_SHIFT (0x00U)

#define	BOARD_TPS65941_ESM_DLY1_SHIFT (0x00U)

#define	BOARD_TPS65941_ESM_DLY2_SHIFT (0x00U)

#define	BOARD_TPS65941_ESM_MODE_SHIFT (0x07U)

#define	BOARD_TPS65941_ESM_EN_SHIFT (0x06U)

#define	BOARD_TPS65941_ESM_ERR_THR_SHIFT (0x00U)

#define	BOARD_TPS65941_ESM_HMAX_SHIFT (0x00U)

#define	BOARD_TPS65941_ESM_HMIN_SHIFT (0x00U)

#define	BOARD_TPS65941_ESM_LMAX_SHIFT (0x00U)

#define	BOARD_TPS65941_ESM_LMIN_SHIFT (0x00U)

#define	BOARD_TPS65941_ESM_ERR_CNT_SHIFT (0x00U)

#define	BOARD_TPS65941_RTC_ALRM_SEC_1_SHIFT (0x04U)

#define	BOARD_TPS65941_RTC_ALRM_SEC_0_SHIFT (0x00U)

#define	BOARD_TPS65941_RTC_ALRM_MIN_1_SHIFT (0x04U)

#define	BOARD_TPS65941_RTC_ALRM_MIN_0_SHIFT (0x00U)

#define	BOARD_TPS65941_RTC_ALRM_AM_PM_SHIFT (0x07U)

#define	BOARD_TPS65941_RTC_ALRM_HR_1_SHIFT (0x04U)

#define	BOARD_TPS65941_RTC_ALRM_HR_0_SHIFT (0x00U)

#define	BOARD_TPS65941_RTC_ALRM_DAY_1_SHIFT (0x04U)

#define	BOARD_TPS65941_RTC_ALRM_DAY_0_SHIFT (0x00U)

#define	BOARD_TPS65941_RTC_ALRM_MON_1_SHIFT (0x04U)

#define	BOARD_TPS65941_RTC_ALRM_MON_0_SHIFT (0x00U)

#define	BOARD_TPS65941_RTC_ALRM_YR_1_SHIFT (0x04U)

#define	BOARD_TPS65941_RTC_ALRM_YR_0_SHIFT (0x00U)

#define	BOARD_TPS65941_RTC_WEEK_SHIFT (0x00U)

#define	BOARD_TPS65941_RTC_REG_OPT_SHIFT (0x07U)

#define	BOARD_TPS65941_GET_TIME_SHIFT (0x06U)

#define	BOARD_TPS65941_HOUR_MODE_SHIFT (0x03U)

#define	BOARD_TPS65941_ROUND_30S_SHIFT (0x01U)

#define	BOARD_TPS65941_STOP_RTC_SHIFT (0x00U)

#define	BOARD_TPS65941_ALRM_STAT_SHIFT (0x06U)

#define	BOARD_TPS65941_TIMER_STAT_SHIFT (0x05U)

#define	BOARD_TPS65941_RUN_SHIFT (0x01U)

#define	BOARD_TPS65941_ALARM_INTR_SHIFT (0x03U)

#define	BOARD_TPS65941_TIMER_INTR_SHIFT (0x02U)

#define	BOARD_TPS65941_TIMER_PERIOD_SHIFT (0x00U)

#define	BOARD_TPS65941_WDT_ANSW_SHIFT (0x00U)

#define	BOARD_TPS65941_WDT_ANSW_CNT_SHIFT (0x04U)

#define	BOARD_TPS65941_WDT_QUES_SHIFT (0x00U)

#define	BOARD_TPS65941_WDT_WIN1_CFG_SHIFT (0x00U)

#define	BOARD_TPS65941_WDT_WIN2_CFG_SHIFT (0x00U)

#define	BOARD_TPS65941_WDT_LONGWIN_CFG_SHIFT (0x00U)

#define	BOARD_TPS65941_WDT_MODE_SHIFT (0x01U)

#define	BOARD_TPS65941_WDT_LONGWIN_RET_SHIFT (0x00U)

#define	BOARD_TPS65941_WDT_RST_STAT_SHIFT (0x07U)

#define	BOARD_TPS65941_WDT_FAIL_STAT_SHIFT (0x06U)

#define	BOARD_TPS65941_WDT_ANSW_ERR_SHIFT (0x05U)

#define	BOARD_TPS65941_WDT_SEQ_ERR_SHIFT (0x04U)

#define	BOARD_TPS65941_WDT_ANSW_ERLY_SHIFT (0x03U)

#define	BOARD_TPS65941_WDT_TRIG_ERLY_SHIFT (0x02U)

#define	BOARD_TPS65941_WDT_TIMEOUT_SHIFT (0x01U)

#define	BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_SHIFT (0x00U)

#define	BOARD_TPS65941_WDT_RST_EN_SHIFT (0x07U)

#define	BOARD_TPS65941_WDT_EN_SHIFT (0x06U)

#define	BOARD_TPS65941_WDT_FAIL_THR_SHIFT (0x03U)

#define	BOARD_TPS65941_WDT_RST_THR_SHIFT (0x00U)

#define	BOARD_TPS65941_WDT_BAD_EVT_SHIFT (0x06U)

#define	BOARD_TPS65941_WDT_FIRST_OK_SHIFT (0x05U)

#define	BOARD_TPS65941_WDT_FAIL_CNT_SHIFT (0x00U)

#define	BOARD_TPS65941_GPIO_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_SEL_SHIFT)

#define	BOARD_TPS65941_GPIO_DEGLITCH_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_DEGLITCH_EN_SHIFT)

#define	BOARD_TPS65941_GPIO_PU_PD_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_PU_PD_EN_SHIFT)

#define	BOARD_TPS65941_GPIO_PU_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_PU_SEL_SHIFT)

#define	BOARD_TPS65941_GPIO_OD_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_OD_SHIFT)

#define	BOARD_TPS65941_GPIO_DIR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_DIR_SHIFT)

#define	BOARD_TPS65941_NPWRON_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_SEL_SHIFT)

#define	BOARD_TPS65941_NPWRON_POL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_POL_SHIFT)

#define	BOARD_TPS65941_NPWRON_PU_PD_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_PU_PD_EN_SHIFT)

#define	BOARD_TPS65941_NPWRON_PU_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_PU_SEL_SHIFT)

#define	BOARD_TPS65941_NPWRON_OD_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_OD_SHIFT)

#define	BOARD_TPS65941_GPIO1_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO1_IN_OUT_SHIFT)

#define	BOARD_TPS65941_GPIO2_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO2_IN_OUT_SHIFT)

#define	BOARD_TPS65941_GPIO3_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO3_IN_OUT_SHIFT)

#define	BOARD_TPS65941_GPIO4_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO4_IN_OUT_SHIFT)

#define	BOARD_TPS65941_GPIO5_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO5_IN_OUT_SHIFT)

#define	BOARD_TPS65941_GPIO6_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO6_IN_OUT_SHIFT)

#define	BOARD_TPS65941_GPIO7_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO7_IN_OUT_SHIFT)

#define	BOARD_TPS65941_GPIO8_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO8_IN_OUT_SHIFT)

#define	BOARD_TPS65941_GPIO9_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO9_IN_OUT_SHIFT)

#define	BOARD_TPS65941_GPIO10_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO10_IN_OUT_SHIFT)

#define	BOARD_TPS65941_GPIO11_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO11_IN_OUT_SHIFT)

#define	BOARD_TPS65941_NPWRON_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_IN_OUT_SHIFT)

#define	BOARD_TPS65941_BUCK_VSEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_BUCK_VSEL_SHIFT)

#define	BOARD_TPS65941_BUCK_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_BUCK_EN_SHIFT)

#define	BOARD_TPS65941_BUCK_ILIM_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_BUCK_ILIM_SHIFT)

#define	BOARD_TPS65941_LDO_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_LDO_EN_SHIFT)

#define	BOARD_TPS65941_BUCK_VSET_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_BUCK_VSET_SHIFT)

#define	BOARD_TPS65941_LDO_123_VSET_BIT_MASK (uint8_t)(0x3F << BOARD_TPS65941_LDO_123_VSET_SHIFT)

#define	BOARD_TPS65941_LDO4_VSET_BIT_MASK (uint8_t)(0x3F << BOARD_TPS65941_LDO4_VSET_SHIFT)

#define	BOARD_TPS65941_PWR_VMON_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PWR_VMON_EN_SHIFT)

#define	BOARD_TPS65941_PWR_UV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_PWR_UV_THR_SHIFT)

#define	BOARD_TPS65941_PWR_OV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_PWR_OV_THR_SHIFT)

#define	BOARD_TPS65941_BUCK1_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK1_PG_SEL_SHIFT)

#define	BOARD_TPS65941_BUCK2_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK2_PG_SEL_SHIFT)

#define	BOARD_TPS65941_BUCK3_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK3_PG_SEL_SHIFT)

#define	BOARD_TPS65941_BUCK4_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK4_PG_SEL_SHIFT)

#define	BOARD_TPS65941_BUCK5_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK5_PG_SEL_SHIFT)

#define	BOARD_TPS65941_LDO1_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO1_PG_SEL_SHIFT)

#define	BOARD_TPS65941_LDO2_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO2_PG_SEL_SHIFT)

#define	BOARD_TPS65941_LDO3_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO3_PG_SEL_SHIFT)

#define	BOARD_TPS65941_LDO4_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO4_PG_SEL_SHIFT)

#define	BOARD_TPS65941_VCCA_VMON_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_VCCA_VMON_EN_SHIFT)

#define	BOARD_TPS65941_VCCA_PG_SET_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_VCCA_PG_SET_SHIFT)

#define	BOARD_TPS65941_VCCA_UV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_VCCA_UV_THR_SHIFT)

#define	BOARD_TPS65941_VCCA_OV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_VCCA_OV_THR_SHIFT)

#define	BOARD_TPS65941_TWARN_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TWARN_STAT_SHIFT)

#define	BOARD_TPS65941_TSD_ORD_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TSD_ORD_STAT_SHIFT)

#define	BOARD_TPS65941_TSD_IMM_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TSD_IMM_STAT_SHIFT)

#define	BOARD_TPS65941_PGOOD_WINDOW_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_WINDOW_SHIFT)

#define	BOARD_TPS65941_PGOOD_POL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_POL_SHIFT)

#define	BOARD_TPS65941_PGOOD_NRSTOUT_SOC_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_NRSTOUT_SOC_SHIFT)

#define	BOARD_TPS65941_PGOOD_NRSTOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_NRSTOUT_SHIFT)

#define	BOARD_TPS65941_PGOOD_TDIE_WARN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_TDIE_WARN_SHIFT)

#define	BOARD_TPS65941_PGOOD_VCCA_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_VCCA_SEL_SHIFT)

#define	BOARD_TPS65941_TWARN_LVL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TWARN_LVL_SHIFT)

#define	BOARD_TPS65941_ESM_START_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_START_SHIFT)

#define	BOARD_TPS65941_ESM_DLY1_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_DLY1_SHIFT)

#define	BOARD_TPS65941_ESM_DLY2_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_DLY2_SHIFT)

#define	BOARD_TPS65941_ESM_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_MODE_SHIFT)

#define	BOARD_TPS65941_ESM_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_EN_SHIFT)

#define	BOARD_TPS65941_ESM_ERR_THR_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_ESM_ERR_THR_SHIFT)

#define	BOARD_TPS65941_ESM_HMAX_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_HMAX_SHIFT)

#define	BOARD_TPS65941_ESM_HMIN_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_HMIN_SHIFT)

#define	BOARD_TPS65941_ESM_LMAX_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_LMAX_SHIFT)

#define	BOARD_TPS65941_ESM_LMIN_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_LMIN_SHIFT)

#define	BOARD_TPS65941_ESM_ERR_CNT_BIT_MASK (uint8_t)(0x1F << BOARD_TPS65941_ESM_ERR_CNT_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_SEC_1_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_ALRM_SEC_1_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_SEC_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_SEC_0_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_MIN_1_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_ALRM_MIN_1_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_MIN_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_MIN_0_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_AM_PM_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_ALRM_AM_PM_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_HR_1_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_RTC_ALRM_HR_1_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_HR_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_HR_0_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_DAY_1_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_RTC_ALRM_DAY_1_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_DAY_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_DAY_0_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_MON_1_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_ALRM_MON_1_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_MON_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_MON_0_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_YR_1_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_YR_1_SHIFT)

#define	BOARD_TPS65941_RTC_ALRM_YR_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_YR_0_SHIFT)

#define	BOARD_TPS65941_RTC_WEEK_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_WEEK_SHIFT)

#define	BOARD_TPS65941_RTC_REG_OPT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_REG_OPT_SHIFT)

#define	BOARD_TPS65941_GET_TIME_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GET_TIME_SHIFT)

#define	BOARD_TPS65941_HOUR_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_HOUR_MODE_SHIFT)

#define	BOARD_TPS65941_ROUND_30S_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ROUND_30S_SHIFT)

#define	BOARD_TPS65941_STOP_RTC_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_STOP_RTC_SHIFT)

#define	BOARD_TPS65941_ALRM_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ALRM_STAT_SHIFT)

#define	BOARD_TPS65941_TIMER_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TIMER_STAT_SHIFT)

#define	BOARD_TPS65941_RUN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RUN_SHIFT)

#define	BOARD_TPS65941_ALARM_INTR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ALARM_INTR_SHIFT)

#define	BOARD_TPS65941_TIMER_INTR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TIMER_INTR_SHIFT)

#define	BOARD_TPS65941_TIMER_PERIOD_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_TIMER_PERIOD_SHIFT)

#define	BOARD_TPS65941_WDT_ANSW_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_WDT_ANSW_SHIFT)

#define	BOARD_TPS65941_WDT_ANSW_CNT_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_WDT_ANSW_CNT_SHIFT)

#define	BOARD_TPS65941_WDT_QUES_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_WDT_QUES_SHIFT)

#define	BOARD_TPS65941_WDT_WIN1_CFG_BIT_MASK (uint8_t)(0x7F << BOARD_TPS65941_WDT_WIN1_CFG_SHIFT)

#define	BOARD_TPS65941_WDT_WIN2_CFG_BIT_MASK (uint8_t)(0x7F << BOARD_TPS65941_WDT_WIN2_CFG_SHIFT)

#define	BOARD_TPS65941_WDT_LONGWIN_CFG_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_WDT_LONGWIN_CFG_SHIFT)

#define	BOARD_TPS65941_WDT_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_MODE_SHIFT)

#define	BOARD_TPS65941_WDT_LONGWIN_RET_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_LONGWIN_RET_SHIFT)

#define	BOARD_TPS65941_WDT_RST_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_RST_STAT_SHIFT)

#define	BOARD_TPS65941_WDT_FAIL_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FAIL_STAT_SHIFT)

#define	BOARD_TPS65941_WDT_ANSW_ERR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_ANSW_ERR_SHIFT)

#define	BOARD_TPS65941_WDT_SEQ_ERR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_SEQ_ERR_SHIFT)

#define	BOARD_TPS65941_WDT_ANSW_ERLY_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_ANSW_ERLY_SHIFT)

#define	BOARD_TPS65941_WDT_TRIG_ERLY_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_TRIG_ERLY_SHIFT)

#define	BOARD_TPS65941_WDT_TIMEOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_TIMEOUT_SHIFT)

#define	BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_SHIFT)

#define	BOARD_TPS65941_WDT_RST_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_RST_EN_SHIFT)

#define	BOARD_TPS65941_WDT_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_EN_SHIFT)

#define	BOARD_TPS65941_WDT_FAIL_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_WDT_FAIL_THR_SHIFT)

#define	BOARD_TPS65941_WDT_RST_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_WDT_RST_THR_SHIFT)

#define	BOARD_TPS65941_WDT_BAD_EVT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_BAD_EVT_SHIFT)

#define	BOARD_TPS65941_WDT_FIRST_OK_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FIRST_OK_SHIFT)

#define	BOARD_TPS65941_WDT_FAIL_CNT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FAIL_CNT_SHIFT)

#define	BOARD_TPS65941_DISABLE (0U)

#define	BOARD_TPS65941_ENABLE (1U)

#define	BOARD_TPS65941_PULLUP_DOWN (0U)

#define	BOARD_TPS65941_OPEN_DRAIN (1U)

#define	BOARD_TPS65941_GPIO_LOW (0U)

#define	BOARD_TPS65941_GPIO_HIGH (1U)

#define	BOARD_TPS65941_GPIO_DIR_IN (0U)

#define	BOARD_TPS65941_GPIO_DIR_OUT (1U)

#define	BOARD_TPS65941_GPIO_MODE (0x0U)

#define	BOARD_TPS65941_GPIO_PIN_MAX (11U)

#define	BOARD_TPS65941_NPWRON_PIN (0)

#define	BOARD_TPS65941_BUCK1_RESOURCE (0U)

#define	BOARD_TPS65941_BUCK2_RESOURCE (1U)

#define	BOARD_TPS65941_BUCK3_RESOURCE (2U)

#define	BOARD_TPS65941_BUCK4_RESOURCE (3U)

#define	BOARD_TPS65941_BUCK5_RESOURCE (4U)

#define	BOARD_TPS65941_LDO1_RESOURCE (5U)

#define	BOARD_TPS65941_LDO2_RESOURCE (6U)

#define	BOARD_TPS65941_LDO3_RESOURCE (7U)

#define	BOARD_TPS65941_LDO4_RESOURCE (8U)

#define	BOARD_TPS65941_INTR_TYPE_BUCK_ERR (0U)

#define	BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR (1U)

#define	BOARD_TPS65941_INTR_TYPE_SEVERE_ERR (2U)

#define	BOARD_TPS65941_INTR_TYPE_MODERATE_ERR (3U)

#define	BOARD_TPS65941_INTR_TYPE_MISC_WARN (4U)

#define	BOARD_TPS65941_INTR_TYPE_STARTUP_SRC (5U)

#define	BOARD_TPS65941_INTR_TYPE_GPIO (6U)

#define	BOARD_TPS65941_INTR_TYPE_FSM_ERR (7U)

#define	BOARD_TPS65941_INTR_ID_BUCK1_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x00U)

#define	BOARD_TPS65941_INTR_ID_BUCK1_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x01U)

#define	BOARD_TPS65941_INTR_ID_BUCK1_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (1 << 8) \| 0x02U)

#define	BOARD_TPS65941_INTR_ID_BUCK1_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x03U)

#define	BOARD_TPS65941_INTR_ID_BUCK2_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x04U)

#define	BOARD_TPS65941_INTR_ID_BUCK2_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x05U)

#define	BOARD_TPS65941_INTR_ID_BUCK2_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (1 << 8) \| 0x06U)

#define	BOARD_TPS65941_INTR_ID_BUCK2_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x07U)

#define	BOARD_TPS65941_INTR_ID_BUCK3_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x08U)

#define	BOARD_TPS65941_INTR_ID_BUCK3_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x09U)

#define	BOARD_TPS65941_INTR_ID_BUCK3_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (1 << 8) \| 0x0AU)

#define	BOARD_TPS65941_INTR_ID_BUCK3_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x0BU)

#define	BOARD_TPS65941_INTR_ID_BUCK4_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x0CU)

#define	BOARD_TPS65941_INTR_ID_BUCK4_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x0DU)

#define	BOARD_TPS65941_INTR_ID_BUCK4_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (1 << 8) \| 0x0EU)

#define	BOARD_TPS65941_INTR_ID_BUCK4_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x0FU)

#define	BOARD_TPS65941_INTR_ID_BUCK5_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x10U)

#define	BOARD_TPS65941_INTR_ID_BUCK5_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x11U)

#define	BOARD_TPS65941_INTR_ID_BUCK5_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (1 << 8) \| 0x12U)

#define	BOARD_TPS65941_INTR_ID_BUCK5_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) \| (0 << 8) \| 0x13U)

#define	BOARD_TPS65941_INTR_ID_LDO1_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x00U)

#define	BOARD_TPS65941_INTR_ID_LDO1_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x01U)

#define	BOARD_TPS65941_INTR_ID_LDO1_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (1 << 8) \| 0x02U)

#define	BOARD_TPS65941_INTR_ID_LDO1_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x03U)

#define	BOARD_TPS65941_INTR_ID_LDO2_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x04U)

#define	BOARD_TPS65941_INTR_ID_LDO2_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x05U)

#define	BOARD_TPS65941_INTR_ID_LDO2_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (1 << 8) \| 0x06U)

#define	BOARD_TPS65941_INTR_ID_LDO2_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x07U)

#define	BOARD_TPS65941_INTR_ID_LDO3_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x08U)

#define	BOARD_TPS65941_INTR_ID_LDO3_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x09U)

#define	BOARD_TPS65941_INTR_ID_LDO3_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (1 << 8) \| 0x0AU)

#define	BOARD_TPS65941_INTR_ID_LDO3_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x0BU)

#define	BOARD_TPS65941_INTR_ID_LDO4_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x0CU)

#define	BOARD_TPS65941_INTR_ID_LDO4_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x0DU)

#define	BOARD_TPS65941_INTR_ID_LDO4_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (1 << 8) \| 0x0EU)

#define	BOARD_TPS65941_INTR_ID_LDO4_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x0FU)

#define	BOARD_TPS65941_INTR_ID_VCCA_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x10U)

#define	BOARD_TPS65941_INTR_ID_VCCA_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) \| (0 << 8) \| 0x11U)

#define	BOARD_TPS65941_INTR_ID_GPIO1_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x00U)

#define	BOARD_TPS65941_INTR_ID_GPIO2_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x01U)

#define	BOARD_TPS65941_INTR_ID_GPIO3_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x02U)

#define	BOARD_TPS65941_INTR_ID_GPIO4_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x03U)

#define	BOARD_TPS65941_INTR_ID_GPIO5_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x04U)

#define	BOARD_TPS65941_INTR_ID_GPIO6_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x05U)

#define	BOARD_TPS65941_INTR_ID_GPIO7_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x06U)

#define	BOARD_TPS65941_INTR_ID_GPIO8_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x07U)

#define	BOARD_TPS65941_INTR_ID_GPIO9_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x10U)

#define	BOARD_TPS65941_INTR_ID_GPIO10_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x11U)

#define	BOARD_TPS65941_INTR_ID_GPIO11_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x12U)

#define	BOARD_TPS65941_INTR_ID_GPIO1_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x08U)

#define	BOARD_TPS65941_INTR_ID_GPIO2_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x09U)

#define	BOARD_TPS65941_INTR_ID_GPIO3_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x0AU)

#define	BOARD_TPS65941_INTR_ID_GPIO4_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x0BU)

#define	BOARD_TPS65941_INTR_ID_GPIO5_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x0CU)

#define	BOARD_TPS65941_INTR_ID_GPIO6_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x0DU)

#define	BOARD_TPS65941_INTR_ID_GPIO7_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x0EU)

#define	BOARD_TPS65941_INTR_ID_GPIO8_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x0FU)

#define	BOARD_TPS65941_INTR_ID_GPIO9_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x13U)

#define	BOARD_TPS65941_INTR_ID_GPIO10_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x14U)

#define	BOARD_TPS65941_INTR_ID_GPIO11_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) \| (0 << 8) \| 0x15U)

#define	BOARD_TPS65941_INTR_ID_FSD ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) \| (0 << 8) \| 0x04U)

#define	BOARD_TPS65941_INTR_ID_RTC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) \| (1 << 8) \| 0x02U)

#define	BOARD_TPS65941_INTR_ID_ENABLE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) \| (0 << 8) \| 0x01U)

#define	BOARD_TPS65941_INTR_ID_NPWRON_START ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) \| (0 << 8) \| 0x00U)

#define	BOARD_TPS65941_INTR_ID_TWARN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) \| (0 << 8) \| 0x03U)

#define	BOARD_TPS65941_INTR_ID_EXT_CLK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) \| (0 << 8) \| 0x01U)

#define	BOARD_TPS65941_INTR_ID_BIST_PASS ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) \| (0 << 8) \| 0x00U)

#define	BOARD_TPS65941_INTR_ID_RECOV_CNT ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) \| (1 << 8) \| 0x06U)

#define	BOARD_TPS65941_INTR_ID_NPWRON_LONG ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) \| (0 << 8) \| 0x05U)

#define	BOARD_TPS65941_INTR_ID_SPMI_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) \| (0 << 8) \| 0x04U)

#define	BOARD_TPS65941_INTR_ID_PFSM_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) \| (0 << 8) \| 0x03U)

#define	BOARD_TPS65941_INTR_ID_REG_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) \| (0 << 8) \| 0x02U)

#define	BOARD_TPS65941_INTR_ID_BIST_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) \| (0 << 8) \| 0x01U)

#define	BOARD_TPS65941_INTR_ID_TSD_ORD ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) \| (1 << 8) \| 0x00U)

#define	BOARD_TPS65941_INTR_ID_VCCA_OVP ((((uint32_t)BOARD_TPS65941_INTR_TYPE_SEVERE_ERR) << 16) \| (1 << 8) \| 0x01U)

#define	BOARD_TPS65941_INTR_ID_TSD_IMM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_SEVERE_ERR) << 16) \| (1 << 8) \| 0x00U)

#define	BOARD_TPS65941_INTR_ID_IMM_SHUTDOWN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x00U)

#define	BOARD_TPS65941_INTR_ID_ORD_SHUTDOWN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x01U)

#define	BOARD_TPS65941_INTR_ID_MCU_PWR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x02U)

#define	BOARD_TPS65941_INTR_ID_SOC_PWR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x03U)

#define	BOARD_TPS65941_INTR_ID_COMM_FRM_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x08U)

#define	BOARD_TPS65941_INTR_ID_COMM_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x09U)

#define	BOARD_TPS65941_INTR_ID_COMM_ADR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x0BU)

#define	BOARD_TPS65941_INTR_ID_I2C2_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x0DU)

#define	BOARD_TPS65941_INTR_ID_I2C2_ADR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x0FU)

#define	BOARD_TPS65941_INTR_ID_EN_DRV_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x10U)

#define	BOARD_TPS65941_INTR_ID_NINT_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x11U)

#define	BOARD_TPS65941_INTR_ID_NRSTOUT_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x12U)

#define	BOARD_TPS65941_INTR_ID_NRSTOUT_SOC_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x13U)

#define	BOARD_TPS65941_INTR_ID_ESM_SOC_PIN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x18U)

#define	BOARD_TPS65941_INTR_ID_ESM_SOC_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x19U)

#define	BOARD_TPS65941_INTR_ID_ESM_SOC_RST ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x1AU)

#define	BOARD_TPS65941_INTR_ID_ESM_MCU_PIN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x1BU)

#define	BOARD_TPS65941_INTR_ID_ESM_MCU_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x1CU)

#define	BOARD_TPS65941_INTR_ID_ESM_MCU_RST ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) \| (0 << 8) \| 0x1DU)

#define	BOARD_TPS65941_INTR_REG_WIDTH (0x8U)

#define	BOARD_TPS65941_INTR_ENABLE (0)

#define	BOARD_TPS65941_INTR_DISABLE (1)

#define	BOARD_TPS65941_INTR_SET (1)

#define	BOARD_TPS65941_INTR_UNSET (0)

#define	BOARD_TPS65941_PG_3V3_LEVEL (0)

#define	BOARD_TPS65941_PG_5V_LEVEL (1)

#define	BOARD_TPS65941_PG_THR_3_PERCENT (0x0U)

#define	BOARD_TPS65941_PG_THR_3_5_PERCENT (0x1U)

#define	BOARD_TPS65941_PG_THR_4_PERCENT (0x2U)

#define	BOARD_TPS65941_PG_THR_5_PERCENT (0x3U)

#define	BOARD_TPS65941_PG_THR_6_PERCENT (0x4U)

#define	BOARD_TPS65941_PG_THR_7_PERCENT (0x5U)

#define	BOARD_TPS65941_PG_THR_8_PERCENT (0x6U)

#define	BOARD_TPS65941_PG_THR_10_PERCENT (0x7U)

#define	BOARD_TPS65941_ILIM_2_5A (0x2U)

#define	BOARD_TPS65941_ILIM_3_5A (0x3U)

#define	BOARD_TPS65941_ILIM_4_5A (0x4U)

#define	BOARD_TPS65941_ILIM_5_5A (0x5U)

#define	BOARD_TPS65941_OV_UV_DISABLE (0)

#define	BOARD_TPS65941_OV_UV_ENABLE (1)

#define	BOARD_TPS65941_PGOOD_MASK (0U)

#define	BOARD_TPS65941_PGOOD_UNMASK (1U)

#define	BOARD_TPS65941_UV_MONITOR (0U)

#define	BOARD_TPS65941_UV_OV_MONITOR (1U)

#define	BOARD_TPS65941_TDIE_NO_WARN (0)

#define	BOARD_TPS65941_TDIE_WARN (1)

#define	BOARD_TPS65941_TDIE_WARN_ORD_SD (2)

#define	BOARD_TPS65941_TDIE_WARN_IMM_SD (3)

#define	BOARD_TPS65941_THERMAL_TEMP_120C (0x0U)

#define	BOARD_TPS65941_THERMAL_TEMP_130C (0x1U)

#define	BOARD_TPS65941_ESM_STOP (0x0)

#define	BOARD_TPS65941_ESM_START (0x1)

#define	BOARD_TPS65941_ESM_DISABLE (0x0)

#define	BOARD_TPS65941_ESM_ENABLE (0x1)

#define	BOARD_TPS65941_SECOND_INTR_PERIOD (0x0U)

#define	BOARD_TPS65941_MINUTE_INTR_PERIOD (0x1U)

#define	BOARD_TPS65941_HOUR_INTR_PERIOD (0x2U)

#define	BOARD_TPS65941_DAY_INTR_PERIOD (0x3U)

#define	BOARD_TPS65941_ALARM_INTR_ENABLE (0x1U)

#define	BOARD_TPS65941_ALARM_INTR_DISABLE (0x0U)

#define	BOARD_TPS65941_TIMER_INTR_ENABLE (0x1U)

#define	BOARD_TPS65941_TIMER_INTR_DISABLE (0x0U)

#define	BOARD_TPS65941_WDT_DISABLE (0x1U)

#define	BOARD_TPS65941_WDT_ENABLE (0x0U)

#define	BOARD_TPS65941_WDT_TRIGGER_MODE (0x0U)

#define	BOARD_TPS65941_WDT_QA_MODE (0x1U)

#define	BOARD_TPS65941_WDT_RST_DISABLE (0x0U)

#define	BOARD_TPS65941_WDT_RST_ENABLE (0x1U)

#define	BOARD_TPS65941_ESM_SOC (0x0U)

#define	BOARD_TPS65941_ESM_MCU (0x1U)

#define	BOARD_TPS65941_ESM_LEVEL_MODE (0x0U)

#define	BOARD_TPS65941_ESM_PWM_MODE (0x1U)

#define	BOARD_TPS65941_12_HOUR_MODE (1)

#define	BOARD_TPS65941_24_HOUR_MODE (0)

#define	BOARD_TPS65941_AM_MODE (0)

#define	BOARD_TPS65941_PM_MODE (1)

#define	BOARD_TPS65941_SUNDAY (0)

#define	BOARD_TPS65941_MONDAY (1)

#define	BOARD_TPS65941_TUESDAY (2)

#define	BOARD_TPS65941_WEDNESDAY (3)

#define	BOARD_TPS65941_THURSDAY (4)

#define	BOARD_TPS65941_FRIDAY (5)

#define	BOARD_TPS65941_SATURDAY (6)

#define	BOARD_TPS65941_RTC_FROZEN (0)

#define	BOARD_TPS65941_RTC_START (1)

#define	BOARD_TPS65941_WDT_RST_INT (0)

#define	BOARD_TPS65941_WDT_FAIL_INT (1)

#define	BOARD_TPS65941_WDT_ANSW_ERR (2)

#define	BOARD_TPS65941_WDT_SEQ_ERR (3)

#define	BOARD_TPS65941_WDT_ANSW_ERLY_ERR (4)

#define	BOARD_TPS65941_WDT_TRIG_ERLY_ERR (5)

#define	BOARD_TPS65941_WDT_TIMEOUT_ERR (6)

#define	BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_ERR (7)

#define	BOARD_TPS65941_WDT_ERR_LATCHED (1)

#define	BOARD_TPS65941_WDT_NO_ERR (0)

#define	BOARD_I2C_NUM_OF_BYTES_01 (1U)

Macro Definition Documentation

◆ BOARD_TPS65941_GPIO1_CONF

#define BOARD_TPS65941_GPIO1_CONF (0x31U)

GPIO Register Offsets

◆ BOARD_TPS65941_GPIO2_CONF

#define BOARD_TPS65941_GPIO2_CONF (0x32U)

◆ BOARD_TPS65941_GPIO3_CONF

#define BOARD_TPS65941_GPIO3_CONF (0x33U)

◆ BOARD_TPS65941_GPIO4_CONF

#define BOARD_TPS65941_GPIO4_CONF (0x34U)

◆ BOARD_TPS65941_GPIO5_CONF

#define BOARD_TPS65941_GPIO5_CONF (0x35U)

◆ BOARD_TPS65941_GPIO6_CONF

#define BOARD_TPS65941_GPIO6_CONF (0x36U)

◆ BOARD_TPS65941_GPIO7_CONF

#define BOARD_TPS65941_GPIO7_CONF (0x37U)

◆ BOARD_TPS65941_GPIO8_CONF

#define BOARD_TPS65941_GPIO8_CONF (0x38U)

◆ BOARD_TPS65941_GPIO9_CONF

#define BOARD_TPS65941_GPIO9_CONF (0x39U)

◆ BOARD_TPS65941_GPIO10_CONF

#define BOARD_TPS65941_GPIO10_CONF (0x3AU)

◆ BOARD_TPS65941_GPIO11_CONF

#define BOARD_TPS65941_GPIO11_CONF (0x3BU)

◆ BOARD_TPS65941_NPWRON_CONF

#define BOARD_TPS65941_NPWRON_CONF (0x3CU)

◆ BOARD_TPS65941_GPIO_OUT_1

#define BOARD_TPS65941_GPIO_OUT_1 (0x3DU)

◆ BOARD_TPS65941_GPIO_OUT_2

#define BOARD_TPS65941_GPIO_OUT_2 (0x3EU)

◆ BOARD_TPS65941_GPIO_IN_1

#define BOARD_TPS65941_GPIO_IN_1 (0x3FU)

◆ BOARD_TPS65941_GPIO_IN_2

#define BOARD_TPS65941_GPIO_IN_2 (0x40U)

◆ BOARD_TPS65941_BUCK1_CTRL

#define BOARD_TPS65941_BUCK1_CTRL (0x04U)

BUCK Power resource Register Offsets

◆ BOARD_TPS65941_BUCK2_CTRL

#define BOARD_TPS65941_BUCK2_CTRL (0x06U)

◆ BOARD_TPS65941_BUCK3_CTRL

#define BOARD_TPS65941_BUCK3_CTRL (0x08U)

◆ BOARD_TPS65941_BUCK4_CTRL

#define BOARD_TPS65941_BUCK4_CTRL (0x0AU)

◆ BOARD_TPS65941_BUCK5_CTRL

#define BOARD_TPS65941_BUCK5_CTRL (0x0CU)

◆ BOARD_TPS65941_BUCK1_CONF

#define BOARD_TPS65941_BUCK1_CONF (0x05U)

◆ BOARD_TPS65941_BUCK2_CONF

#define BOARD_TPS65941_BUCK2_CONF (0x07U)

◆ BOARD_TPS65941_BUCK3_CONF

#define BOARD_TPS65941_BUCK3_CONF (0x09U)

◆ BOARD_TPS65941_BUCK4_CONF

#define BOARD_TPS65941_BUCK4_CONF (0x0BU)

◆ BOARD_TPS65941_BUCK5_CONF

#define BOARD_TPS65941_BUCK5_CONF (0x0DU)

◆ BOARD_TPS65941_BUCK1_VOUT_1

#define BOARD_TPS65941_BUCK1_VOUT_1 (0x0EU)

◆ BOARD_TPS65941_BUCK1_VOUT_2

#define BOARD_TPS65941_BUCK1_VOUT_2 (0x0FU)

◆ BOARD_TPS65941_BUCK2_VOUT_1

#define BOARD_TPS65941_BUCK2_VOUT_1 (0x10U)

◆ BOARD_TPS65941_BUCK2_VOUT_2

#define BOARD_TPS65941_BUCK2_VOUT_2 (0x11U)

◆ BOARD_TPS65941_BUCK3_VOUT_1

#define BOARD_TPS65941_BUCK3_VOUT_1 (0x12U)

◆ BOARD_TPS65941_BUCK3_VOUT_2

#define BOARD_TPS65941_BUCK3_VOUT_2 (0x13U)

◆ BOARD_TPS65941_BUCK4_VOUT_1

#define BOARD_TPS65941_BUCK4_VOUT_1 (0x14U)

◆ BOARD_TPS65941_BUCK4_VOUT_2

#define BOARD_TPS65941_BUCK4_VOUT_2 (0x15U)

◆ BOARD_TPS65941_BUCK5_VOUT_1

#define BOARD_TPS65941_BUCK5_VOUT_1 (0x16U)

◆ BOARD_TPS65941_BUCK5_VOUT_2

#define BOARD_TPS65941_BUCK5_VOUT_2 (0x17U)

◆ BOARD_TPS65941_BUCK1_PG_WIN

#define BOARD_TPS65941_BUCK1_PG_WIN (0x18U)

◆ BOARD_TPS65941_BUCK2_PG_WIN

#define BOARD_TPS65941_BUCK2_PG_WIN (0x19U)

◆ BOARD_TPS65941_BUCK3_PG_WIN

#define BOARD_TPS65941_BUCK3_PG_WIN (0x1AU)

◆ BOARD_TPS65941_BUCK4_PG_WIN

#define BOARD_TPS65941_BUCK4_PG_WIN (0x1BU)

◆ BOARD_TPS65941_BUCK5_PG_WIN

#define BOARD_TPS65941_BUCK5_PG_WIN (0x1CU)

◆ BOARD_TPS65941_LDO1_CTRL

#define BOARD_TPS65941_LDO1_CTRL (0x1DU)

LDO Power resource Register Offsets

◆ BOARD_TPS65941_LDO2_CTRL

#define BOARD_TPS65941_LDO2_CTRL (0x1EU)

◆ BOARD_TPS65941_LDO3_CTRL

#define BOARD_TPS65941_LDO3_CTRL (0x1FU)

◆ BOARD_TPS65941_LDO4_CTRL

#define BOARD_TPS65941_LDO4_CTRL (0x20U)

◆ BOARD_TPS65941_LDO1_VOUT

#define BOARD_TPS65941_LDO1_VOUT (0x23U)

◆ BOARD_TPS65941_LDO2_VOUT

#define BOARD_TPS65941_LDO2_VOUT (0x24U)

◆ BOARD_TPS65941_LDO3_VOUT

#define BOARD_TPS65941_LDO3_VOUT (0x25U)

◆ BOARD_TPS65941_LDO4_VOUT

#define BOARD_TPS65941_LDO4_VOUT (0x26U)

◆ BOARD_TPS65941_LDO1_PG_WIN

#define BOARD_TPS65941_LDO1_PG_WIN (0x27U)

◆ BOARD_TPS65941_LDO2_PG_WIN

#define BOARD_TPS65941_LDO2_PG_WIN (0x28U)

◆ BOARD_TPS65941_LDO3_PG_WIN

#define BOARD_TPS65941_LDO3_PG_WIN (0x29U)

◆ BOARD_TPS65941_LDO4_PG_WIN

#define BOARD_TPS65941_LDO4_PG_WIN (0x2AU)

◆ BOARD_TPS65941_VCCA_VMON_CTRL

#define BOARD_TPS65941_VCCA_VMON_CTRL (0x2BU)

VCCA Voltage monitor Register Offsets

◆ BOARD_TPS65941_VCCA_PG_WINDOW

#define BOARD_TPS65941_VCCA_PG_WINDOW (0x2CU)

◆ BOARD_TPS65941_BUCK_MASK

#define BOARD_TPS65941_BUCK_MASK (0x49)

Interrupt Mask Register Offsets

◆ BOARD_TPS65941_LDO_MASK

#define BOARD_TPS65941_LDO_MASK (0x4C)

◆ BOARD_TPS65941_GPIO_MASK

#define BOARD_TPS65941_GPIO_MASK (0x4F)

◆ BOARD_TPS65941_STARTUP_MASK

#define BOARD_TPS65941_STARTUP_MASK (0x52)

◆ BOARD_TPS65941_MISC_WARN_MASK

#define BOARD_TPS65941_MISC_WARN_MASK (0x53)

◆ BOARD_TPS65941_MOD_ERR_MASK

#define BOARD_TPS65941_MOD_ERR_MASK (0x54)

◆ BOARD_TPS65941_FSM_ERR_MASK

#define BOARD_TPS65941_FSM_ERR_MASK (0x56)

◆ BOARD_TPS65941_INT_TOP

#define BOARD_TPS65941_INT_TOP (0x5A)

Interrupt Register Offsets

◆ BOARD_TPS65941_BUCK_INT

#define BOARD_TPS65941_BUCK_INT (0x5C)

◆ BOARD_TPS65941_LDO_VMON_INT

#define BOARD_TPS65941_LDO_VMON_INT (0x60)

◆ BOARD_TPS65941_GPIO_INT

#define BOARD_TPS65941_GPIO_INT (0x63)

◆ BOARD_TPS65941_STARTUP_INT

#define BOARD_TPS65941_STARTUP_INT (0x65)

◆ BOARD_TPS65941_MISC_INT

#define BOARD_TPS65941_MISC_INT (0x66)

◆ BOARD_TPS65941_MOD_ERR_INT

#define BOARD_TPS65941_MOD_ERR_INT (0x67)

◆ BOARD_TPS65941_SEV_ERR_INT

#define BOARD_TPS65941_SEV_ERR_INT (0x68)

◆ BOARD_TPS65941_FSM_ERR_INT

#define BOARD_TPS65941_FSM_ERR_INT (0x69)

◆ BOARD_TPS65941_STAT_MISC

#define BOARD_TPS65941_STAT_MISC (0x74U)

Status Register Offset

◆ BOARD_TPS65941_STAT_MODERATE_ERR

#define BOARD_TPS65941_STAT_MODERATE_ERR (0x75U)

◆ BOARD_TPS65941_STAT_SEVERE_ERR

#define BOARD_TPS65941_STAT_SEVERE_ERR (0x76U)

◆ BOARD_TPS65941_PGOOD_1

#define BOARD_TPS65941_PGOOD_1 (0x78U)

PGOOD Register Offsets

◆ BOARD_TPS65941_PGOOD_2

#define BOARD_TPS65941_PGOOD_2 (0x79U)

◆ BOARD_TPS65941_PGOOD_3

#define BOARD_TPS65941_PGOOD_3 (0x7AU)

◆ BOARD_TPS65941_PGOOD_4

#define BOARD_TPS65941_PGOOD_4 (0x7BU)

◆ BOARD_TPS65941_CONFIG_1

#define BOARD_TPS65941_CONFIG_1 (0x7DU)

TPS65941 Configuration Register Offsets

◆ BOARD_TPS65941_CONFIG_2

#define BOARD_TPS65941_CONFIG_2 (0x7EU)

◆ BOARD_TPS65941_ESM_MCU_START

#define BOARD_TPS65941_ESM_MCU_START (0x8FU)

TPS65941 ESM Register Offsets

◆ BOARD_TPS65941_ESM_MCU_DELAY1

#define BOARD_TPS65941_ESM_MCU_DELAY1 (0x90U)

◆ BOARD_TPS65941_ESM_MCU_DELAY2

#define BOARD_TPS65941_ESM_MCU_DELAY2 (0x91U)

◆ BOARD_TPS65941_ESM_MCU_MODE_CFG

#define BOARD_TPS65941_ESM_MCU_MODE_CFG (0x92U)

◆ BOARD_TPS65941_ESM_MCU_HMAX

#define BOARD_TPS65941_ESM_MCU_HMAX (0x93U)

◆ BOARD_TPS65941_ESM_MCU_HMIN

#define BOARD_TPS65941_ESM_MCU_HMIN (0x94U)

◆ BOARD_TPS65941_ESM_MCU_LMAX

#define BOARD_TPS65941_ESM_MCU_LMAX (0x95U)

◆ BOARD_TPS65941_ESM_MCU_LMIN

#define BOARD_TPS65941_ESM_MCU_LMIN (0x96U)

◆ BOARD_TPS65941_ESM_MCU_ERR_CNT

#define BOARD_TPS65941_ESM_MCU_ERR_CNT (0x97U)

◆ BOARD_TPS65941_ESM_SOC_START

#define BOARD_TPS65941_ESM_SOC_START (0x98U)

◆ BOARD_TPS65941_ESM_SOC_DELAY1

#define BOARD_TPS65941_ESM_SOC_DELAY1 (0x99U)

◆ BOARD_TPS65941_ESM_SOC_DELAY2

#define BOARD_TPS65941_ESM_SOC_DELAY2 (0x9AU)

◆ BOARD_TPS65941_ESM_SOC_MODE_CFG

#define BOARD_TPS65941_ESM_SOC_MODE_CFG (0x9BU)

◆ BOARD_TPS65941_ESM_SOC_HMAX

#define BOARD_TPS65941_ESM_SOC_HMAX (0x9CU)

◆ BOARD_TPS65941_ESM_SOC_HMIN

#define BOARD_TPS65941_ESM_SOC_HMIN (0x9DU)

◆ BOARD_TPS65941_ESM_SOC_LMAX

#define BOARD_TPS65941_ESM_SOC_LMAX (0x9EU)

◆ BOARD_TPS65941_ESM_SOC_LMIN

#define BOARD_TPS65941_ESM_SOC_LMIN (0x9FU)

◆ BOARD_TPS65941_ESM_SOC_ERR_CNT

#define BOARD_TPS65941_ESM_SOC_ERR_CNT (0xA0U)

◆ BOARD_TPS65941_RTC_SECONDS

#define BOARD_TPS65941_RTC_SECONDS (0xB5U)

TPS65941 RTC time and date Register Offsets

◆ BOARD_TPS65941_RTC_MINUTES

#define BOARD_TPS65941_RTC_MINUTES (0xB6U)

◆ BOARD_TPS65941_RTC_HOURS

#define BOARD_TPS65941_RTC_HOURS (0xB7U)

◆ BOARD_TPS65941_RTC_DAYS

#define BOARD_TPS65941_RTC_DAYS (0xB8U)

◆ BOARD_TPS65941_RTC_MONTHS

#define BOARD_TPS65941_RTC_MONTHS (0xB9U)

◆ BOARD_TPS65941_RTC_YEARS

#define BOARD_TPS65941_RTC_YEARS (0xBAU)

◆ BOARD_TPS65941_RTC_WEEKS

#define BOARD_TPS65941_RTC_WEEKS (0xBBU)

◆ BOARD_TPS65941_ALARM_SECONDS

#define BOARD_TPS65941_ALARM_SECONDS (0xBCU)

TPS65941 Alarm time and date Register Offsets

◆ BOARD_TPS65941_ALARM_MINUTES

#define BOARD_TPS65941_ALARM_MINUTES (0xBDU)

◆ BOARD_TPS65941_ALARM_HOURS

#define BOARD_TPS65941_ALARM_HOURS (0xBEU)

◆ BOARD_TPS65941_ALARM_DAYS

#define BOARD_TPS65941_ALARM_DAYS (0xBFU)

◆ BOARD_TPS65941_ALARM_MONTHS

#define BOARD_TPS65941_ALARM_MONTHS (0xC0U)

◆ BOARD_TPS65941_ALARM_YEARS

#define BOARD_TPS65941_ALARM_YEARS (0xC1U)

◆ BOARD_TPS65941_RTC_CTRL_1

#define BOARD_TPS65941_RTC_CTRL_1 (0xC2U)

TPS65941 RTC Register Offsets

◆ BOARD_TPS65941_RTC_CTRL_2

#define BOARD_TPS65941_RTC_CTRL_2 (0xC3U)

◆ BOARD_TPS65941_RTC_STATUS

#define BOARD_TPS65941_RTC_STATUS (0xC4U)

◆ BOARD_TPS65941_RTC_INTR

#define BOARD_TPS65941_RTC_INTR (0xC5U)

◆ BOARD_TPS65941_WDT_ANSW_REG

#define BOARD_TPS65941_WDT_ANSW_REG (0x01U)

TPS65941 WDT Register Offsets

◆ BOARD_TPS65941_WDT_QUES_ANSW_CNT

#define BOARD_TPS65941_WDT_QUES_ANSW_CNT (0x02U)

◆ BOARD_TPS65941_WDT_WIN1_CFG

#define BOARD_TPS65941_WDT_WIN1_CFG (0x03U)

◆ BOARD_TPS65941_WDT_WIN2_CFG

#define BOARD_TPS65941_WDT_WIN2_CFG (0x04U)

◆ BOARD_TPS65941_WDT_LONGWIN_CFG

#define BOARD_TPS65941_WDT_LONGWIN_CFG (0x05U)

◆ BOARD_TPS65941_WDT_MODE_REG

#define BOARD_TPS65941_WDT_MODE_REG (0x06U)

◆ BOARD_TPS65941_WDT_QA_CFG

#define BOARD_TPS65941_WDT_QA_CFG (0x07U)

◆ BOARD_TPS65941_WDT_ERR_STAT

#define BOARD_TPS65941_WDT_ERR_STAT (0x08U)

◆ BOARD_TPS65941_WDT_THR_CFG

#define BOARD_TPS65941_WDT_THR_CFG (0x09U)

◆ BOARD_TPS65941_WDT_FAIL_CNT_REG

#define BOARD_TPS65941_WDT_FAIL_CNT_REG (0x0AU)

◆ BOARD_TPS65941_GPIO_SEL_SHIFT

#define BOARD_TPS65941_GPIO_SEL_SHIFT (0x05U)

GPIO Register bit fields

◆ BOARD_TPS65941_GPIO_DEGLITCH_EN_SHIFT

#define BOARD_TPS65941_GPIO_DEGLITCH_EN_SHIFT (0x04U)

◆ BOARD_TPS65941_GPIO_PU_PD_EN_SHIFT

#define BOARD_TPS65941_GPIO_PU_PD_EN_SHIFT (0x03U)

◆ BOARD_TPS65941_GPIO_PU_SEL_SHIFT

#define BOARD_TPS65941_GPIO_PU_SEL_SHIFT (0x02U)

◆ BOARD_TPS65941_GPIO_OD_SHIFT

#define BOARD_TPS65941_GPIO_OD_SHIFT (0x01U)

◆ BOARD_TPS65941_GPIO_DIR_SHIFT

#define BOARD_TPS65941_GPIO_DIR_SHIFT (0x00U)

◆ BOARD_TPS65941_NPWRON_SEL_SHIFT

#define BOARD_TPS65941_NPWRON_SEL_SHIFT (0x06U)

NPWRON Register bit fields

◆ BOARD_TPS65941_NPWRON_POL_SHIFT

#define BOARD_TPS65941_NPWRON_POL_SHIFT (0x05U)

◆ BOARD_TPS65941_NPWRON_PU_PD_EN_SHIFT

#define BOARD_TPS65941_NPWRON_PU_PD_EN_SHIFT (0x03U)

◆ BOARD_TPS65941_NPWRON_PU_SEL_SHIFT

#define BOARD_TPS65941_NPWRON_PU_SEL_SHIFT (0x02U)

◆ BOARD_TPS65941_NPWRON_OD_SHIFT

#define BOARD_TPS65941_NPWRON_OD_SHIFT (0x00U)

◆ BOARD_TPS65941_GPIO1_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO1_IN_OUT_SHIFT (0x00U)

GPIO IN/OUT Register bit fields

◆ BOARD_TPS65941_GPIO2_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO2_IN_OUT_SHIFT (0x01U)

◆ BOARD_TPS65941_GPIO3_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO3_IN_OUT_SHIFT (0x02U)

◆ BOARD_TPS65941_GPIO4_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO4_IN_OUT_SHIFT (0x03U)

◆ BOARD_TPS65941_GPIO5_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO5_IN_OUT_SHIFT (0x04U)

◆ BOARD_TPS65941_GPIO6_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO6_IN_OUT_SHIFT (0x05U)

◆ BOARD_TPS65941_GPIO7_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO7_IN_OUT_SHIFT (0x06U)

◆ BOARD_TPS65941_GPIO8_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO8_IN_OUT_SHIFT (0x07U)

◆ BOARD_TPS65941_GPIO9_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO9_IN_OUT_SHIFT (0x00U)

◆ BOARD_TPS65941_GPIO10_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO10_IN_OUT_SHIFT (0x01U)

◆ BOARD_TPS65941_GPIO11_IN_OUT_SHIFT

#define BOARD_TPS65941_GPIO11_IN_OUT_SHIFT (0x02U)

◆ BOARD_TPS65941_NPWRON_IN_OUT_SHIFT

#define BOARD_TPS65941_NPWRON_IN_OUT_SHIFT (0x03U)

◆ BOARD_TPS65941_BUCK_VSEL_SHIFT

#define BOARD_TPS65941_BUCK_VSEL_SHIFT (0x03U)

BUCK Power resource bit fields

◆ BOARD_TPS65941_BUCK_EN_SHIFT

#define BOARD_TPS65941_BUCK_EN_SHIFT (0x00U)

◆ BOARD_TPS65941_BUCK_ILIM_SHIFT

#define BOARD_TPS65941_BUCK_ILIM_SHIFT (0x03U)

◆ BOARD_TPS65941_LDO_EN_SHIFT

#define BOARD_TPS65941_LDO_EN_SHIFT (0x00U)

LDO Power resource bit field

◆ BOARD_TPS65941_BUCK_VSET_SHIFT

#define BOARD_TPS65941_BUCK_VSET_SHIFT (0x00U)

BUCK Voltage set bit field

◆ BOARD_TPS65941_LDO_123_VSET_SHIFT

#define BOARD_TPS65941_LDO_123_VSET_SHIFT (0x01U)

LDO Voltage set bit fields

◆ BOARD_TPS65941_LDO4_VSET_SHIFT

#define BOARD_TPS65941_LDO4_VSET_SHIFT (0x00U)

◆ BOARD_TPS65941_PWR_VMON_EN_SHIFT

#define BOARD_TPS65941_PWR_VMON_EN_SHIFT (0x04U)

Power resource voltage monitor set bit field

◆ BOARD_TPS65941_PWR_UV_THR_SHIFT

#define BOARD_TPS65941_PWR_UV_THR_SHIFT (0x03U)

Power resource PG Window set bit fields

◆ BOARD_TPS65941_PWR_OV_THR_SHIFT

#define BOARD_TPS65941_PWR_OV_THR_SHIFT (0x00U)

◆ BOARD_TPS65941_BUCK1_PG_SEL_SHIFT

#define BOARD_TPS65941_BUCK1_PG_SEL_SHIFT (0x00U)

Power resource PGOOD bit fields

◆ BOARD_TPS65941_BUCK2_PG_SEL_SHIFT

#define BOARD_TPS65941_BUCK2_PG_SEL_SHIFT (0x02U)

◆ BOARD_TPS65941_BUCK3_PG_SEL_SHIFT

#define BOARD_TPS65941_BUCK3_PG_SEL_SHIFT (0x04U)

◆ BOARD_TPS65941_BUCK4_PG_SEL_SHIFT

#define BOARD_TPS65941_BUCK4_PG_SEL_SHIFT (0x06U)

◆ BOARD_TPS65941_BUCK5_PG_SEL_SHIFT

#define BOARD_TPS65941_BUCK5_PG_SEL_SHIFT (0x00U)

◆ BOARD_TPS65941_LDO1_PG_SEL_SHIFT

#define BOARD_TPS65941_LDO1_PG_SEL_SHIFT (0x00U)

◆ BOARD_TPS65941_LDO2_PG_SEL_SHIFT

#define BOARD_TPS65941_LDO2_PG_SEL_SHIFT (0x02U)

◆ BOARD_TPS65941_LDO3_PG_SEL_SHIFT

#define BOARD_TPS65941_LDO3_PG_SEL_SHIFT (0x04U)

◆ BOARD_TPS65941_LDO4_PG_SEL_SHIFT

#define BOARD_TPS65941_LDO4_PG_SEL_SHIFT (0x06U)

◆ BOARD_TPS65941_VCCA_VMON_EN_SHIFT

#define BOARD_TPS65941_VCCA_VMON_EN_SHIFT (0x00U)

VCCA voltage monitor bit fields

◆ BOARD_TPS65941_VCCA_PG_SET_SHIFT

#define BOARD_TPS65941_VCCA_PG_SET_SHIFT (0x06U)

◆ BOARD_TPS65941_VCCA_UV_THR_SHIFT

#define BOARD_TPS65941_VCCA_UV_THR_SHIFT (0x03U)

◆ BOARD_TPS65941_VCCA_OV_THR_SHIFT

#define BOARD_TPS65941_VCCA_OV_THR_SHIFT (0x00U)

◆ BOARD_TPS65941_TWARN_STAT_SHIFT

#define BOARD_TPS65941_TWARN_STAT_SHIFT (0x03U)

Status register bit fields

◆ BOARD_TPS65941_TSD_ORD_STAT_SHIFT

#define BOARD_TPS65941_TSD_ORD_STAT_SHIFT (0x00U)

◆ BOARD_TPS65941_TSD_IMM_STAT_SHIFT

#define BOARD_TPS65941_TSD_IMM_STAT_SHIFT (0x00U)

◆ BOARD_TPS65941_PGOOD_WINDOW_SHIFT

#define BOARD_TPS65941_PGOOD_WINDOW_SHIFT (0x07U)

PGOOD signal bit fields

◆ BOARD_TPS65941_PGOOD_POL_SHIFT

#define BOARD_TPS65941_PGOOD_POL_SHIFT (0x06U)

◆ BOARD_TPS65941_PGOOD_NRSTOUT_SOC_SHIFT

#define BOARD_TPS65941_PGOOD_NRSTOUT_SOC_SHIFT (0x05U)

◆ BOARD_TPS65941_PGOOD_NRSTOUT_SHIFT

#define BOARD_TPS65941_PGOOD_NRSTOUT_SHIFT (0x04U)

◆ BOARD_TPS65941_PGOOD_TDIE_WARN_SHIFT

#define BOARD_TPS65941_PGOOD_TDIE_WARN_SHIFT (0x03U)

◆ BOARD_TPS65941_PGOOD_VCCA_SEL_SHIFT

#define BOARD_TPS65941_PGOOD_VCCA_SEL_SHIFT (0x00U)

◆ BOARD_TPS65941_TWARN_LVL_SHIFT

#define BOARD_TPS65941_TWARN_LVL_SHIFT (0x00U)

Thermal threshold value bit fields

◆ BOARD_TPS65941_ESM_START_SHIFT

#define BOARD_TPS65941_ESM_START_SHIFT (0x00U)

ESM MCU and SOC bit fields

◆ BOARD_TPS65941_ESM_DLY1_SHIFT

#define BOARD_TPS65941_ESM_DLY1_SHIFT (0x00U)

◆ BOARD_TPS65941_ESM_DLY2_SHIFT

#define BOARD_TPS65941_ESM_DLY2_SHIFT (0x00U)

◆ BOARD_TPS65941_ESM_MODE_SHIFT

#define BOARD_TPS65941_ESM_MODE_SHIFT (0x07U)

◆ BOARD_TPS65941_ESM_EN_SHIFT

#define BOARD_TPS65941_ESM_EN_SHIFT (0x06U)

◆ BOARD_TPS65941_ESM_ERR_THR_SHIFT

#define BOARD_TPS65941_ESM_ERR_THR_SHIFT (0x00U)

◆ BOARD_TPS65941_ESM_HMAX_SHIFT

#define BOARD_TPS65941_ESM_HMAX_SHIFT (0x00U)

◆ BOARD_TPS65941_ESM_HMIN_SHIFT

#define BOARD_TPS65941_ESM_HMIN_SHIFT (0x00U)

◆ BOARD_TPS65941_ESM_LMAX_SHIFT

#define BOARD_TPS65941_ESM_LMAX_SHIFT (0x00U)

◆ BOARD_TPS65941_ESM_LMIN_SHIFT

#define BOARD_TPS65941_ESM_LMIN_SHIFT (0x00U)

◆ BOARD_TPS65941_ESM_ERR_CNT_SHIFT

#define BOARD_TPS65941_ESM_ERR_CNT_SHIFT (0x00U)

◆ BOARD_TPS65941_RTC_ALRM_SEC_1_SHIFT

#define BOARD_TPS65941_RTC_ALRM_SEC_1_SHIFT (0x04U)

RTC and alarm time and date bit fields

◆ BOARD_TPS65941_RTC_ALRM_SEC_0_SHIFT

#define BOARD_TPS65941_RTC_ALRM_SEC_0_SHIFT (0x00U)

◆ BOARD_TPS65941_RTC_ALRM_MIN_1_SHIFT

#define BOARD_TPS65941_RTC_ALRM_MIN_1_SHIFT (0x04U)

◆ BOARD_TPS65941_RTC_ALRM_MIN_0_SHIFT

#define BOARD_TPS65941_RTC_ALRM_MIN_0_SHIFT (0x00U)

◆ BOARD_TPS65941_RTC_ALRM_AM_PM_SHIFT

#define BOARD_TPS65941_RTC_ALRM_AM_PM_SHIFT (0x07U)

◆ BOARD_TPS65941_RTC_ALRM_HR_1_SHIFT

#define BOARD_TPS65941_RTC_ALRM_HR_1_SHIFT (0x04U)

◆ BOARD_TPS65941_RTC_ALRM_HR_0_SHIFT

#define BOARD_TPS65941_RTC_ALRM_HR_0_SHIFT (0x00U)

◆ BOARD_TPS65941_RTC_ALRM_DAY_1_SHIFT

#define BOARD_TPS65941_RTC_ALRM_DAY_1_SHIFT (0x04U)

◆ BOARD_TPS65941_RTC_ALRM_DAY_0_SHIFT

#define BOARD_TPS65941_RTC_ALRM_DAY_0_SHIFT (0x00U)

◆ BOARD_TPS65941_RTC_ALRM_MON_1_SHIFT

#define BOARD_TPS65941_RTC_ALRM_MON_1_SHIFT (0x04U)

◆ BOARD_TPS65941_RTC_ALRM_MON_0_SHIFT

#define BOARD_TPS65941_RTC_ALRM_MON_0_SHIFT (0x00U)

◆ BOARD_TPS65941_RTC_ALRM_YR_1_SHIFT

#define BOARD_TPS65941_RTC_ALRM_YR_1_SHIFT (0x04U)

◆ BOARD_TPS65941_RTC_ALRM_YR_0_SHIFT

#define BOARD_TPS65941_RTC_ALRM_YR_0_SHIFT (0x00U)

◆ BOARD_TPS65941_RTC_WEEK_SHIFT

#define BOARD_TPS65941_RTC_WEEK_SHIFT (0x00U)

◆ BOARD_TPS65941_RTC_REG_OPT_SHIFT

#define BOARD_TPS65941_RTC_REG_OPT_SHIFT (0x07U)

RTC CTRL bit fields

◆ BOARD_TPS65941_GET_TIME_SHIFT

#define BOARD_TPS65941_GET_TIME_SHIFT (0x06U)

◆ BOARD_TPS65941_HOUR_MODE_SHIFT

#define BOARD_TPS65941_HOUR_MODE_SHIFT (0x03U)

◆ BOARD_TPS65941_ROUND_30S_SHIFT

#define BOARD_TPS65941_ROUND_30S_SHIFT (0x01U)

◆ BOARD_TPS65941_STOP_RTC_SHIFT

#define BOARD_TPS65941_STOP_RTC_SHIFT (0x00U)

◆ BOARD_TPS65941_ALRM_STAT_SHIFT

#define BOARD_TPS65941_ALRM_STAT_SHIFT (0x06U)

RTC Status bit fields

◆ BOARD_TPS65941_TIMER_STAT_SHIFT

#define BOARD_TPS65941_TIMER_STAT_SHIFT (0x05U)

◆ BOARD_TPS65941_RUN_SHIFT

#define BOARD_TPS65941_RUN_SHIFT (0x01U)

◆ BOARD_TPS65941_ALARM_INTR_SHIFT

#define BOARD_TPS65941_ALARM_INTR_SHIFT (0x03U)

RTC Interrupt bit fields

◆ BOARD_TPS65941_TIMER_INTR_SHIFT

#define BOARD_TPS65941_TIMER_INTR_SHIFT (0x02U)

◆ BOARD_TPS65941_TIMER_PERIOD_SHIFT

#define BOARD_TPS65941_TIMER_PERIOD_SHIFT (0x00U)

RTC Timer periods bit fields

◆ BOARD_TPS65941_WDT_ANSW_SHIFT

#define BOARD_TPS65941_WDT_ANSW_SHIFT (0x00U)

WDT configuration bit fields

◆ BOARD_TPS65941_WDT_ANSW_CNT_SHIFT

#define BOARD_TPS65941_WDT_ANSW_CNT_SHIFT (0x04U)

◆ BOARD_TPS65941_WDT_QUES_SHIFT

#define BOARD_TPS65941_WDT_QUES_SHIFT (0x00U)

◆ BOARD_TPS65941_WDT_WIN1_CFG_SHIFT

#define BOARD_TPS65941_WDT_WIN1_CFG_SHIFT (0x00U)

◆ BOARD_TPS65941_WDT_WIN2_CFG_SHIFT

#define BOARD_TPS65941_WDT_WIN2_CFG_SHIFT (0x00U)

◆ BOARD_TPS65941_WDT_LONGWIN_CFG_SHIFT

#define BOARD_TPS65941_WDT_LONGWIN_CFG_SHIFT (0x00U)

◆ BOARD_TPS65941_WDT_MODE_SHIFT

#define BOARD_TPS65941_WDT_MODE_SHIFT (0x01U)

◆ BOARD_TPS65941_WDT_LONGWIN_RET_SHIFT

#define BOARD_TPS65941_WDT_LONGWIN_RET_SHIFT (0x00U)

◆ BOARD_TPS65941_WDT_RST_STAT_SHIFT

#define BOARD_TPS65941_WDT_RST_STAT_SHIFT (0x07U)

WDT Error status bit fields

◆ BOARD_TPS65941_WDT_FAIL_STAT_SHIFT

#define BOARD_TPS65941_WDT_FAIL_STAT_SHIFT (0x06U)

◆ BOARD_TPS65941_WDT_ANSW_ERR_SHIFT

#define BOARD_TPS65941_WDT_ANSW_ERR_SHIFT (0x05U)

◆ BOARD_TPS65941_WDT_SEQ_ERR_SHIFT

#define BOARD_TPS65941_WDT_SEQ_ERR_SHIFT (0x04U)

◆ BOARD_TPS65941_WDT_ANSW_ERLY_SHIFT

#define BOARD_TPS65941_WDT_ANSW_ERLY_SHIFT (0x03U)

◆ BOARD_TPS65941_WDT_TRIG_ERLY_SHIFT

#define BOARD_TPS65941_WDT_TRIG_ERLY_SHIFT (0x02U)

◆ BOARD_TPS65941_WDT_TIMEOUT_SHIFT

#define BOARD_TPS65941_WDT_TIMEOUT_SHIFT (0x01U)

◆ BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_SHIFT

#define BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_SHIFT (0x00U)

◆ BOARD_TPS65941_WDT_RST_EN_SHIFT

#define BOARD_TPS65941_WDT_RST_EN_SHIFT (0x07U)

WDT Threshold bit fields

◆ BOARD_TPS65941_WDT_EN_SHIFT

#define BOARD_TPS65941_WDT_EN_SHIFT (0x06U)

◆ BOARD_TPS65941_WDT_FAIL_THR_SHIFT

#define BOARD_TPS65941_WDT_FAIL_THR_SHIFT (0x03U)

◆ BOARD_TPS65941_WDT_RST_THR_SHIFT

#define BOARD_TPS65941_WDT_RST_THR_SHIFT (0x00U)

◆ BOARD_TPS65941_WDT_BAD_EVT_SHIFT

#define BOARD_TPS65941_WDT_BAD_EVT_SHIFT (0x06U)

WDT Fail count bit fields

◆ BOARD_TPS65941_WDT_FIRST_OK_SHIFT

#define BOARD_TPS65941_WDT_FIRST_OK_SHIFT (0x05U)

◆ BOARD_TPS65941_WDT_FAIL_CNT_SHIFT

#define BOARD_TPS65941_WDT_FAIL_CNT_SHIFT (0x00U)

◆ BOARD_TPS65941_GPIO_SEL_BIT_MASK

#define BOARD_TPS65941_GPIO_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_SEL_SHIFT)

GPIO Register bit mask

◆ BOARD_TPS65941_GPIO_DEGLITCH_EN_BIT_MASK

#define BOARD_TPS65941_GPIO_DEGLITCH_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_DEGLITCH_EN_SHIFT)

◆ BOARD_TPS65941_GPIO_PU_PD_EN_BIT_MASK

#define BOARD_TPS65941_GPIO_PU_PD_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_PU_PD_EN_SHIFT)

◆ BOARD_TPS65941_GPIO_PU_SEL_BIT_MASK

#define BOARD_TPS65941_GPIO_PU_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_PU_SEL_SHIFT)

◆ BOARD_TPS65941_GPIO_OD_BIT_MASK

#define BOARD_TPS65941_GPIO_OD_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_OD_SHIFT)

◆ BOARD_TPS65941_GPIO_DIR_BIT_MASK

#define BOARD_TPS65941_GPIO_DIR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_DIR_SHIFT)

◆ BOARD_TPS65941_NPWRON_SEL_BIT_MASK

#define BOARD_TPS65941_NPWRON_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_SEL_SHIFT)

NPWRON Register bit mask

◆ BOARD_TPS65941_NPWRON_POL_BIT_MASK

#define BOARD_TPS65941_NPWRON_POL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_POL_SHIFT)

◆ BOARD_TPS65941_NPWRON_PU_PD_EN_BIT_MASK

#define BOARD_TPS65941_NPWRON_PU_PD_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_PU_PD_EN_SHIFT)

◆ BOARD_TPS65941_NPWRON_PU_SEL_BIT_MASK

#define BOARD_TPS65941_NPWRON_PU_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_PU_SEL_SHIFT)

◆ BOARD_TPS65941_NPWRON_OD_BIT_MASK

#define BOARD_TPS65941_NPWRON_OD_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_OD_SHIFT)

◆ BOARD_TPS65941_GPIO1_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO1_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO1_IN_OUT_SHIFT)

GPIO IN/OUT Register bit mask

◆ BOARD_TPS65941_GPIO2_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO2_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO2_IN_OUT_SHIFT)

◆ BOARD_TPS65941_GPIO3_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO3_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO3_IN_OUT_SHIFT)

◆ BOARD_TPS65941_GPIO4_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO4_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO4_IN_OUT_SHIFT)

◆ BOARD_TPS65941_GPIO5_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO5_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO5_IN_OUT_SHIFT)

◆ BOARD_TPS65941_GPIO6_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO6_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO6_IN_OUT_SHIFT)

◆ BOARD_TPS65941_GPIO7_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO7_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO7_IN_OUT_SHIFT)

◆ BOARD_TPS65941_GPIO8_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO8_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO8_IN_OUT_SHIFT)

◆ BOARD_TPS65941_GPIO9_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO9_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO9_IN_OUT_SHIFT)

◆ BOARD_TPS65941_GPIO10_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO10_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO10_IN_OUT_SHIFT)

◆ BOARD_TPS65941_GPIO11_IN_OUT_BIT_MASK

#define BOARD_TPS65941_GPIO11_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO11_IN_OUT_SHIFT)

◆ BOARD_TPS65941_NPWRON_IN_OUT_BIT_MASK

#define BOARD_TPS65941_NPWRON_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_IN_OUT_SHIFT)

◆ BOARD_TPS65941_BUCK_VSEL_BIT_MASK

#define BOARD_TPS65941_BUCK_VSEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_BUCK_VSEL_SHIFT)

BUCK Power resource bit mask

◆ BOARD_TPS65941_BUCK_EN_BIT_MASK

#define BOARD_TPS65941_BUCK_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_BUCK_EN_SHIFT)

◆ BOARD_TPS65941_BUCK_ILIM_BIT_MASK

#define BOARD_TPS65941_BUCK_ILIM_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_BUCK_ILIM_SHIFT)

◆ BOARD_TPS65941_LDO_EN_BIT_MASK

#define BOARD_TPS65941_LDO_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_LDO_EN_SHIFT)

LDO Power resource bit mask

◆ BOARD_TPS65941_BUCK_VSET_BIT_MASK

#define BOARD_TPS65941_BUCK_VSET_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_BUCK_VSET_SHIFT)

BUCK Voltage set bit mask

◆ BOARD_TPS65941_LDO_123_VSET_BIT_MASK

#define BOARD_TPS65941_LDO_123_VSET_BIT_MASK (uint8_t)(0x3F << BOARD_TPS65941_LDO_123_VSET_SHIFT)

LDO Voltage set bit mask

◆ BOARD_TPS65941_LDO4_VSET_BIT_MASK

#define BOARD_TPS65941_LDO4_VSET_BIT_MASK (uint8_t)(0x3F << BOARD_TPS65941_LDO4_VSET_SHIFT)

◆ BOARD_TPS65941_PWR_VMON_EN_BIT_MASK

#define BOARD_TPS65941_PWR_VMON_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PWR_VMON_EN_SHIFT)

Power resource voltage monitor set bit mask

◆ BOARD_TPS65941_PWR_UV_THR_BIT_MASK

#define BOARD_TPS65941_PWR_UV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_PWR_UV_THR_SHIFT)

Power resource PG Window set bit mask

◆ BOARD_TPS65941_PWR_OV_THR_BIT_MASK

#define BOARD_TPS65941_PWR_OV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_PWR_OV_THR_SHIFT)

◆ BOARD_TPS65941_BUCK1_PG_SEL_BIT_MASK

#define BOARD_TPS65941_BUCK1_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK1_PG_SEL_SHIFT)

Voltage monitor set bit mask

◆ BOARD_TPS65941_BUCK2_PG_SEL_BIT_MASK

#define BOARD_TPS65941_BUCK2_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK2_PG_SEL_SHIFT)

◆ BOARD_TPS65941_BUCK3_PG_SEL_BIT_MASK

#define BOARD_TPS65941_BUCK3_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK3_PG_SEL_SHIFT)

◆ BOARD_TPS65941_BUCK4_PG_SEL_BIT_MASK

#define BOARD_TPS65941_BUCK4_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK4_PG_SEL_SHIFT)

◆ BOARD_TPS65941_BUCK5_PG_SEL_BIT_MASK

#define BOARD_TPS65941_BUCK5_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK5_PG_SEL_SHIFT)

◆ BOARD_TPS65941_LDO1_PG_SEL_BIT_MASK

#define BOARD_TPS65941_LDO1_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO1_PG_SEL_SHIFT)

◆ BOARD_TPS65941_LDO2_PG_SEL_BIT_MASK

#define BOARD_TPS65941_LDO2_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO2_PG_SEL_SHIFT)

◆ BOARD_TPS65941_LDO3_PG_SEL_BIT_MASK

#define BOARD_TPS65941_LDO3_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO3_PG_SEL_SHIFT)

◆ BOARD_TPS65941_LDO4_PG_SEL_BIT_MASK

#define BOARD_TPS65941_LDO4_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO4_PG_SEL_SHIFT)

◆ BOARD_TPS65941_VCCA_VMON_EN_BIT_MASK

#define BOARD_TPS65941_VCCA_VMON_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_VCCA_VMON_EN_SHIFT)

VCCA voltage monitor set bit mask

◆ BOARD_TPS65941_VCCA_PG_SET_BIT_MASK

#define BOARD_TPS65941_VCCA_PG_SET_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_VCCA_PG_SET_SHIFT)

◆ BOARD_TPS65941_VCCA_UV_THR_BIT_MASK

#define BOARD_TPS65941_VCCA_UV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_VCCA_UV_THR_SHIFT)

◆ BOARD_TPS65941_VCCA_OV_THR_BIT_MASK

#define BOARD_TPS65941_VCCA_OV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_VCCA_OV_THR_SHIFT)

◆ BOARD_TPS65941_TWARN_STAT_BIT_MASK

#define BOARD_TPS65941_TWARN_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TWARN_STAT_SHIFT)

Status register bit mask

◆ BOARD_TPS65941_TSD_ORD_STAT_BIT_MASK

#define BOARD_TPS65941_TSD_ORD_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TSD_ORD_STAT_SHIFT)

◆ BOARD_TPS65941_TSD_IMM_STAT_BIT_MASK

#define BOARD_TPS65941_TSD_IMM_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TSD_IMM_STAT_SHIFT)

◆ BOARD_TPS65941_PGOOD_WINDOW_BIT_MASK

#define BOARD_TPS65941_PGOOD_WINDOW_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_WINDOW_SHIFT)

PGOOD signal bit mask

◆ BOARD_TPS65941_PGOOD_POL_BIT_MASK

#define BOARD_TPS65941_PGOOD_POL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_POL_SHIFT)

◆ BOARD_TPS65941_PGOOD_NRSTOUT_SOC_BIT_MASK

#define BOARD_TPS65941_PGOOD_NRSTOUT_SOC_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_NRSTOUT_SOC_SHIFT)

◆ BOARD_TPS65941_PGOOD_NRSTOUT_BIT_MASK

#define BOARD_TPS65941_PGOOD_NRSTOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_NRSTOUT_SHIFT)

◆ BOARD_TPS65941_PGOOD_TDIE_WARN_BIT_MASK

#define BOARD_TPS65941_PGOOD_TDIE_WARN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_TDIE_WARN_SHIFT)

◆ BOARD_TPS65941_PGOOD_VCCA_SEL_BIT_MASK

#define BOARD_TPS65941_PGOOD_VCCA_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_VCCA_SEL_SHIFT)

◆ BOARD_TPS65941_TWARN_LVL_BIT_MASK

#define BOARD_TPS65941_TWARN_LVL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TWARN_LVL_SHIFT)

Thermal threshold value bit mask

◆ BOARD_TPS65941_ESM_START_BIT_MASK

#define BOARD_TPS65941_ESM_START_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_START_SHIFT)

ESM bit mask

◆ BOARD_TPS65941_ESM_DLY1_BIT_MASK

#define BOARD_TPS65941_ESM_DLY1_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_DLY1_SHIFT)

◆ BOARD_TPS65941_ESM_DLY2_BIT_MASK

#define BOARD_TPS65941_ESM_DLY2_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_DLY2_SHIFT)

◆ BOARD_TPS65941_ESM_MODE_BIT_MASK

#define BOARD_TPS65941_ESM_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_MODE_SHIFT)

◆ BOARD_TPS65941_ESM_EN_BIT_MASK

#define BOARD_TPS65941_ESM_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_EN_SHIFT)

◆ BOARD_TPS65941_ESM_ERR_THR_BIT_MASK

#define BOARD_TPS65941_ESM_ERR_THR_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_ESM_ERR_THR_SHIFT)

◆ BOARD_TPS65941_ESM_HMAX_BIT_MASK

#define BOARD_TPS65941_ESM_HMAX_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_HMAX_SHIFT)

◆ BOARD_TPS65941_ESM_HMIN_BIT_MASK

#define BOARD_TPS65941_ESM_HMIN_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_HMIN_SHIFT)

◆ BOARD_TPS65941_ESM_LMAX_BIT_MASK

#define BOARD_TPS65941_ESM_LMAX_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_LMAX_SHIFT)

◆ BOARD_TPS65941_ESM_LMIN_BIT_MASK

#define BOARD_TPS65941_ESM_LMIN_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_LMIN_SHIFT)

◆ BOARD_TPS65941_ESM_ERR_CNT_BIT_MASK

#define BOARD_TPS65941_ESM_ERR_CNT_BIT_MASK (uint8_t)(0x1F << BOARD_TPS65941_ESM_ERR_CNT_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_SEC_1_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_SEC_1_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_ALRM_SEC_1_SHIFT)

RTC and alarm time and date bit mask

◆ BOARD_TPS65941_RTC_ALRM_SEC_0_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_SEC_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_SEC_0_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_MIN_1_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_MIN_1_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_ALRM_MIN_1_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_MIN_0_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_MIN_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_MIN_0_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_AM_PM_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_AM_PM_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_ALRM_AM_PM_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_HR_1_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_HR_1_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_RTC_ALRM_HR_1_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_HR_0_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_HR_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_HR_0_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_DAY_1_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_DAY_1_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_RTC_ALRM_DAY_1_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_DAY_0_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_DAY_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_DAY_0_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_MON_1_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_MON_1_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_ALRM_MON_1_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_MON_0_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_MON_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_MON_0_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_YR_1_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_YR_1_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_YR_1_SHIFT)

◆ BOARD_TPS65941_RTC_ALRM_YR_0_BIT_MASK

#define BOARD_TPS65941_RTC_ALRM_YR_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_YR_0_SHIFT)

◆ BOARD_TPS65941_RTC_WEEK_BIT_MASK

#define BOARD_TPS65941_RTC_WEEK_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_WEEK_SHIFT)

◆ BOARD_TPS65941_RTC_REG_OPT_BIT_MASK

#define BOARD_TPS65941_RTC_REG_OPT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_REG_OPT_SHIFT)

RTC CTRL bit mask

◆ BOARD_TPS65941_GET_TIME_BIT_MASK

#define BOARD_TPS65941_GET_TIME_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GET_TIME_SHIFT)

◆ BOARD_TPS65941_HOUR_MODE_BIT_MASK

#define BOARD_TPS65941_HOUR_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_HOUR_MODE_SHIFT)

◆ BOARD_TPS65941_ROUND_30S_BIT_MASK

#define BOARD_TPS65941_ROUND_30S_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ROUND_30S_SHIFT)

◆ BOARD_TPS65941_STOP_RTC_BIT_MASK

#define BOARD_TPS65941_STOP_RTC_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_STOP_RTC_SHIFT)

◆ BOARD_TPS65941_ALRM_STAT_BIT_MASK

#define BOARD_TPS65941_ALRM_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ALRM_STAT_SHIFT)

RTC Status bit mask

◆ BOARD_TPS65941_TIMER_STAT_BIT_MASK

#define BOARD_TPS65941_TIMER_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TIMER_STAT_SHIFT)

◆ BOARD_TPS65941_RUN_BIT_MASK

#define BOARD_TPS65941_RUN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RUN_SHIFT)

◆ BOARD_TPS65941_ALARM_INTR_BIT_MASK

#define BOARD_TPS65941_ALARM_INTR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ALARM_INTR_SHIFT)

RTC Interrupt bit mask

◆ BOARD_TPS65941_TIMER_INTR_BIT_MASK

#define BOARD_TPS65941_TIMER_INTR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TIMER_INTR_SHIFT)

◆ BOARD_TPS65941_TIMER_PERIOD_BIT_MASK

#define BOARD_TPS65941_TIMER_PERIOD_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_TIMER_PERIOD_SHIFT)

RTC Timer period bit mask

◆ BOARD_TPS65941_WDT_ANSW_BIT_MASK

#define BOARD_TPS65941_WDT_ANSW_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_WDT_ANSW_SHIFT)

WDT configuration bit fields

◆ BOARD_TPS65941_WDT_ANSW_CNT_BIT_MASK

#define BOARD_TPS65941_WDT_ANSW_CNT_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_WDT_ANSW_CNT_SHIFT)

◆ BOARD_TPS65941_WDT_QUES_BIT_MASK

#define BOARD_TPS65941_WDT_QUES_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_WDT_QUES_SHIFT)

◆ BOARD_TPS65941_WDT_WIN1_CFG_BIT_MASK

#define BOARD_TPS65941_WDT_WIN1_CFG_BIT_MASK (uint8_t)(0x7F << BOARD_TPS65941_WDT_WIN1_CFG_SHIFT)

◆ BOARD_TPS65941_WDT_WIN2_CFG_BIT_MASK

#define BOARD_TPS65941_WDT_WIN2_CFG_BIT_MASK (uint8_t)(0x7F << BOARD_TPS65941_WDT_WIN2_CFG_SHIFT)

◆ BOARD_TPS65941_WDT_LONGWIN_CFG_BIT_MASK

#define BOARD_TPS65941_WDT_LONGWIN_CFG_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_WDT_LONGWIN_CFG_SHIFT)

◆ BOARD_TPS65941_WDT_MODE_BIT_MASK

#define BOARD_TPS65941_WDT_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_MODE_SHIFT)

◆ BOARD_TPS65941_WDT_LONGWIN_RET_BIT_MASK

#define BOARD_TPS65941_WDT_LONGWIN_RET_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_LONGWIN_RET_SHIFT)

◆ BOARD_TPS65941_WDT_RST_STAT_BIT_MASK

#define BOARD_TPS65941_WDT_RST_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_RST_STAT_SHIFT)

WDT Error status bit fields

◆ BOARD_TPS65941_WDT_FAIL_STAT_BIT_MASK

#define BOARD_TPS65941_WDT_FAIL_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FAIL_STAT_SHIFT)

◆ BOARD_TPS65941_WDT_ANSW_ERR_BIT_MASK

#define BOARD_TPS65941_WDT_ANSW_ERR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_ANSW_ERR_SHIFT)

◆ BOARD_TPS65941_WDT_SEQ_ERR_BIT_MASK

#define BOARD_TPS65941_WDT_SEQ_ERR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_SEQ_ERR_SHIFT)

◆ BOARD_TPS65941_WDT_ANSW_ERLY_BIT_MASK

#define BOARD_TPS65941_WDT_ANSW_ERLY_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_ANSW_ERLY_SHIFT)

◆ BOARD_TPS65941_WDT_TRIG_ERLY_BIT_MASK

#define BOARD_TPS65941_WDT_TRIG_ERLY_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_TRIG_ERLY_SHIFT)

◆ BOARD_TPS65941_WDT_TIMEOUT_BIT_MASK

#define BOARD_TPS65941_WDT_TIMEOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_TIMEOUT_SHIFT)

◆ BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_BIT_MASK

#define BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_SHIFT)

◆ BOARD_TPS65941_WDT_RST_EN_BIT_MASK

#define BOARD_TPS65941_WDT_RST_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_RST_EN_SHIFT)

WDT Threshold bit fields

◆ BOARD_TPS65941_WDT_EN_BIT_MASK

#define BOARD_TPS65941_WDT_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_EN_SHIFT)

◆ BOARD_TPS65941_WDT_FAIL_THR_BIT_MASK

#define BOARD_TPS65941_WDT_FAIL_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_WDT_FAIL_THR_SHIFT)

◆ BOARD_TPS65941_WDT_RST_THR_BIT_MASK

#define BOARD_TPS65941_WDT_RST_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_WDT_RST_THR_SHIFT)

◆ BOARD_TPS65941_WDT_BAD_EVT_BIT_MASK

#define BOARD_TPS65941_WDT_BAD_EVT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_BAD_EVT_SHIFT)

WDT Fail count bit fields

◆ BOARD_TPS65941_WDT_FIRST_OK_BIT_MASK

#define BOARD_TPS65941_WDT_FIRST_OK_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FIRST_OK_SHIFT)

◆ BOARD_TPS65941_WDT_FAIL_CNT_BIT_MASK

#define BOARD_TPS65941_WDT_FAIL_CNT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FAIL_CNT_SHIFT)

◆ BOARD_TPS65941_DISABLE

#define BOARD_TPS65941_DISABLE (0U)

GPIO functionality enable/disable

◆ BOARD_TPS65941_ENABLE

#define BOARD_TPS65941_ENABLE (1U)

◆ BOARD_TPS65941_PULLUP_DOWN

#define BOARD_TPS65941_PULLUP_DOWN (0U)

GPIO type

◆ BOARD_TPS65941_OPEN_DRAIN

#define BOARD_TPS65941_OPEN_DRAIN (1U)

◆ BOARD_TPS65941_GPIO_LOW

#define BOARD_TPS65941_GPIO_LOW (0U)

GPIO signal level

◆ BOARD_TPS65941_GPIO_HIGH

#define BOARD_TPS65941_GPIO_HIGH (1U)

◆ BOARD_TPS65941_GPIO_DIR_IN

#define BOARD_TPS65941_GPIO_DIR_IN (0U)

GPIO Direction

◆ BOARD_TPS65941_GPIO_DIR_OUT

#define BOARD_TPS65941_GPIO_DIR_OUT (1U)

◆ BOARD_TPS65941_GPIO_MODE

#define BOARD_TPS65941_GPIO_MODE (0x0U)

◆ BOARD_TPS65941_GPIO_PIN_MAX

#define BOARD_TPS65941_GPIO_PIN_MAX (11U)

◆ BOARD_TPS65941_NPWRON_PIN

#define BOARD_TPS65941_NPWRON_PIN (0)

◆ BOARD_TPS65941_BUCK1_RESOURCE

#define BOARD_TPS65941_BUCK1_RESOURCE (0U)

TPS65941 Power resource

◆ BOARD_TPS65941_BUCK2_RESOURCE

#define BOARD_TPS65941_BUCK2_RESOURCE (1U)

◆ BOARD_TPS65941_BUCK3_RESOURCE

#define BOARD_TPS65941_BUCK3_RESOURCE (2U)

◆ BOARD_TPS65941_BUCK4_RESOURCE

#define BOARD_TPS65941_BUCK4_RESOURCE (3U)

◆ BOARD_TPS65941_BUCK5_RESOURCE

#define BOARD_TPS65941_BUCK5_RESOURCE (4U)

◆ BOARD_TPS65941_LDO1_RESOURCE

#define BOARD_TPS65941_LDO1_RESOURCE (5U)

◆ BOARD_TPS65941_LDO2_RESOURCE

#define BOARD_TPS65941_LDO2_RESOURCE (6U)

◆ BOARD_TPS65941_LDO3_RESOURCE

#define BOARD_TPS65941_LDO3_RESOURCE (7U)

◆ BOARD_TPS65941_LDO4_RESOURCE

#define BOARD_TPS65941_LDO4_RESOURCE (8U)

◆ BOARD_TPS65941_INTR_TYPE_BUCK_ERR

#define BOARD_TPS65941_INTR_TYPE_BUCK_ERR (0U)

Interrupt type

◆ BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR

#define BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR (1U)

◆ BOARD_TPS65941_INTR_TYPE_SEVERE_ERR

#define BOARD_TPS65941_INTR_TYPE_SEVERE_ERR (2U)

◆ BOARD_TPS65941_INTR_TYPE_MODERATE_ERR

#define BOARD_TPS65941_INTR_TYPE_MODERATE_ERR (3U)

◆ BOARD_TPS65941_INTR_TYPE_MISC_WARN

#define BOARD_TPS65941_INTR_TYPE_MISC_WARN (4U)

◆ BOARD_TPS65941_INTR_TYPE_STARTUP_SRC

#define BOARD_TPS65941_INTR_TYPE_STARTUP_SRC (5U)

◆ BOARD_TPS65941_INTR_TYPE_GPIO

#define BOARD_TPS65941_INTR_TYPE_GPIO (6U)

◆ BOARD_TPS65941_INTR_TYPE_FSM_ERR

#define BOARD_TPS65941_INTR_TYPE_FSM_ERR (7U)

◆ BOARD_TPS65941_INTR_ID_BUCK1_OV

#define BOARD_TPS65941_INTR_ID_BUCK1_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x00U)

Interrupt IDs

◆ BOARD_TPS65941_INTR_ID_BUCK1_UV

#define BOARD_TPS65941_INTR_ID_BUCK1_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x01U)

◆ BOARD_TPS65941_INTR_ID_BUCK1_SC

#define BOARD_TPS65941_INTR_ID_BUCK1_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x02U)

◆ BOARD_TPS65941_INTR_ID_BUCK1_ILIM

#define BOARD_TPS65941_INTR_ID_BUCK1_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x03U)

◆ BOARD_TPS65941_INTR_ID_BUCK2_OV

#define BOARD_TPS65941_INTR_ID_BUCK2_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x04U)

◆ BOARD_TPS65941_INTR_ID_BUCK2_UV

#define BOARD_TPS65941_INTR_ID_BUCK2_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x05U)

◆ BOARD_TPS65941_INTR_ID_BUCK2_SC

#define BOARD_TPS65941_INTR_ID_BUCK2_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x06U)

◆ BOARD_TPS65941_INTR_ID_BUCK2_ILIM

#define BOARD_TPS65941_INTR_ID_BUCK2_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x07U)

◆ BOARD_TPS65941_INTR_ID_BUCK3_OV

#define BOARD_TPS65941_INTR_ID_BUCK3_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x08U)

◆ BOARD_TPS65941_INTR_ID_BUCK3_UV

#define BOARD_TPS65941_INTR_ID_BUCK3_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x09U)

◆ BOARD_TPS65941_INTR_ID_BUCK3_SC

#define BOARD_TPS65941_INTR_ID_BUCK3_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x0AU)

◆ BOARD_TPS65941_INTR_ID_BUCK3_ILIM

#define BOARD_TPS65941_INTR_ID_BUCK3_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0BU)

◆ BOARD_TPS65941_INTR_ID_BUCK4_OV

#define BOARD_TPS65941_INTR_ID_BUCK4_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0CU)

◆ BOARD_TPS65941_INTR_ID_BUCK4_UV

#define BOARD_TPS65941_INTR_ID_BUCK4_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0DU)

◆ BOARD_TPS65941_INTR_ID_BUCK4_SC

#define BOARD_TPS65941_INTR_ID_BUCK4_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x0EU)

◆ BOARD_TPS65941_INTR_ID_BUCK4_ILIM

#define BOARD_TPS65941_INTR_ID_BUCK4_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0FU)

◆ BOARD_TPS65941_INTR_ID_BUCK5_OV

#define BOARD_TPS65941_INTR_ID_BUCK5_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x10U)

◆ BOARD_TPS65941_INTR_ID_BUCK5_UV

#define BOARD_TPS65941_INTR_ID_BUCK5_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x11U)

◆ BOARD_TPS65941_INTR_ID_BUCK5_SC

#define BOARD_TPS65941_INTR_ID_BUCK5_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x12U)

◆ BOARD_TPS65941_INTR_ID_BUCK5_ILIM

#define BOARD_TPS65941_INTR_ID_BUCK5_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x13U)

◆ BOARD_TPS65941_INTR_ID_LDO1_OV

#define BOARD_TPS65941_INTR_ID_LDO1_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x00U)

◆ BOARD_TPS65941_INTR_ID_LDO1_UV

#define BOARD_TPS65941_INTR_ID_LDO1_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x01U)

◆ BOARD_TPS65941_INTR_ID_LDO1_SC

#define BOARD_TPS65941_INTR_ID_LDO1_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x02U)

◆ BOARD_TPS65941_INTR_ID_LDO1_ILIM

#define BOARD_TPS65941_INTR_ID_LDO1_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x03U)

◆ BOARD_TPS65941_INTR_ID_LDO2_OV

#define BOARD_TPS65941_INTR_ID_LDO2_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x04U)

◆ BOARD_TPS65941_INTR_ID_LDO2_UV

#define BOARD_TPS65941_INTR_ID_LDO2_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x05U)

◆ BOARD_TPS65941_INTR_ID_LDO2_SC

#define BOARD_TPS65941_INTR_ID_LDO2_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x06U)

◆ BOARD_TPS65941_INTR_ID_LDO2_ILIM

#define BOARD_TPS65941_INTR_ID_LDO2_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x07U)

◆ BOARD_TPS65941_INTR_ID_LDO3_OV

#define BOARD_TPS65941_INTR_ID_LDO3_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x08U)

◆ BOARD_TPS65941_INTR_ID_LDO3_UV

#define BOARD_TPS65941_INTR_ID_LDO3_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x09U)

◆ BOARD_TPS65941_INTR_ID_LDO3_SC

#define BOARD_TPS65941_INTR_ID_LDO3_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x0AU)

◆ BOARD_TPS65941_INTR_ID_LDO3_ILIM

#define BOARD_TPS65941_INTR_ID_LDO3_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0BU)

◆ BOARD_TPS65941_INTR_ID_LDO4_OV

#define BOARD_TPS65941_INTR_ID_LDO4_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0CU)

◆ BOARD_TPS65941_INTR_ID_LDO4_UV

#define BOARD_TPS65941_INTR_ID_LDO4_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0DU)

◆ BOARD_TPS65941_INTR_ID_LDO4_SC

#define BOARD_TPS65941_INTR_ID_LDO4_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x0EU)

◆ BOARD_TPS65941_INTR_ID_LDO4_ILIM

#define BOARD_TPS65941_INTR_ID_LDO4_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0FU)

◆ BOARD_TPS65941_INTR_ID_VCCA_OV

#define BOARD_TPS65941_INTR_ID_VCCA_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x10U)

◆ BOARD_TPS65941_INTR_ID_VCCA_UV

#define BOARD_TPS65941_INTR_ID_VCCA_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x11U)

◆ BOARD_TPS65941_INTR_ID_GPIO1_FALL

#define BOARD_TPS65941_INTR_ID_GPIO1_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x00U)

◆ BOARD_TPS65941_INTR_ID_GPIO2_FALL

#define BOARD_TPS65941_INTR_ID_GPIO2_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x01U)

◆ BOARD_TPS65941_INTR_ID_GPIO3_FALL

#define BOARD_TPS65941_INTR_ID_GPIO3_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x02U)

◆ BOARD_TPS65941_INTR_ID_GPIO4_FALL

#define BOARD_TPS65941_INTR_ID_GPIO4_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x03U)

◆ BOARD_TPS65941_INTR_ID_GPIO5_FALL

#define BOARD_TPS65941_INTR_ID_GPIO5_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x04U)

◆ BOARD_TPS65941_INTR_ID_GPIO6_FALL

#define BOARD_TPS65941_INTR_ID_GPIO6_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x05U)

◆ BOARD_TPS65941_INTR_ID_GPIO7_FALL

#define BOARD_TPS65941_INTR_ID_GPIO7_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x06U)

◆ BOARD_TPS65941_INTR_ID_GPIO8_FALL

#define BOARD_TPS65941_INTR_ID_GPIO8_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x07U)

◆ BOARD_TPS65941_INTR_ID_GPIO9_FALL

#define BOARD_TPS65941_INTR_ID_GPIO9_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x10U)

◆ BOARD_TPS65941_INTR_ID_GPIO10_FALL

#define BOARD_TPS65941_INTR_ID_GPIO10_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x11U)

◆ BOARD_TPS65941_INTR_ID_GPIO11_FALL

#define BOARD_TPS65941_INTR_ID_GPIO11_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x12U)

◆ BOARD_TPS65941_INTR_ID_GPIO1_RISE

#define BOARD_TPS65941_INTR_ID_GPIO1_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x08U)

◆ BOARD_TPS65941_INTR_ID_GPIO2_RISE

#define BOARD_TPS65941_INTR_ID_GPIO2_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x09U)

◆ BOARD_TPS65941_INTR_ID_GPIO3_RISE

#define BOARD_TPS65941_INTR_ID_GPIO3_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0AU)

◆ BOARD_TPS65941_INTR_ID_GPIO4_RISE

#define BOARD_TPS65941_INTR_ID_GPIO4_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0BU)

◆ BOARD_TPS65941_INTR_ID_GPIO5_RISE

#define BOARD_TPS65941_INTR_ID_GPIO5_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0CU)

◆ BOARD_TPS65941_INTR_ID_GPIO6_RISE

#define BOARD_TPS65941_INTR_ID_GPIO6_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0DU)

◆ BOARD_TPS65941_INTR_ID_GPIO7_RISE

#define BOARD_TPS65941_INTR_ID_GPIO7_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0EU)

◆ BOARD_TPS65941_INTR_ID_GPIO8_RISE

#define BOARD_TPS65941_INTR_ID_GPIO8_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0FU)

◆ BOARD_TPS65941_INTR_ID_GPIO9_RISE

#define BOARD_TPS65941_INTR_ID_GPIO9_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x13U)

◆ BOARD_TPS65941_INTR_ID_GPIO10_RISE

#define BOARD_TPS65941_INTR_ID_GPIO10_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x14U)

◆ BOARD_TPS65941_INTR_ID_GPIO11_RISE

#define BOARD_TPS65941_INTR_ID_GPIO11_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x15U)

◆ BOARD_TPS65941_INTR_ID_FSD

#define BOARD_TPS65941_INTR_ID_FSD ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (0 << 8) | 0x04U)

◆ BOARD_TPS65941_INTR_ID_RTC

#define BOARD_TPS65941_INTR_ID_RTC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (1 << 8) | 0x02U)

◆ BOARD_TPS65941_INTR_ID_ENABLE

#define BOARD_TPS65941_INTR_ID_ENABLE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (0 << 8) | 0x01U)

◆ BOARD_TPS65941_INTR_ID_NPWRON_START

#define BOARD_TPS65941_INTR_ID_NPWRON_START ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (0 << 8) | 0x00U)

◆ BOARD_TPS65941_INTR_ID_TWARN

#define BOARD_TPS65941_INTR_ID_TWARN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) | (0 << 8) | 0x03U)

◆ BOARD_TPS65941_INTR_ID_EXT_CLK

#define BOARD_TPS65941_INTR_ID_EXT_CLK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) | (0 << 8) | 0x01U)

◆ BOARD_TPS65941_INTR_ID_BIST_PASS

#define BOARD_TPS65941_INTR_ID_BIST_PASS ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) | (0 << 8) | 0x00U)

◆ BOARD_TPS65941_INTR_ID_RECOV_CNT

#define BOARD_TPS65941_INTR_ID_RECOV_CNT ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (1 << 8) | 0x06U)

◆ BOARD_TPS65941_INTR_ID_NPWRON_LONG

#define BOARD_TPS65941_INTR_ID_NPWRON_LONG ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x05U)

◆ BOARD_TPS65941_INTR_ID_SPMI_ERR

#define BOARD_TPS65941_INTR_ID_SPMI_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x04U)

◆ BOARD_TPS65941_INTR_ID_PFSM_ERR

#define BOARD_TPS65941_INTR_ID_PFSM_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x03U)

◆ BOARD_TPS65941_INTR_ID_REG_CRC_ERR

#define BOARD_TPS65941_INTR_ID_REG_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x02U)

◆ BOARD_TPS65941_INTR_ID_BIST_FAIL

#define BOARD_TPS65941_INTR_ID_BIST_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x01U)

◆ BOARD_TPS65941_INTR_ID_TSD_ORD

#define BOARD_TPS65941_INTR_ID_TSD_ORD ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (1 << 8) | 0x00U)

◆ BOARD_TPS65941_INTR_ID_VCCA_OVP

#define BOARD_TPS65941_INTR_ID_VCCA_OVP ((((uint32_t)BOARD_TPS65941_INTR_TYPE_SEVERE_ERR) << 16) | (1 << 8) | 0x01U)

◆ BOARD_TPS65941_INTR_ID_TSD_IMM

#define BOARD_TPS65941_INTR_ID_TSD_IMM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_SEVERE_ERR) << 16) | (1 << 8) | 0x00U)

◆ BOARD_TPS65941_INTR_ID_IMM_SHUTDOWN

#define BOARD_TPS65941_INTR_ID_IMM_SHUTDOWN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x00U)

◆ BOARD_TPS65941_INTR_ID_ORD_SHUTDOWN

#define BOARD_TPS65941_INTR_ID_ORD_SHUTDOWN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x01U)

◆ BOARD_TPS65941_INTR_ID_MCU_PWR_ERR

#define BOARD_TPS65941_INTR_ID_MCU_PWR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x02U)

◆ BOARD_TPS65941_INTR_ID_SOC_PWR_ERR

#define BOARD_TPS65941_INTR_ID_SOC_PWR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x03U)

◆ BOARD_TPS65941_INTR_ID_COMM_FRM_ERR

#define BOARD_TPS65941_INTR_ID_COMM_FRM_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x08U)

◆ BOARD_TPS65941_INTR_ID_COMM_CRC_ERR

#define BOARD_TPS65941_INTR_ID_COMM_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x09U)

◆ BOARD_TPS65941_INTR_ID_COMM_ADR_ERR

#define BOARD_TPS65941_INTR_ID_COMM_ADR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x0BU)

◆ BOARD_TPS65941_INTR_ID_I2C2_CRC_ERR

#define BOARD_TPS65941_INTR_ID_I2C2_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x0DU)

◆ BOARD_TPS65941_INTR_ID_I2C2_ADR_ERR

#define BOARD_TPS65941_INTR_ID_I2C2_ADR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x0FU)

◆ BOARD_TPS65941_INTR_ID_EN_DRV_RDBACK

#define BOARD_TPS65941_INTR_ID_EN_DRV_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x10U)

◆ BOARD_TPS65941_INTR_ID_NINT_RDBACK

#define BOARD_TPS65941_INTR_ID_NINT_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x11U)

◆ BOARD_TPS65941_INTR_ID_NRSTOUT_RDBACK

#define BOARD_TPS65941_INTR_ID_NRSTOUT_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x12U)

◆ BOARD_TPS65941_INTR_ID_NRSTOUT_SOC_RDBACK

#define BOARD_TPS65941_INTR_ID_NRSTOUT_SOC_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x13U)

◆ BOARD_TPS65941_INTR_ID_ESM_SOC_PIN

#define BOARD_TPS65941_INTR_ID_ESM_SOC_PIN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x18U)

◆ BOARD_TPS65941_INTR_ID_ESM_SOC_FAIL

#define BOARD_TPS65941_INTR_ID_ESM_SOC_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x19U)

◆ BOARD_TPS65941_INTR_ID_ESM_SOC_RST

#define BOARD_TPS65941_INTR_ID_ESM_SOC_RST ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1AU)

◆ BOARD_TPS65941_INTR_ID_ESM_MCU_PIN

#define BOARD_TPS65941_INTR_ID_ESM_MCU_PIN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1BU)

◆ BOARD_TPS65941_INTR_ID_ESM_MCU_FAIL

#define BOARD_TPS65941_INTR_ID_ESM_MCU_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1CU)

◆ BOARD_TPS65941_INTR_ID_ESM_MCU_RST

#define BOARD_TPS65941_INTR_ID_ESM_MCU_RST ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1DU)

◆ BOARD_TPS65941_INTR_REG_WIDTH

#define BOARD_TPS65941_INTR_REG_WIDTH (0x8U)

◆ BOARD_TPS65941_INTR_ENABLE

#define BOARD_TPS65941_INTR_ENABLE (0)

Interrupt Enable/Disable

◆ BOARD_TPS65941_INTR_DISABLE

#define BOARD_TPS65941_INTR_DISABLE (1)

◆ BOARD_TPS65941_INTR_SET

#define BOARD_TPS65941_INTR_SET (1)

Interrupt Set/UnSet

◆ BOARD_TPS65941_INTR_UNSET

#define BOARD_TPS65941_INTR_UNSET (0)

◆ BOARD_TPS65941_PG_3V3_LEVEL

#define BOARD_TPS65941_PG_3V3_LEVEL (0)

Voltage monitor PGOOD level values

◆ BOARD_TPS65941_PG_5V_LEVEL

#define BOARD_TPS65941_PG_5V_LEVEL (1)

◆ BOARD_TPS65941_PG_THR_3_PERCENT

#define BOARD_TPS65941_PG_THR_3_PERCENT (0x0U)

Voltage monitor PGOOD threshold values

◆ BOARD_TPS65941_PG_THR_3_5_PERCENT

#define BOARD_TPS65941_PG_THR_3_5_PERCENT (0x1U)

◆ BOARD_TPS65941_PG_THR_4_PERCENT

#define BOARD_TPS65941_PG_THR_4_PERCENT (0x2U)

◆ BOARD_TPS65941_PG_THR_5_PERCENT

#define BOARD_TPS65941_PG_THR_5_PERCENT (0x3U)

◆ BOARD_TPS65941_PG_THR_6_PERCENT

#define BOARD_TPS65941_PG_THR_6_PERCENT (0x4U)

◆ BOARD_TPS65941_PG_THR_7_PERCENT

#define BOARD_TPS65941_PG_THR_7_PERCENT (0x5U)

◆ BOARD_TPS65941_PG_THR_8_PERCENT

#define BOARD_TPS65941_PG_THR_8_PERCENT (0x6U)

◆ BOARD_TPS65941_PG_THR_10_PERCENT

#define BOARD_TPS65941_PG_THR_10_PERCENT (0x7U)

◆ BOARD_TPS65941_ILIM_2_5A

#define BOARD_TPS65941_ILIM_2_5A (0x2U)

Peak Current limit of BUCK power resources

◆ BOARD_TPS65941_ILIM_3_5A

#define BOARD_TPS65941_ILIM_3_5A (0x3U)

◆ BOARD_TPS65941_ILIM_4_5A

#define BOARD_TPS65941_ILIM_4_5A (0x4U)

◆ BOARD_TPS65941_ILIM_5_5A

#define BOARD_TPS65941_ILIM_5_5A (0x5U)

◆ BOARD_TPS65941_OV_UV_DISABLE

#define BOARD_TPS65941_OV_UV_DISABLE (0)

Voltage monitor OV and UV Enable/Disable

◆ BOARD_TPS65941_OV_UV_ENABLE

#define BOARD_TPS65941_OV_UV_ENABLE (1)

◆ BOARD_TPS65941_PGOOD_MASK

#define BOARD_TPS65941_PGOOD_MASK (0U)

PGOOD Mask Enable/Disable

◆ BOARD_TPS65941_PGOOD_UNMASK

#define BOARD_TPS65941_PGOOD_UNMASK (1U)

◆ BOARD_TPS65941_UV_MONITOR

#define BOARD_TPS65941_UV_MONITOR (0U)

PGOOD Window Value

◆ BOARD_TPS65941_UV_OV_MONITOR

#define BOARD_TPS65941_UV_OV_MONITOR (1U)

◆ BOARD_TPS65941_TDIE_NO_WARN

#define BOARD_TPS65941_TDIE_NO_WARN (0)

Thermal error status value

◆ BOARD_TPS65941_TDIE_WARN

#define BOARD_TPS65941_TDIE_WARN (1)

◆ BOARD_TPS65941_TDIE_WARN_ORD_SD

#define BOARD_TPS65941_TDIE_WARN_ORD_SD (2)

◆ BOARD_TPS65941_TDIE_WARN_IMM_SD

#define BOARD_TPS65941_TDIE_WARN_IMM_SD (3)

◆ BOARD_TPS65941_THERMAL_TEMP_120C

#define BOARD_TPS65941_THERMAL_TEMP_120C (0x0U)

Thermal threshold value

◆ BOARD_TPS65941_THERMAL_TEMP_130C

#define BOARD_TPS65941_THERMAL_TEMP_130C (0x1U)

◆ BOARD_TPS65941_ESM_STOP

#define BOARD_TPS65941_ESM_STOP (0x0)

ESM Start/Stop value

◆ BOARD_TPS65941_ESM_START

#define BOARD_TPS65941_ESM_START (0x1)

◆ BOARD_TPS65941_ESM_DISABLE

#define BOARD_TPS65941_ESM_DISABLE (0x0)

ESM Enable/Disable value

◆ BOARD_TPS65941_ESM_ENABLE

#define BOARD_TPS65941_ESM_ENABLE (0x1)

◆ BOARD_TPS65941_SECOND_INTR_PERIOD

#define BOARD_TPS65941_SECOND_INTR_PERIOD (0x0U)

RTC timer Periods

◆ BOARD_TPS65941_MINUTE_INTR_PERIOD

#define BOARD_TPS65941_MINUTE_INTR_PERIOD (0x1U)

◆ BOARD_TPS65941_HOUR_INTR_PERIOD

#define BOARD_TPS65941_HOUR_INTR_PERIOD (0x2U)

◆ BOARD_TPS65941_DAY_INTR_PERIOD

#define BOARD_TPS65941_DAY_INTR_PERIOD (0x3U)

◆ BOARD_TPS65941_ALARM_INTR_ENABLE

#define BOARD_TPS65941_ALARM_INTR_ENABLE (0x1U)

RTC alarm and timer interrupt

◆ BOARD_TPS65941_ALARM_INTR_DISABLE

#define BOARD_TPS65941_ALARM_INTR_DISABLE (0x0U)

◆ BOARD_TPS65941_TIMER_INTR_ENABLE

#define BOARD_TPS65941_TIMER_INTR_ENABLE (0x1U)

◆ BOARD_TPS65941_TIMER_INTR_DISABLE

#define BOARD_TPS65941_TIMER_INTR_DISABLE (0x0U)

◆ BOARD_TPS65941_WDT_DISABLE

#define BOARD_TPS65941_WDT_DISABLE (0x1U)

Watchdog timer Mode

◆ BOARD_TPS65941_WDT_ENABLE

#define BOARD_TPS65941_WDT_ENABLE (0x0U)

◆ BOARD_TPS65941_WDT_TRIGGER_MODE

#define BOARD_TPS65941_WDT_TRIGGER_MODE (0x0U)

Watchdog config mode

◆ BOARD_TPS65941_WDT_QA_MODE

#define BOARD_TPS65941_WDT_QA_MODE (0x1U)

◆ BOARD_TPS65941_WDT_RST_DISABLE

#define BOARD_TPS65941_WDT_RST_DISABLE (0x0U)

Watchdog reset Enable/Disable

◆ BOARD_TPS65941_WDT_RST_ENABLE

#define BOARD_TPS65941_WDT_RST_ENABLE (0x1U)

◆ BOARD_TPS65941_ESM_SOC

#define BOARD_TPS65941_ESM_SOC (0x0U)

ESM configuration

◆ BOARD_TPS65941_ESM_MCU

#define BOARD_TPS65941_ESM_MCU (0x1U)

◆ BOARD_TPS65941_ESM_LEVEL_MODE

#define BOARD_TPS65941_ESM_LEVEL_MODE (0x0U)

ESM configuration mode

◆ BOARD_TPS65941_ESM_PWM_MODE

#define BOARD_TPS65941_ESM_PWM_MODE (0x1U)

◆ BOARD_TPS65941_12_HOUR_MODE

#define BOARD_TPS65941_12_HOUR_MODE (1)

RTC time mode

◆ BOARD_TPS65941_24_HOUR_MODE

#define BOARD_TPS65941_24_HOUR_MODE (0)

◆ BOARD_TPS65941_AM_MODE

#define BOARD_TPS65941_AM_MODE (0)

RTC Meridien mode

◆ BOARD_TPS65941_PM_MODE

#define BOARD_TPS65941_PM_MODE (1)

◆ BOARD_TPS65941_SUNDAY

#define BOARD_TPS65941_SUNDAY (0)

RTC Week days

◆ BOARD_TPS65941_MONDAY

#define BOARD_TPS65941_MONDAY (1)

◆ BOARD_TPS65941_TUESDAY

#define BOARD_TPS65941_TUESDAY (2)

◆ BOARD_TPS65941_WEDNESDAY

#define BOARD_TPS65941_WEDNESDAY (3)

◆ BOARD_TPS65941_THURSDAY

#define BOARD_TPS65941_THURSDAY (4)

◆ BOARD_TPS65941_FRIDAY

#define BOARD_TPS65941_FRIDAY (5)

◆ BOARD_TPS65941_SATURDAY

#define BOARD_TPS65941_SATURDAY (6)

◆ BOARD_TPS65941_RTC_FROZEN

#define BOARD_TPS65941_RTC_FROZEN (0)

RTC State

◆ BOARD_TPS65941_RTC_START

#define BOARD_TPS65941_RTC_START (1)

◆ BOARD_TPS65941_WDT_RST_INT

#define BOARD_TPS65941_WDT_RST_INT (0)

WDT Error status values

◆ BOARD_TPS65941_WDT_FAIL_INT

#define BOARD_TPS65941_WDT_FAIL_INT (1)

◆ BOARD_TPS65941_WDT_ANSW_ERR

#define BOARD_TPS65941_WDT_ANSW_ERR (2)

◆ BOARD_TPS65941_WDT_SEQ_ERR

#define BOARD_TPS65941_WDT_SEQ_ERR (3)

◆ BOARD_TPS65941_WDT_ANSW_ERLY_ERR

#define BOARD_TPS65941_WDT_ANSW_ERLY_ERR (4)

◆ BOARD_TPS65941_WDT_TRIG_ERLY_ERR

#define BOARD_TPS65941_WDT_TRIG_ERLY_ERR (5)

◆ BOARD_TPS65941_WDT_TIMEOUT_ERR

#define BOARD_TPS65941_WDT_TIMEOUT_ERR (6)

◆ BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_ERR

#define BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_ERR (7)

◆ BOARD_TPS65941_WDT_ERR_LATCHED

#define BOARD_TPS65941_WDT_ERR_LATCHED (1)

◆ BOARD_TPS65941_WDT_NO_ERR

#define BOARD_TPS65941_WDT_NO_ERR (0)

◆ BOARD_I2C_NUM_OF_BYTES_01

#define BOARD_I2C_NUM_OF_BYTES_01 (1U)

I2C number of bytes