PDK API Guide for J721E
Data Fields
CSITX_DphyConfig Struct Reference
CSL-FL » CSITX CSL-FL » CSITX Dynamic Data Structures

Detailed Description

Configuration of DPHY

Data Fields

bool dphyReset
 
bool dphyCalEnable
 
uint8_t dphyClockMode
 
uint8_t dphyMode
 
bool dphyClkEnable
 
bool dphyLn3Enable
 
bool dphyLn2Enable
 
bool dphyLn1Enable
 
bool dphyLn0Enable
 

Field Documentation

bool CSITX_DphyConfig::dphyReset

Active low reset for D-PHY

bool CSITX_DphyConfig::dphyCalEnable

D-PHY Calibration Enable.

uint8_t CSITX_DphyConfig::dphyClockMode

D-PHY Clock Mode.

uint8_t CSITX_DphyConfig::dphyMode

D-PHY Mode

bool CSITX_DphyConfig::dphyClkEnable

Active high enable for DPHY clock lane

bool CSITX_DphyConfig::dphyLn3Enable

Active high enable for DPHY data lane 3

bool CSITX_DphyConfig::dphyLn2Enable

Active high enable for DPHY data lane 2

bool CSITX_DphyConfig::dphyLn1Enable

Active high enable for DPHY data lane 1

bool CSITX_DphyConfig::dphyLn0Enable

Active high enable for DPHY data lane 0