CSIRX_StreamStatus Struct Reference

Detailed Description

CSI2 Slave Controller Status. Contains useful debug information such as FSM states.

Data Fields
uint8_t	running
uint8_t	readyState
uint8_t	streamFsm
uint8_t	protocolFsm

Field Documentation

uint8_t CSIRX_StreamStatus::running

he Stream is enabled

uint8_t CSIRX_StreamStatus::readyState

Indicates the state of the pushback signal PixelReadyIf for this stream

uint8_t CSIRX_StreamStatus::streamFsm

"Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA Expecting control data next 0x2: STREAM_CTRL Check contents of Ctrl packet and extract header information 0x3: STREAM_DATA Pixel stream pixel data unpacking 0x4: STREAM_DATA_START Assert Hsync 0x5: STREAM_DATA_END De-assert Hysnc 0x6: STREAM_FILL_WAIT Elastic Buffer cfg - wait until fill level is reached 0x7: STREAM_STOP Stop at the end of Frame - used to set irq 0x8: STREAM_WAIT_CRC Wait until CRC check has completed - Full Line cfg 0x9: STREAM_DATA_PACKED Packed stream data handling 0xA-F : Reserved

uint8_t CSIRX_StreamStatus::protocolFsm

Input to Stream FSM states: 0x0: PRO_IDLE 0x1: PROT_CRL 0x2: PROT_DAA 0x3: Reserved