PDK API Guide for J721E
CacheP

Introduction

CacheP interface

Files

file  CacheP.h
 Cache Handling routines for the RTOS Porting Interface.
 

Functions

void CacheP_wb (const void *addr, int32_t size)
 Function to write back cache lines. More...
 
void CacheP_Inv (const void *addr, int32_t size)
 Function to invalidate cache lines. More...
 
void CacheP_wbInv (const void *addr, int32_t size)
 Function to write back and invalidate cache lines. More...
 
void CacheP_fenceCpu2Dma (uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent)
 Function to call before handing over the memory buffer to DMA from CPU. More...
 
void CacheP_fenceDma2Cpu (uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent)
 Function to call before reading the memory to CPU after DMA operations. More...
 

Typedefs

typedef uint32_t Osal_CacheP_isCoherent
 This enumerator defines the cache coherent or not. More...
 

Macros

#define OSAL_CACHEP_COHERENT   ((uint32_t) 0U)
 
#define OSAL_CACHEP_NOT_COHERENT   ((uint32_t) 1U)
 

Macro Definition Documentation

#define OSAL_CACHEP_COHERENT   ((uint32_t) 0U)

Cache is coherent on this CPU

#define OSAL_CACHEP_NOT_COHERENT   ((uint32_t) 1U)

Cache is not coherent on this CPU

Typedef Documentation

typedef uint32_t Osal_CacheP_isCoherent

This enumerator defines the cache coherent or not.

Function Documentation

void CacheP_wb ( const void *  addr,
int32_t  size 
)

Function to write back cache lines.

Parameters
addrStart address of the cache line/s
sizesize (in bytes) of the memory to be written back
void CacheP_Inv ( const void *  addr,
int32_t  size 
)

Function to invalidate cache lines.

Parameters
addrStart address of the cache line/s
sizesize (in bytes) of the memory to invalidate
void CacheP_wbInv ( const void *  addr,
int32_t  size 
)

Function to write back and invalidate cache lines.

Parameters
addrStart address of the cache line/s
sizesize (in bytes) of the memory to be written back and invalidate
void CacheP_fenceCpu2Dma ( uintptr_t  addr,
uint32_t  size,
Osal_CacheP_isCoherent  isCoherent 
)

Function to call before handing over the memory buffer to DMA from CPU.

Parameters
addrStart address of the cache line/s
sizesize (in bytes) of the memory to be written back and invalidate
isCoherentif the cache is coherent on that CPU or not
void CacheP_fenceDma2Cpu ( uintptr_t  addr,
uint32_t  size,
Osal_CacheP_isCoherent  isCoherent 
)

Function to call before reading the memory to CPU after DMA operations.

Parameters
addrStart address of the cache line/s
sizesize (in bytes) of the memory to be written back and invalidate
isCoherentif the cache is coherent on that CPU or not Osal_CacheP_isCoherent