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PDK API Guide for J721E
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Data types used by TPS65941 PMIC device library.
| #define BOARD_TPS65941_GPIO1_CONF (0x31U) |
GPIO Register Offsets
| #define BOARD_TPS65941_GPIO2_CONF (0x32U) |
| #define BOARD_TPS65941_GPIO3_CONF (0x33U) |
| #define BOARD_TPS65941_GPIO4_CONF (0x34U) |
| #define BOARD_TPS65941_GPIO5_CONF (0x35U) |
| #define BOARD_TPS65941_GPIO6_CONF (0x36U) |
| #define BOARD_TPS65941_GPIO7_CONF (0x37U) |
| #define BOARD_TPS65941_GPIO8_CONF (0x38U) |
| #define BOARD_TPS65941_GPIO9_CONF (0x39U) |
| #define BOARD_TPS65941_GPIO10_CONF (0x3AU) |
| #define BOARD_TPS65941_GPIO11_CONF (0x3BU) |
| #define BOARD_TPS65941_NPWRON_CONF (0x3CU) |
| #define BOARD_TPS65941_GPIO_OUT_1 (0x3DU) |
| #define BOARD_TPS65941_GPIO_OUT_2 (0x3EU) |
| #define BOARD_TPS65941_GPIO_IN_1 (0x3FU) |
| #define BOARD_TPS65941_GPIO_IN_2 (0x40U) |
| #define BOARD_TPS65941_BUCK1_CTRL (0x04U) |
BUCK Power resource Register Offsets
| #define BOARD_TPS65941_BUCK2_CTRL (0x06U) |
| #define BOARD_TPS65941_BUCK3_CTRL (0x08U) |
| #define BOARD_TPS65941_BUCK4_CTRL (0x0AU) |
| #define BOARD_TPS65941_BUCK5_CTRL (0x0CU) |
| #define BOARD_TPS65941_BUCK1_CONF (0x05U) |
| #define BOARD_TPS65941_BUCK2_CONF (0x07U) |
| #define BOARD_TPS65941_BUCK3_CONF (0x09U) |
| #define BOARD_TPS65941_BUCK4_CONF (0x0BU) |
| #define BOARD_TPS65941_BUCK5_CONF (0x0DU) |
| #define BOARD_TPS65941_BUCK1_VOUT_1 (0x0EU) |
| #define BOARD_TPS65941_BUCK1_VOUT_2 (0x0FU) |
| #define BOARD_TPS65941_BUCK2_VOUT_1 (0x10U) |
| #define BOARD_TPS65941_BUCK2_VOUT_2 (0x11U) |
| #define BOARD_TPS65941_BUCK3_VOUT_1 (0x12U) |
| #define BOARD_TPS65941_BUCK3_VOUT_2 (0x13U) |
| #define BOARD_TPS65941_BUCK4_VOUT_1 (0x14U) |
| #define BOARD_TPS65941_BUCK4_VOUT_2 (0x15U) |
| #define BOARD_TPS65941_BUCK5_VOUT_1 (0x16U) |
| #define BOARD_TPS65941_BUCK5_VOUT_2 (0x17U) |
| #define BOARD_TPS65941_BUCK1_PG_WIN (0x18U) |
| #define BOARD_TPS65941_BUCK2_PG_WIN (0x19U) |
| #define BOARD_TPS65941_BUCK3_PG_WIN (0x1AU) |
| #define BOARD_TPS65941_BUCK4_PG_WIN (0x1BU) |
| #define BOARD_TPS65941_BUCK5_PG_WIN (0x1CU) |
| #define BOARD_TPS65941_LDO1_CTRL (0x1DU) |
LDO Power resource Register Offsets
| #define BOARD_TPS65941_LDO2_CTRL (0x1EU) |
| #define BOARD_TPS65941_LDO3_CTRL (0x1FU) |
| #define BOARD_TPS65941_LDO4_CTRL (0x20U) |
| #define BOARD_TPS65941_LDO1_VOUT (0x23U) |
| #define BOARD_TPS65941_LDO2_VOUT (0x24U) |
| #define BOARD_TPS65941_LDO3_VOUT (0x25U) |
| #define BOARD_TPS65941_LDO4_VOUT (0x26U) |
| #define BOARD_TPS65941_LDO1_PG_WIN (0x27U) |
| #define BOARD_TPS65941_LDO2_PG_WIN (0x28U) |
| #define BOARD_TPS65941_LDO3_PG_WIN (0x29U) |
| #define BOARD_TPS65941_LDO4_PG_WIN (0x2AU) |
| #define BOARD_TPS65941_VCCA_VMON_CTRL (0x2BU) |
VCCA Voltage monitor Register Offsets
| #define BOARD_TPS65941_VCCA_PG_WINDOW (0x2CU) |
| #define BOARD_TPS65941_BUCK_MASK (0x49) |
Interrupt Mask Register Offsets
| #define BOARD_TPS65941_LDO_MASK (0x4C) |
| #define BOARD_TPS65941_GPIO_MASK (0x4F) |
| #define BOARD_TPS65941_STARTUP_MASK (0x52) |
| #define BOARD_TPS65941_MISC_WARN_MASK (0x53) |
| #define BOARD_TPS65941_MOD_ERR_MASK (0x54) |
| #define BOARD_TPS65941_FSM_ERR_MASK (0x56) |
| #define BOARD_TPS65941_INT_TOP (0x5A) |
Interrupt Register Offsets
| #define BOARD_TPS65941_BUCK_INT (0x5C) |
| #define BOARD_TPS65941_LDO_VMON_INT (0x60) |
| #define BOARD_TPS65941_GPIO_INT (0x63) |
| #define BOARD_TPS65941_STARTUP_INT (0x65) |
| #define BOARD_TPS65941_MISC_INT (0x66) |
| #define BOARD_TPS65941_MOD_ERR_INT (0x67) |
| #define BOARD_TPS65941_SEV_ERR_INT (0x68) |
| #define BOARD_TPS65941_FSM_ERR_INT (0x69) |
| #define BOARD_TPS65941_STAT_MISC (0x74U) |
Status Register Offset
| #define BOARD_TPS65941_STAT_MODERATE_ERR (0x75U) |
| #define BOARD_TPS65941_STAT_SEVERE_ERR (0x76U) |
| #define BOARD_TPS65941_PGOOD_1 (0x78U) |
PGOOD Register Offsets
| #define BOARD_TPS65941_PGOOD_2 (0x79U) |
| #define BOARD_TPS65941_PGOOD_3 (0x7AU) |
| #define BOARD_TPS65941_PGOOD_4 (0x7BU) |
| #define BOARD_TPS65941_CONFIG_1 (0x7DU) |
TPS65941 Configuration Register Offsets
| #define BOARD_TPS65941_CONFIG_2 (0x7EU) |
| #define BOARD_TPS65941_ESM_MCU_START (0x8FU) |
TPS65941 ESM Register Offsets
| #define BOARD_TPS65941_ESM_MCU_DELAY1 (0x90U) |
| #define BOARD_TPS65941_ESM_MCU_DELAY2 (0x91U) |
| #define BOARD_TPS65941_ESM_MCU_MODE_CFG (0x92U) |
| #define BOARD_TPS65941_ESM_MCU_HMAX (0x93U) |
| #define BOARD_TPS65941_ESM_MCU_HMIN (0x94U) |
| #define BOARD_TPS65941_ESM_MCU_LMAX (0x95U) |
| #define BOARD_TPS65941_ESM_MCU_LMIN (0x96U) |
| #define BOARD_TPS65941_ESM_MCU_ERR_CNT (0x97U) |
| #define BOARD_TPS65941_ESM_SOC_START (0x98U) |
| #define BOARD_TPS65941_ESM_SOC_DELAY1 (0x99U) |
| #define BOARD_TPS65941_ESM_SOC_DELAY2 (0x9AU) |
| #define BOARD_TPS65941_ESM_SOC_MODE_CFG (0x9BU) |
| #define BOARD_TPS65941_ESM_SOC_HMAX (0x9CU) |
| #define BOARD_TPS65941_ESM_SOC_HMIN (0x9DU) |
| #define BOARD_TPS65941_ESM_SOC_LMAX (0x9EU) |
| #define BOARD_TPS65941_ESM_SOC_LMIN (0x9FU) |
| #define BOARD_TPS65941_ESM_SOC_ERR_CNT (0xA0U) |
| #define BOARD_TPS65941_RTC_SECONDS (0xB5U) |
TPS65941 RTC time and date Register Offsets
| #define BOARD_TPS65941_RTC_MINUTES (0xB6U) |
| #define BOARD_TPS65941_RTC_HOURS (0xB7U) |
| #define BOARD_TPS65941_RTC_DAYS (0xB8U) |
| #define BOARD_TPS65941_RTC_MONTHS (0xB9U) |
| #define BOARD_TPS65941_RTC_YEARS (0xBAU) |
| #define BOARD_TPS65941_RTC_WEEKS (0xBBU) |
| #define BOARD_TPS65941_ALARM_SECONDS (0xBCU) |
TPS65941 Alarm time and date Register Offsets
| #define BOARD_TPS65941_ALARM_MINUTES (0xBDU) |
| #define BOARD_TPS65941_ALARM_HOURS (0xBEU) |
| #define BOARD_TPS65941_ALARM_DAYS (0xBFU) |
| #define BOARD_TPS65941_ALARM_MONTHS (0xC0U) |
| #define BOARD_TPS65941_ALARM_YEARS (0xC1U) |
| #define BOARD_TPS65941_RTC_CTRL_1 (0xC2U) |
TPS65941 RTC Register Offsets
| #define BOARD_TPS65941_RTC_CTRL_2 (0xC3U) |
| #define BOARD_TPS65941_RTC_STATUS (0xC4U) |
| #define BOARD_TPS65941_RTC_INTR (0xC5U) |
| #define BOARD_TPS65941_WDT_ANSW_REG (0x01U) |
TPS65941 WDT Register Offsets
| #define BOARD_TPS65941_WDT_QUES_ANSW_CNT (0x02U) |
| #define BOARD_TPS65941_WDT_WIN1_CFG (0x03U) |
| #define BOARD_TPS65941_WDT_WIN2_CFG (0x04U) |
| #define BOARD_TPS65941_WDT_LONGWIN_CFG (0x05U) |
| #define BOARD_TPS65941_WDT_MODE_REG (0x06U) |
| #define BOARD_TPS65941_WDT_QA_CFG (0x07U) |
| #define BOARD_TPS65941_WDT_ERR_STAT (0x08U) |
| #define BOARD_TPS65941_WDT_THR_CFG (0x09U) |
| #define BOARD_TPS65941_WDT_FAIL_CNT_REG (0x0AU) |
| #define BOARD_TPS65941_GPIO_SEL_SHIFT (0x05U) |
GPIO Register bit fields
| #define BOARD_TPS65941_GPIO_DEGLITCH_EN_SHIFT (0x04U) |
| #define BOARD_TPS65941_GPIO_PU_PD_EN_SHIFT (0x03U) |
| #define BOARD_TPS65941_GPIO_PU_SEL_SHIFT (0x02U) |
| #define BOARD_TPS65941_GPIO_OD_SHIFT (0x01U) |
| #define BOARD_TPS65941_GPIO_DIR_SHIFT (0x00U) |
| #define BOARD_TPS65941_NPWRON_SEL_SHIFT (0x06U) |
NPWRON Register bit fields
| #define BOARD_TPS65941_NPWRON_POL_SHIFT (0x05U) |
| #define BOARD_TPS65941_NPWRON_PU_PD_EN_SHIFT (0x03U) |
| #define BOARD_TPS65941_NPWRON_PU_SEL_SHIFT (0x02U) |
| #define BOARD_TPS65941_NPWRON_OD_SHIFT (0x00U) |
| #define BOARD_TPS65941_GPIO1_IN_OUT_SHIFT (0x00U) |
GPIO IN/OUT Register bit fields
| #define BOARD_TPS65941_GPIO2_IN_OUT_SHIFT (0x01U) |
| #define BOARD_TPS65941_GPIO3_IN_OUT_SHIFT (0x02U) |
| #define BOARD_TPS65941_GPIO4_IN_OUT_SHIFT (0x03U) |
| #define BOARD_TPS65941_GPIO5_IN_OUT_SHIFT (0x04U) |
| #define BOARD_TPS65941_GPIO6_IN_OUT_SHIFT (0x05U) |
| #define BOARD_TPS65941_GPIO7_IN_OUT_SHIFT (0x06U) |
| #define BOARD_TPS65941_GPIO8_IN_OUT_SHIFT (0x07U) |
| #define BOARD_TPS65941_GPIO9_IN_OUT_SHIFT (0x00U) |
| #define BOARD_TPS65941_GPIO10_IN_OUT_SHIFT (0x01U) |
| #define BOARD_TPS65941_GPIO11_IN_OUT_SHIFT (0x02U) |
| #define BOARD_TPS65941_NPWRON_IN_OUT_SHIFT (0x03U) |
| #define BOARD_TPS65941_BUCK_VSEL_SHIFT (0x03U) |
BUCK Power resource bit fields
| #define BOARD_TPS65941_BUCK_EN_SHIFT (0x00U) |
| #define BOARD_TPS65941_BUCK_ILIM_SHIFT (0x03U) |
| #define BOARD_TPS65941_LDO_EN_SHIFT (0x00U) |
LDO Power resource bit field
| #define BOARD_TPS65941_BUCK_VSET_SHIFT (0x00U) |
BUCK Voltage set bit field
| #define BOARD_TPS65941_LDO_123_VSET_SHIFT (0x01U) |
LDO Voltage set bit fields
| #define BOARD_TPS65941_LDO4_VSET_SHIFT (0x00U) |
| #define BOARD_TPS65941_PWR_VMON_EN_SHIFT (0x04U) |
Power resource voltage monitor set bit field
| #define BOARD_TPS65941_PWR_UV_THR_SHIFT (0x03U) |
Power resource PG Window set bit fields
| #define BOARD_TPS65941_PWR_OV_THR_SHIFT (0x00U) |
| #define BOARD_TPS65941_BUCK1_PG_SEL_SHIFT (0x00U) |
Power resource PGOOD bit fields
| #define BOARD_TPS65941_BUCK2_PG_SEL_SHIFT (0x02U) |
| #define BOARD_TPS65941_BUCK3_PG_SEL_SHIFT (0x04U) |
| #define BOARD_TPS65941_BUCK4_PG_SEL_SHIFT (0x06U) |
| #define BOARD_TPS65941_BUCK5_PG_SEL_SHIFT (0x00U) |
| #define BOARD_TPS65941_LDO1_PG_SEL_SHIFT (0x00U) |
| #define BOARD_TPS65941_LDO2_PG_SEL_SHIFT (0x02U) |
| #define BOARD_TPS65941_LDO3_PG_SEL_SHIFT (0x04U) |
| #define BOARD_TPS65941_LDO4_PG_SEL_SHIFT (0x06U) |
| #define BOARD_TPS65941_VCCA_VMON_EN_SHIFT (0x00U) |
VCCA voltage monitor bit fields
| #define BOARD_TPS65941_VCCA_PG_SET_SHIFT (0x06U) |
| #define BOARD_TPS65941_VCCA_UV_THR_SHIFT (0x03U) |
| #define BOARD_TPS65941_VCCA_OV_THR_SHIFT (0x00U) |
| #define BOARD_TPS65941_TWARN_STAT_SHIFT (0x03U) |
Status register bit fields
| #define BOARD_TPS65941_TSD_ORD_STAT_SHIFT (0x00U) |
| #define BOARD_TPS65941_TSD_IMM_STAT_SHIFT (0x00U) |
| #define BOARD_TPS65941_PGOOD_WINDOW_SHIFT (0x07U) |
PGOOD signal bit fields
| #define BOARD_TPS65941_PGOOD_POL_SHIFT (0x06U) |
| #define BOARD_TPS65941_PGOOD_NRSTOUT_SOC_SHIFT (0x05U) |
| #define BOARD_TPS65941_PGOOD_NRSTOUT_SHIFT (0x04U) |
| #define BOARD_TPS65941_PGOOD_TDIE_WARN_SHIFT (0x03U) |
| #define BOARD_TPS65941_PGOOD_VCCA_SEL_SHIFT (0x00U) |
| #define BOARD_TPS65941_TWARN_LVL_SHIFT (0x00U) |
Thermal threshold value bit fields
| #define BOARD_TPS65941_ESM_START_SHIFT (0x00U) |
ESM MCU and SOC bit fields
| #define BOARD_TPS65941_ESM_DLY1_SHIFT (0x00U) |
| #define BOARD_TPS65941_ESM_DLY2_SHIFT (0x00U) |
| #define BOARD_TPS65941_ESM_MODE_SHIFT (0x07U) |
| #define BOARD_TPS65941_ESM_EN_SHIFT (0x06U) |
| #define BOARD_TPS65941_ESM_ERR_THR_SHIFT (0x00U) |
| #define BOARD_TPS65941_ESM_HMAX_SHIFT (0x00U) |
| #define BOARD_TPS65941_ESM_HMIN_SHIFT (0x00U) |
| #define BOARD_TPS65941_ESM_LMAX_SHIFT (0x00U) |
| #define BOARD_TPS65941_ESM_LMIN_SHIFT (0x00U) |
| #define BOARD_TPS65941_ESM_ERR_CNT_SHIFT (0x00U) |
| #define BOARD_TPS65941_RTC_ALRM_SEC_1_SHIFT (0x04U) |
RTC and alarm time and date bit fields
| #define BOARD_TPS65941_RTC_ALRM_SEC_0_SHIFT (0x00U) |
| #define BOARD_TPS65941_RTC_ALRM_MIN_1_SHIFT (0x04U) |
| #define BOARD_TPS65941_RTC_ALRM_MIN_0_SHIFT (0x00U) |
| #define BOARD_TPS65941_RTC_ALRM_AM_PM_SHIFT (0x07U) |
| #define BOARD_TPS65941_RTC_ALRM_HR_1_SHIFT (0x04U) |
| #define BOARD_TPS65941_RTC_ALRM_HR_0_SHIFT (0x00U) |
| #define BOARD_TPS65941_RTC_ALRM_DAY_1_SHIFT (0x04U) |
| #define BOARD_TPS65941_RTC_ALRM_DAY_0_SHIFT (0x00U) |
| #define BOARD_TPS65941_RTC_ALRM_MON_1_SHIFT (0x04U) |
| #define BOARD_TPS65941_RTC_ALRM_MON_0_SHIFT (0x00U) |
| #define BOARD_TPS65941_RTC_ALRM_YR_1_SHIFT (0x04U) |
| #define BOARD_TPS65941_RTC_ALRM_YR_0_SHIFT (0x00U) |
| #define BOARD_TPS65941_RTC_WEEK_SHIFT (0x00U) |
| #define BOARD_TPS65941_RTC_REG_OPT_SHIFT (0x07U) |
RTC CTRL bit fields
| #define BOARD_TPS65941_GET_TIME_SHIFT (0x06U) |
| #define BOARD_TPS65941_HOUR_MODE_SHIFT (0x03U) |
| #define BOARD_TPS65941_ROUND_30S_SHIFT (0x01U) |
| #define BOARD_TPS65941_STOP_RTC_SHIFT (0x00U) |
| #define BOARD_TPS65941_ALRM_STAT_SHIFT (0x06U) |
RTC Status bit fields
| #define BOARD_TPS65941_TIMER_STAT_SHIFT (0x05U) |
| #define BOARD_TPS65941_RUN_SHIFT (0x01U) |
| #define BOARD_TPS65941_ALARM_INTR_SHIFT (0x03U) |
RTC Interrupt bit fields
| #define BOARD_TPS65941_TIMER_INTR_SHIFT (0x02U) |
| #define BOARD_TPS65941_TIMER_PERIOD_SHIFT (0x00U) |
RTC Timer periods bit fields
| #define BOARD_TPS65941_WDT_ANSW_SHIFT (0x00U) |
WDT configuration bit fields
| #define BOARD_TPS65941_WDT_ANSW_CNT_SHIFT (0x04U) |
| #define BOARD_TPS65941_WDT_QUES_SHIFT (0x00U) |
| #define BOARD_TPS65941_WDT_WIN1_CFG_SHIFT (0x00U) |
| #define BOARD_TPS65941_WDT_WIN2_CFG_SHIFT (0x00U) |
| #define BOARD_TPS65941_WDT_LONGWIN_CFG_SHIFT (0x00U) |
| #define BOARD_TPS65941_WDT_MODE_SHIFT (0x01U) |
| #define BOARD_TPS65941_WDT_LONGWIN_RET_SHIFT (0x00U) |
| #define BOARD_TPS65941_WDT_RST_STAT_SHIFT (0x07U) |
WDT Error status bit fields
| #define BOARD_TPS65941_WDT_FAIL_STAT_SHIFT (0x06U) |
| #define BOARD_TPS65941_WDT_ANSW_ERR_SHIFT (0x05U) |
| #define BOARD_TPS65941_WDT_SEQ_ERR_SHIFT (0x04U) |
| #define BOARD_TPS65941_WDT_ANSW_ERLY_SHIFT (0x03U) |
| #define BOARD_TPS65941_WDT_TRIG_ERLY_SHIFT (0x02U) |
| #define BOARD_TPS65941_WDT_TIMEOUT_SHIFT (0x01U) |
| #define BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_SHIFT (0x00U) |
| #define BOARD_TPS65941_WDT_RST_EN_SHIFT (0x07U) |
WDT Threshold bit fields
| #define BOARD_TPS65941_WDT_EN_SHIFT (0x06U) |
| #define BOARD_TPS65941_WDT_FAIL_THR_SHIFT (0x03U) |
| #define BOARD_TPS65941_WDT_RST_THR_SHIFT (0x00U) |
| #define BOARD_TPS65941_WDT_BAD_EVT_SHIFT (0x06U) |
WDT Fail count bit fields
| #define BOARD_TPS65941_WDT_FIRST_OK_SHIFT (0x05U) |
| #define BOARD_TPS65941_WDT_FAIL_CNT_SHIFT (0x00U) |
| #define BOARD_TPS65941_GPIO_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_SEL_SHIFT) |
GPIO Register bit mask
| #define BOARD_TPS65941_GPIO_DEGLITCH_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_DEGLITCH_EN_SHIFT) |
| #define BOARD_TPS65941_GPIO_PU_PD_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_PU_PD_EN_SHIFT) |
| #define BOARD_TPS65941_GPIO_PU_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_PU_SEL_SHIFT) |
| #define BOARD_TPS65941_GPIO_OD_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_OD_SHIFT) |
| #define BOARD_TPS65941_GPIO_DIR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_DIR_SHIFT) |
| #define BOARD_TPS65941_NPWRON_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_SEL_SHIFT) |
NPWRON Register bit mask
| #define BOARD_TPS65941_NPWRON_POL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_POL_SHIFT) |
| #define BOARD_TPS65941_NPWRON_PU_PD_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_PU_PD_EN_SHIFT) |
| #define BOARD_TPS65941_NPWRON_PU_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_PU_SEL_SHIFT) |
| #define BOARD_TPS65941_NPWRON_OD_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_OD_SHIFT) |
| #define BOARD_TPS65941_GPIO1_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO1_IN_OUT_SHIFT) |
GPIO IN/OUT Register bit mask
| #define BOARD_TPS65941_GPIO2_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO2_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_GPIO3_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO3_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_GPIO4_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO4_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_GPIO5_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO5_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_GPIO6_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO6_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_GPIO7_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO7_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_GPIO8_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO8_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_GPIO9_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO9_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_GPIO10_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO10_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_GPIO11_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO11_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_NPWRON_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_IN_OUT_SHIFT) |
| #define BOARD_TPS65941_BUCK_VSEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_BUCK_VSEL_SHIFT) |
BUCK Power resource bit mask
| #define BOARD_TPS65941_BUCK_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_BUCK_EN_SHIFT) |
| #define BOARD_TPS65941_BUCK_ILIM_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_BUCK_ILIM_SHIFT) |
| #define BOARD_TPS65941_LDO_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_LDO_EN_SHIFT) |
LDO Power resource bit mask
| #define BOARD_TPS65941_BUCK_VSET_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_BUCK_VSET_SHIFT) |
BUCK Voltage set bit mask
| #define BOARD_TPS65941_LDO_123_VSET_BIT_MASK (uint8_t)(0x3F << BOARD_TPS65941_LDO_123_VSET_SHIFT) |
LDO Voltage set bit mask
| #define BOARD_TPS65941_LDO4_VSET_BIT_MASK (uint8_t)(0x3F << BOARD_TPS65941_LDO4_VSET_SHIFT) |
| #define BOARD_TPS65941_PWR_VMON_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PWR_VMON_EN_SHIFT) |
Power resource voltage monitor set bit mask
| #define BOARD_TPS65941_PWR_UV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_PWR_UV_THR_SHIFT) |
Power resource PG Window set bit mask
| #define BOARD_TPS65941_PWR_OV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_PWR_OV_THR_SHIFT) |
| #define BOARD_TPS65941_BUCK1_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK1_PG_SEL_SHIFT) |
Voltage monitor set bit mask
| #define BOARD_TPS65941_BUCK2_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK2_PG_SEL_SHIFT) |
| #define BOARD_TPS65941_BUCK3_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK3_PG_SEL_SHIFT) |
| #define BOARD_TPS65941_BUCK4_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK4_PG_SEL_SHIFT) |
| #define BOARD_TPS65941_BUCK5_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK5_PG_SEL_SHIFT) |
| #define BOARD_TPS65941_LDO1_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO1_PG_SEL_SHIFT) |
| #define BOARD_TPS65941_LDO2_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO2_PG_SEL_SHIFT) |
| #define BOARD_TPS65941_LDO3_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO3_PG_SEL_SHIFT) |
| #define BOARD_TPS65941_LDO4_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO4_PG_SEL_SHIFT) |
| #define BOARD_TPS65941_VCCA_VMON_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_VCCA_VMON_EN_SHIFT) |
VCCA voltage monitor set bit mask
| #define BOARD_TPS65941_VCCA_PG_SET_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_VCCA_PG_SET_SHIFT) |
| #define BOARD_TPS65941_VCCA_UV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_VCCA_UV_THR_SHIFT) |
| #define BOARD_TPS65941_VCCA_OV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_VCCA_OV_THR_SHIFT) |
| #define BOARD_TPS65941_TWARN_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TWARN_STAT_SHIFT) |
Status register bit mask
| #define BOARD_TPS65941_TSD_ORD_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TSD_ORD_STAT_SHIFT) |
| #define BOARD_TPS65941_TSD_IMM_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TSD_IMM_STAT_SHIFT) |
| #define BOARD_TPS65941_PGOOD_WINDOW_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_WINDOW_SHIFT) |
PGOOD signal bit mask
| #define BOARD_TPS65941_PGOOD_POL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_POL_SHIFT) |
| #define BOARD_TPS65941_PGOOD_NRSTOUT_SOC_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_NRSTOUT_SOC_SHIFT) |
| #define BOARD_TPS65941_PGOOD_NRSTOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_NRSTOUT_SHIFT) |
| #define BOARD_TPS65941_PGOOD_TDIE_WARN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_TDIE_WARN_SHIFT) |
| #define BOARD_TPS65941_PGOOD_VCCA_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_VCCA_SEL_SHIFT) |
| #define BOARD_TPS65941_TWARN_LVL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TWARN_LVL_SHIFT) |
Thermal threshold value bit mask
| #define BOARD_TPS65941_ESM_START_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_START_SHIFT) |
ESM bit mask
| #define BOARD_TPS65941_ESM_DLY1_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_DLY1_SHIFT) |
| #define BOARD_TPS65941_ESM_DLY2_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_DLY2_SHIFT) |
| #define BOARD_TPS65941_ESM_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_MODE_SHIFT) |
| #define BOARD_TPS65941_ESM_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_EN_SHIFT) |
| #define BOARD_TPS65941_ESM_ERR_THR_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_ESM_ERR_THR_SHIFT) |
| #define BOARD_TPS65941_ESM_HMAX_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_HMAX_SHIFT) |
| #define BOARD_TPS65941_ESM_HMIN_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_HMIN_SHIFT) |
| #define BOARD_TPS65941_ESM_LMAX_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_LMAX_SHIFT) |
| #define BOARD_TPS65941_ESM_LMIN_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_LMIN_SHIFT) |
| #define BOARD_TPS65941_ESM_ERR_CNT_BIT_MASK (uint8_t)(0x1F << BOARD_TPS65941_ESM_ERR_CNT_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_SEC_1_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_ALRM_SEC_1_SHIFT) |
RTC and alarm time and date bit mask
| #define BOARD_TPS65941_RTC_ALRM_SEC_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_SEC_0_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_MIN_1_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_ALRM_MIN_1_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_MIN_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_MIN_0_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_AM_PM_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_ALRM_AM_PM_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_HR_1_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_RTC_ALRM_HR_1_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_HR_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_HR_0_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_DAY_1_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_RTC_ALRM_DAY_1_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_DAY_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_DAY_0_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_MON_1_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_ALRM_MON_1_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_MON_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_MON_0_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_YR_1_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_YR_1_SHIFT) |
| #define BOARD_TPS65941_RTC_ALRM_YR_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_YR_0_SHIFT) |
| #define BOARD_TPS65941_RTC_WEEK_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_WEEK_SHIFT) |
| #define BOARD_TPS65941_RTC_REG_OPT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_REG_OPT_SHIFT) |
RTC CTRL bit mask
| #define BOARD_TPS65941_GET_TIME_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GET_TIME_SHIFT) |
| #define BOARD_TPS65941_HOUR_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_HOUR_MODE_SHIFT) |
| #define BOARD_TPS65941_ROUND_30S_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ROUND_30S_SHIFT) |
| #define BOARD_TPS65941_STOP_RTC_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_STOP_RTC_SHIFT) |
| #define BOARD_TPS65941_ALRM_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ALRM_STAT_SHIFT) |
RTC Status bit mask
| #define BOARD_TPS65941_TIMER_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TIMER_STAT_SHIFT) |
| #define BOARD_TPS65941_RUN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RUN_SHIFT) |
| #define BOARD_TPS65941_ALARM_INTR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ALARM_INTR_SHIFT) |
RTC Interrupt bit mask
| #define BOARD_TPS65941_TIMER_INTR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TIMER_INTR_SHIFT) |
| #define BOARD_TPS65941_TIMER_PERIOD_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_TIMER_PERIOD_SHIFT) |
RTC Timer period bit mask
| #define BOARD_TPS65941_WDT_ANSW_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_WDT_ANSW_SHIFT) |
WDT configuration bit fields
| #define BOARD_TPS65941_WDT_ANSW_CNT_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_WDT_ANSW_CNT_SHIFT) |
| #define BOARD_TPS65941_WDT_QUES_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_WDT_QUES_SHIFT) |
| #define BOARD_TPS65941_WDT_WIN1_CFG_BIT_MASK (uint8_t)(0x7F << BOARD_TPS65941_WDT_WIN1_CFG_SHIFT) |
| #define BOARD_TPS65941_WDT_WIN2_CFG_BIT_MASK (uint8_t)(0x7F << BOARD_TPS65941_WDT_WIN2_CFG_SHIFT) |
| #define BOARD_TPS65941_WDT_LONGWIN_CFG_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_WDT_LONGWIN_CFG_SHIFT) |
| #define BOARD_TPS65941_WDT_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_MODE_SHIFT) |
| #define BOARD_TPS65941_WDT_LONGWIN_RET_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_LONGWIN_RET_SHIFT) |
| #define BOARD_TPS65941_WDT_RST_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_RST_STAT_SHIFT) |
WDT Error status bit fields
| #define BOARD_TPS65941_WDT_FAIL_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FAIL_STAT_SHIFT) |
| #define BOARD_TPS65941_WDT_ANSW_ERR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_ANSW_ERR_SHIFT) |
| #define BOARD_TPS65941_WDT_SEQ_ERR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_SEQ_ERR_SHIFT) |
| #define BOARD_TPS65941_WDT_ANSW_ERLY_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_ANSW_ERLY_SHIFT) |
| #define BOARD_TPS65941_WDT_TRIG_ERLY_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_TRIG_ERLY_SHIFT) |
| #define BOARD_TPS65941_WDT_TIMEOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_TIMEOUT_SHIFT) |
| #define BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_SHIFT) |
| #define BOARD_TPS65941_WDT_RST_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_RST_EN_SHIFT) |
WDT Threshold bit fields
| #define BOARD_TPS65941_WDT_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_EN_SHIFT) |
| #define BOARD_TPS65941_WDT_FAIL_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_WDT_FAIL_THR_SHIFT) |
| #define BOARD_TPS65941_WDT_RST_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_WDT_RST_THR_SHIFT) |
| #define BOARD_TPS65941_WDT_BAD_EVT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_BAD_EVT_SHIFT) |
WDT Fail count bit fields
| #define BOARD_TPS65941_WDT_FIRST_OK_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FIRST_OK_SHIFT) |
| #define BOARD_TPS65941_WDT_FAIL_CNT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FAIL_CNT_SHIFT) |
| #define BOARD_TPS65941_DISABLE (0U) |
GPIO functionality enable/disable
| #define BOARD_TPS65941_ENABLE (1U) |
| #define BOARD_TPS65941_PULLUP_DOWN (0U) |
GPIO type
| #define BOARD_TPS65941_OPEN_DRAIN (1U) |
| #define BOARD_TPS65941_GPIO_LOW (0U) |
GPIO signal level
| #define BOARD_TPS65941_GPIO_HIGH (1U) |
| #define BOARD_TPS65941_GPIO_DIR_IN (0U) |
GPIO Direction
| #define BOARD_TPS65941_GPIO_DIR_OUT (1U) |
| #define BOARD_TPS65941_GPIO_MODE (0x0U) |
| #define BOARD_TPS65941_GPIO_PIN_MAX (11U) |
| #define BOARD_TPS65941_NPWRON_PIN (0) |
| #define BOARD_TPS65941_BUCK1_RESOURCE (0U) |
TPS65941 Power resource
| #define BOARD_TPS65941_BUCK2_RESOURCE (1U) |
| #define BOARD_TPS65941_BUCK3_RESOURCE (2U) |
| #define BOARD_TPS65941_BUCK4_RESOURCE (3U) |
| #define BOARD_TPS65941_BUCK5_RESOURCE (4U) |
| #define BOARD_TPS65941_LDO1_RESOURCE (5U) |
| #define BOARD_TPS65941_LDO2_RESOURCE (6U) |
| #define BOARD_TPS65941_LDO3_RESOURCE (7U) |
| #define BOARD_TPS65941_LDO4_RESOURCE (8U) |
| #define BOARD_TPS65941_INTR_TYPE_BUCK_ERR (0U) |
Interrupt type
| #define BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR (1U) |
| #define BOARD_TPS65941_INTR_TYPE_SEVERE_ERR (2U) |
| #define BOARD_TPS65941_INTR_TYPE_MODERATE_ERR (3U) |
| #define BOARD_TPS65941_INTR_TYPE_MISC_WARN (4U) |
| #define BOARD_TPS65941_INTR_TYPE_STARTUP_SRC (5U) |
| #define BOARD_TPS65941_INTR_TYPE_GPIO (6U) |
| #define BOARD_TPS65941_INTR_TYPE_FSM_ERR (7U) |
| #define BOARD_TPS65941_INTR_ID_BUCK1_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x00U) |
Interrupt IDs
| #define BOARD_TPS65941_INTR_ID_BUCK1_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x01U) |
| #define BOARD_TPS65941_INTR_ID_BUCK1_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x02U) |
| #define BOARD_TPS65941_INTR_ID_BUCK1_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x03U) |
| #define BOARD_TPS65941_INTR_ID_BUCK2_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x04U) |
| #define BOARD_TPS65941_INTR_ID_BUCK2_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x05U) |
| #define BOARD_TPS65941_INTR_ID_BUCK2_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x06U) |
| #define BOARD_TPS65941_INTR_ID_BUCK2_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x07U) |
| #define BOARD_TPS65941_INTR_ID_BUCK3_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x08U) |
| #define BOARD_TPS65941_INTR_ID_BUCK3_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x09U) |
| #define BOARD_TPS65941_INTR_ID_BUCK3_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x0AU) |
| #define BOARD_TPS65941_INTR_ID_BUCK3_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0BU) |
| #define BOARD_TPS65941_INTR_ID_BUCK4_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0CU) |
| #define BOARD_TPS65941_INTR_ID_BUCK4_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0DU) |
| #define BOARD_TPS65941_INTR_ID_BUCK4_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x0EU) |
| #define BOARD_TPS65941_INTR_ID_BUCK4_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0FU) |
| #define BOARD_TPS65941_INTR_ID_BUCK5_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x10U) |
| #define BOARD_TPS65941_INTR_ID_BUCK5_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x11U) |
| #define BOARD_TPS65941_INTR_ID_BUCK5_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x12U) |
| #define BOARD_TPS65941_INTR_ID_BUCK5_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x13U) |
| #define BOARD_TPS65941_INTR_ID_LDO1_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x00U) |
| #define BOARD_TPS65941_INTR_ID_LDO1_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x01U) |
| #define BOARD_TPS65941_INTR_ID_LDO1_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x02U) |
| #define BOARD_TPS65941_INTR_ID_LDO1_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x03U) |
| #define BOARD_TPS65941_INTR_ID_LDO2_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x04U) |
| #define BOARD_TPS65941_INTR_ID_LDO2_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x05U) |
| #define BOARD_TPS65941_INTR_ID_LDO2_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x06U) |
| #define BOARD_TPS65941_INTR_ID_LDO2_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x07U) |
| #define BOARD_TPS65941_INTR_ID_LDO3_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x08U) |
| #define BOARD_TPS65941_INTR_ID_LDO3_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x09U) |
| #define BOARD_TPS65941_INTR_ID_LDO3_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x0AU) |
| #define BOARD_TPS65941_INTR_ID_LDO3_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0BU) |
| #define BOARD_TPS65941_INTR_ID_LDO4_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0CU) |
| #define BOARD_TPS65941_INTR_ID_LDO4_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0DU) |
| #define BOARD_TPS65941_INTR_ID_LDO4_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x0EU) |
| #define BOARD_TPS65941_INTR_ID_LDO4_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0FU) |
| #define BOARD_TPS65941_INTR_ID_VCCA_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x10U) |
| #define BOARD_TPS65941_INTR_ID_VCCA_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x11U) |
| #define BOARD_TPS65941_INTR_ID_GPIO1_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x00U) |
| #define BOARD_TPS65941_INTR_ID_GPIO2_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x01U) |
| #define BOARD_TPS65941_INTR_ID_GPIO3_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x02U) |
| #define BOARD_TPS65941_INTR_ID_GPIO4_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x03U) |
| #define BOARD_TPS65941_INTR_ID_GPIO5_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x04U) |
| #define BOARD_TPS65941_INTR_ID_GPIO6_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x05U) |
| #define BOARD_TPS65941_INTR_ID_GPIO7_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x06U) |
| #define BOARD_TPS65941_INTR_ID_GPIO8_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x07U) |
| #define BOARD_TPS65941_INTR_ID_GPIO9_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x10U) |
| #define BOARD_TPS65941_INTR_ID_GPIO10_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x11U) |
| #define BOARD_TPS65941_INTR_ID_GPIO11_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x12U) |
| #define BOARD_TPS65941_INTR_ID_GPIO1_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x08U) |
| #define BOARD_TPS65941_INTR_ID_GPIO2_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x09U) |
| #define BOARD_TPS65941_INTR_ID_GPIO3_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0AU) |
| #define BOARD_TPS65941_INTR_ID_GPIO4_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0BU) |
| #define BOARD_TPS65941_INTR_ID_GPIO5_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0CU) |
| #define BOARD_TPS65941_INTR_ID_GPIO6_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0DU) |
| #define BOARD_TPS65941_INTR_ID_GPIO7_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0EU) |
| #define BOARD_TPS65941_INTR_ID_GPIO8_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0FU) |
| #define BOARD_TPS65941_INTR_ID_GPIO9_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x13U) |
| #define BOARD_TPS65941_INTR_ID_GPIO10_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x14U) |
| #define BOARD_TPS65941_INTR_ID_GPIO11_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x15U) |
| #define BOARD_TPS65941_INTR_ID_FSD ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (0 << 8) | 0x04U) |
| #define BOARD_TPS65941_INTR_ID_RTC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (1 << 8) | 0x02U) |
| #define BOARD_TPS65941_INTR_ID_ENABLE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (0 << 8) | 0x01U) |
| #define BOARD_TPS65941_INTR_ID_NPWRON_START ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (0 << 8) | 0x00U) |
| #define BOARD_TPS65941_INTR_ID_TWARN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) | (0 << 8) | 0x03U) |
| #define BOARD_TPS65941_INTR_ID_EXT_CLK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) | (0 << 8) | 0x01U) |
| #define BOARD_TPS65941_INTR_ID_BIST_PASS ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) | (0 << 8) | 0x00U) |
| #define BOARD_TPS65941_INTR_ID_RECOV_CNT ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (1 << 8) | 0x06U) |
| #define BOARD_TPS65941_INTR_ID_NPWRON_LONG ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x05U) |
| #define BOARD_TPS65941_INTR_ID_SPMI_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x04U) |
| #define BOARD_TPS65941_INTR_ID_PFSM_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x03U) |
| #define BOARD_TPS65941_INTR_ID_REG_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x02U) |
| #define BOARD_TPS65941_INTR_ID_BIST_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x01U) |
| #define BOARD_TPS65941_INTR_ID_TSD_ORD ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (1 << 8) | 0x00U) |
| #define BOARD_TPS65941_INTR_ID_VCCA_OVP ((((uint32_t)BOARD_TPS65941_INTR_TYPE_SEVERE_ERR) << 16) | (1 << 8) | 0x01U) |
| #define BOARD_TPS65941_INTR_ID_TSD_IMM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_SEVERE_ERR) << 16) | (1 << 8) | 0x00U) |
| #define BOARD_TPS65941_INTR_ID_IMM_SHUTDOWN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x00U) |
| #define BOARD_TPS65941_INTR_ID_ORD_SHUTDOWN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x01U) |
| #define BOARD_TPS65941_INTR_ID_MCU_PWR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x02U) |
| #define BOARD_TPS65941_INTR_ID_SOC_PWR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x03U) |
| #define BOARD_TPS65941_INTR_ID_COMM_FRM_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x08U) |
| #define BOARD_TPS65941_INTR_ID_COMM_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x09U) |
| #define BOARD_TPS65941_INTR_ID_COMM_ADR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x0BU) |
| #define BOARD_TPS65941_INTR_ID_I2C2_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x0DU) |
| #define BOARD_TPS65941_INTR_ID_I2C2_ADR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x0FU) |
| #define BOARD_TPS65941_INTR_ID_EN_DRV_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x10U) |
| #define BOARD_TPS65941_INTR_ID_NINT_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x11U) |
| #define BOARD_TPS65941_INTR_ID_NRSTOUT_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x12U) |
| #define BOARD_TPS65941_INTR_ID_NRSTOUT_SOC_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x13U) |
| #define BOARD_TPS65941_INTR_ID_ESM_SOC_PIN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x18U) |
| #define BOARD_TPS65941_INTR_ID_ESM_SOC_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x19U) |
| #define BOARD_TPS65941_INTR_ID_ESM_SOC_RST ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1AU) |
| #define BOARD_TPS65941_INTR_ID_ESM_MCU_PIN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1BU) |
| #define BOARD_TPS65941_INTR_ID_ESM_MCU_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1CU) |
| #define BOARD_TPS65941_INTR_ID_ESM_MCU_RST ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1DU) |
| #define BOARD_TPS65941_INTR_REG_WIDTH (0x8U) |
| #define BOARD_TPS65941_INTR_ENABLE (0) |
Interrupt Enable/Disable
| #define BOARD_TPS65941_INTR_DISABLE (1) |
| #define BOARD_TPS65941_INTR_SET (1) |
Interrupt Set/UnSet
| #define BOARD_TPS65941_INTR_UNSET (0) |
| #define BOARD_TPS65941_PG_3V3_LEVEL (0) |
Voltage monitor PGOOD level values
| #define BOARD_TPS65941_PG_5V_LEVEL (1) |
| #define BOARD_TPS65941_PG_THR_3_PERCENT (0x0U) |
Voltage monitor PGOOD threshold values
| #define BOARD_TPS65941_PG_THR_3_5_PERCENT (0x1U) |
| #define BOARD_TPS65941_PG_THR_4_PERCENT (0x2U) |
| #define BOARD_TPS65941_PG_THR_5_PERCENT (0x3U) |
| #define BOARD_TPS65941_PG_THR_6_PERCENT (0x4U) |
| #define BOARD_TPS65941_PG_THR_7_PERCENT (0x5U) |
| #define BOARD_TPS65941_PG_THR_8_PERCENT (0x6U) |
| #define BOARD_TPS65941_PG_THR_10_PERCENT (0x7U) |
| #define BOARD_TPS65941_ILIM_2_5A (0x2U) |
Peak Current limit of BUCK power resources
| #define BOARD_TPS65941_ILIM_3_5A (0x3U) |
| #define BOARD_TPS65941_ILIM_4_5A (0x4U) |
| #define BOARD_TPS65941_ILIM_5_5A (0x5U) |
| #define BOARD_TPS65941_OV_UV_DISABLE (0) |
Voltage monitor OV and UV Enable/Disable
| #define BOARD_TPS65941_OV_UV_ENABLE (1) |
| #define BOARD_TPS65941_PGOOD_MASK (0U) |
PGOOD Mask Enable/Disable
| #define BOARD_TPS65941_PGOOD_UNMASK (1U) |
| #define BOARD_TPS65941_UV_MONITOR (0U) |
PGOOD Window Value
| #define BOARD_TPS65941_UV_OV_MONITOR (1U) |
| #define BOARD_TPS65941_TDIE_NO_WARN (0) |
Thermal error status value
| #define BOARD_TPS65941_TDIE_WARN (1) |
| #define BOARD_TPS65941_TDIE_WARN_ORD_SD (2) |
| #define BOARD_TPS65941_TDIE_WARN_IMM_SD (3) |
| #define BOARD_TPS65941_THERMAL_TEMP_120C (0x0U) |
Thermal threshold value
| #define BOARD_TPS65941_THERMAL_TEMP_130C (0x1U) |
| #define BOARD_TPS65941_ESM_STOP (0x0) |
ESM Start/Stop value
| #define BOARD_TPS65941_ESM_START (0x1) |
| #define BOARD_TPS65941_ESM_DISABLE (0x0) |
ESM Enable/Disable value
| #define BOARD_TPS65941_ESM_ENABLE (0x1) |
| #define BOARD_TPS65941_SECOND_INTR_PERIOD (0x0U) |
RTC timer Periods
| #define BOARD_TPS65941_MINUTE_INTR_PERIOD (0x1U) |
| #define BOARD_TPS65941_HOUR_INTR_PERIOD (0x2U) |
| #define BOARD_TPS65941_DAY_INTR_PERIOD (0x3U) |
| #define BOARD_TPS65941_ALARM_INTR_ENABLE (0x1U) |
RTC alarm and timer interrupt
| #define BOARD_TPS65941_ALARM_INTR_DISABLE (0x0U) |
| #define BOARD_TPS65941_TIMER_INTR_ENABLE (0x1U) |
| #define BOARD_TPS65941_TIMER_INTR_DISABLE (0x0U) |
| #define BOARD_TPS65941_WDT_DISABLE (0x1U) |
Watchdog timer Mode
| #define BOARD_TPS65941_WDT_ENABLE (0x0U) |
| #define BOARD_TPS65941_WDT_TRIGGER_MODE (0x0U) |
Watchdog config mode
| #define BOARD_TPS65941_WDT_QA_MODE (0x1U) |
| #define BOARD_TPS65941_WDT_RST_DISABLE (0x0U) |
Watchdog reset Enable/Disable
| #define BOARD_TPS65941_WDT_RST_ENABLE (0x1U) |
| #define BOARD_TPS65941_ESM_SOC (0x0U) |
ESM configuration
| #define BOARD_TPS65941_ESM_MCU (0x1U) |
| #define BOARD_TPS65941_ESM_LEVEL_MODE (0x0U) |
ESM configuration mode
| #define BOARD_TPS65941_ESM_PWM_MODE (0x1U) |
| #define BOARD_TPS65941_12_HOUR_MODE (1) |
RTC time mode
| #define BOARD_TPS65941_24_HOUR_MODE (0) |
| #define BOARD_TPS65941_AM_MODE (0) |
RTC Meridien mode
| #define BOARD_TPS65941_PM_MODE (1) |
| #define BOARD_TPS65941_SUNDAY (0) |
RTC Week days
| #define BOARD_TPS65941_MONDAY (1) |
| #define BOARD_TPS65941_TUESDAY (2) |
| #define BOARD_TPS65941_WEDNESDAY (3) |
| #define BOARD_TPS65941_THURSDAY (4) |
| #define BOARD_TPS65941_FRIDAY (5) |
| #define BOARD_TPS65941_SATURDAY (6) |
| #define BOARD_TPS65941_RTC_FROZEN (0) |
RTC State
| #define BOARD_TPS65941_RTC_START (1) |
| #define BOARD_TPS65941_WDT_RST_INT (0) |
WDT Error status values
| #define BOARD_TPS65941_WDT_FAIL_INT (1) |
| #define BOARD_TPS65941_WDT_ANSW_ERR (2) |
| #define BOARD_TPS65941_WDT_SEQ_ERR (3) |
| #define BOARD_TPS65941_WDT_ANSW_ERLY_ERR (4) |
| #define BOARD_TPS65941_WDT_TRIG_ERLY_ERR (5) |
| #define BOARD_TPS65941_WDT_TIMEOUT_ERR (6) |
| #define BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_ERR (7) |
| #define BOARD_TPS65941_WDT_ERR_LATCHED (1) |
| #define BOARD_TPS65941_WDT_NO_ERR (0) |
| #define BOARD_I2C_NUM_OF_BYTES_01 (1U) |
I2C number of bytes
1.8.11 
