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PDK API Guide for J721E
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Data types used by DS90UB941 FPD-Link device library.
| #define BOARD_FPD_UB941_I2C_INSTANCE (0x00U) /* TBD */ |
ub941 serializer i2c instance number
| #define BOARD_FPD_UB941_I2C_SLV_ADDR (0x00U) /* TBD */ |
ub941 serializer i2c slave address
| #define BOARD_FPD_UB941_RESET_CTL_REG_ADDR (0x01U) |
memory-mapped registers for the DS90UB941AS-Q1[Main Registers RESET control register address
| #define BOARD_FPD_UB941_DEVICE_CFG_REG_ADDR (0x02U) |
Device configuration register address
| #define BOARD_FPD_UB941_GENERAL_CFG_REG_ADDR (0x03U) |
Generatl configuration register address
| #define BOARD_FPD_UB941_DES_ID_REG_ADDR (0x06U) |
Deserializer ID register address
| #define BOARD_FPD_UB941_SLAVE_ID0_REG_ADDR (0x07U) |
Slave ID0 register address
| #define BOARD_FPD_UB941_SLAVE_ID1_REG_ADDR (0x70U) |
Slave ID1 register address
| #define BOARD_FPD_UB941_SLAVE_ID2_REG_ADDR (0x71U) |
Slave ID2 register address
| #define BOARD_FPD_UB941_SLAVE_ID3_REG_ADDR (0x72U) |
Slave ID3 register address
| #define BOARD_FPD_UB941_SLAVE_ID4_REG_ADDR (0x73U) |
Slave ID4 register address
| #define BOARD_FPD_UB941_SLAVE_ID5_REG_ADDR (0x74U) |
Slave ID5 register address
| #define BOARD_FPD_UB941_SLAVE_ID6_REG_ADDR (0x75U) |
Slave ID6 register address
| #define BOARD_FPD_UB941_SLAVE_ID7_REG_ADDR (0x76U) |
Slave ID7 register address
| #define BOARD_FPD_UB941_SLAVE_ALIAS_0_REG_ADDR (0x08U) |
Slave Alias0 register address
| #define BOARD_FPD_UB941_SLAVE_ALIAS_1_REG_ADDR (0x77U) |
Slave Alias1 register address
| #define BOARD_FPD_UB941_SLAVE_ALIAS_2_REG_ADDR (0x78U) |
Slave Alias2 register address
| #define BOARD_FPD_UB941_SLAVE_ALIAS_3_REG_ADDR (0x79U) |
Slave Alias3 register address
| #define BOARD_FPD_UB941_SLAVE_ALIAS_4_REG_ADDR (0x7AU) |
Slave Alias4 register address
| #define BOARD_FPD_UB941_SLAVE_ALIAS_5_REG_ADDR (0x7BU) |
Slave Alias5 register address
| #define BOARD_FPD_UB941_SLAVE_ALIAS_6_REG_ADDR (0x7CU) |
Slave Alias6 register address
| #define BOARD_FPD_UB941_SLAVE_ALIAS_7_REG_ADDR (0x7DU) |
Slave Alias7 register address
| #define BOARD_FPD_UB941_GENERAL_STS_REG_ADDR (0x0CU) |
General status register address
| #define BOARD_FPD_UB941_I2C_CONTROL_REG_ADDR (0x17U) |
I2C control register address
| #define BOARD_FPD_UB941_SCL_HIGH_TIME_REG_ADDR (0x18U) |
Serial clock high time register address
| #define BOARD_FPD_UB941_SCL_LOW_TIME_REG_ADDR (0x19U) |
Serial clock low time register address
| #define BOARD_FPD_UB941_TX_PORT_SEL_REG_ADDR (0x1EU) |
Transmission port register address
| #define BOARD_FPD_UB941_IND_ACC_CTL_REG_ADDR (0x40U) |
Indirect access control register address
| #define BOARD_FPD_UB941_IND_ACC_ADDR_REG_ADDR (0x41U) |
Indirect access address register address
| #define BOARD_FPD_UB941_IND_ADD_DATA_REG_ADDR (0x42U) |
Indirect access data register address
| #define BOARD_FPD_UB941_BRIDGE_CTL_REG_ADDR (0x4FU) |
Bridge control register address
| #define BOARD_FPD_UB941_BRIDGE_CFG_REG_ADDR (0x54U) |
Bridge configuraiton register address
| #define BOARD_FPD_UB941_BRIDGE_CFG2_REG_ADDR (0x56U) |
Bridge configuraiton2 register address
| #define BOARD_FPD_UB941_DUAL_STS_DUAL_STS_P1_REG_ADDR (0x5AU) |
Dual status P1 register address
| #define BOARD_FPD_UB941_DUAL_CTL1_REG_ADDR (0x5BU) |
Dual control1 register address
| #define BOARD_FPD_UB941_DUAL_CTL2_REG_ADDR (0x5CU) |
Dual control2 register address
| #define BOARD_FPD_UB941_PGCTL_PGCTL_P1_REG_ADDR (0x64U) |
Pattern generation control P1 register address
| #define BOARD_FPD_UB941_PGCFG_PGCFG_P1_REG_ADDR (0x65U) |
Pattern generation configuration P1 register address
| #define BOARD_FPD_UB941_PGIA_PGIA_P1_REG_ADDR (0x66U) |
Pattern generation indirect address register address
| #define BOARD_FPD_UB941_PGID_PGID_P1_REG_ADDR (0x67U) |
Pattern generation indirect data register address
| #define BOARD_FPD_UB941_DPHY_SKIP_TIMING_REG_ADDR (0x05U) |
DPHY skip timing register address
| #define BOARD_FPD_UB941_DSI_CONFIG_1_REG_ADDR (0x21U) |
DSI config1 register address
| #define BOARD_FPD_UB941_PGCDC1_REG_ADDR (0x03U) |
Pattern generation clock divider configuration register address
| #define BOARD_FPD_UB941_PGTFS1_REG_ADDR (0x04U) |
Pattern generation total frame sync1 register address
| #define BOARD_FPD_UB941_PGTFS2_REG_ADDR (0x05U) |
Pattern generation total frame sync2 register address
| #define BOARD_FPD_UB941_PGTFS3_REG_ADDR (0x06U) |
Pattern generation total frame sync3 register address
| #define BOARD_FPD_UB941_PGAFS1_REG_ADDR (0x07U) |
Pattern generation active frame sync1 register address
| #define BOARD_FPD_UB941_PGAFS2_REG_ADDR (0x08U) |
Pattern generation active frame sync2 register address
| #define BOARD_FPD_UB941_PGAFS3_REG_ADDR (0x09U) |
Pattern generation active frame sync3 register address
| #define BOARD_FPD_UB941_PGHBP_REG_ADDR (0x0CU) |
Pattern generation horizontal back porch register address
| #define BOARD_FPD_UB941_PGVBP_REG_ADDR (0x0DU) |
Pattern generation vertical back porch register address
| #define BOARD_FPD_UB941_ACT_HOR_WIDTH_REG_ADDR (0x20U) |
Active horizontal width register address
| #define BOARD_FPD_UB941_ACT_VER_AND_HOR_WIDTH_REG_ADDR (0x03U) |
Active vertical width register address
| #define BOARD_FPD_UB941_TOT_VER_WIDTH_REG_ADDR (0x09U) |
Total vertical width register address
| #define BOARD_FPD_UB941_TOT_VER_AND_HOR_WIDTH_REG_ADDR (0xD4U) |
Total vertical and horizontal width register address Total vertical and horizontal width register address
| #define BOARD_FPD_UB941_TOT_HOR_AND_VER_WIDTH_REG_ADDR (0x20U) |
Active horizontal width register address
| #define BOARD_FPD_UB941_HOR_BACK_PORCH_WIDTH_REG_ADDR (0xD8U) |
Active horizontal width register address
| #define BOARD_FPD_UB941_VER_BACK_PORCH_WIDTH_REG_ADDR (0x23U) |
Active horizontal width register address
| #define BOARD_FPD_UB941_DISABLE_DSI_SHIFT_CNT (3U) |
RESET_CTL Register Fields Disable DSI field shift count
| #define BOARD_FPD_UB941_DIGITAL_RESET1_SHIFT_CNT (1U) |
Digital Reset1 field shift count
| #define BOARD_FPD_UB941_DIGITAL_RESET0_SHIFT_CNT (1U) |
Digital Reset0 field shift count
| #define BOARD_FPD_UB941_DSI1_CLK_PN_SWAP_SHIFT_CNT (6U) |
DEVICE_CFG Register Fields DSI1 clock P/N field shift count
| #define BOARD_FPD_UB941_DSI1_DATA_PN_SWAP_SHIFT_CNT (5U) |
DSI1 data P/N field shift count
| #define BOARD_FPD_UB941_DSI0_CLK_PN_SWAP_SHIFT_CNT (2U) |
DSI0 clock P/N field shift count
| #define BOARD_FPD_UB941_DSI0_DATA_PN_SWAP_SHIFT_CNT (1U) |
DSI0 data P/N field shift count
| #define BOARD_FPD_UB941_IND_ACC_SEL_SHIFT_CNT (2U) |
IND_ACC_CTL Register Fields Indirect access select field shift count
| #define BOARD_FPD_UB941_IND_ACC_READ_SHIFT_CNT (0U) |
Indirect access read field shift count
| #define BOARD_FPD_UB941_DSI_BYTES_PER_PIXEL_SHIFT_CNT (4U) |
BRIDGE_CFG Register Fields DSI bytes per pixel field shift count
| #define BOARD_FPD_UB941_BRIDGE_LANE_MODE_SHIFT_CNT (2U) |
BRIDGE_CFG2 Register Fields Bridge clock mode field shift count
| #define BOARD_FPD_UB941_FREQ_STBL_THR_SHIFT_CNT (3U) |
DUAL_CTL2 Register Fields Frequency stability threshold field shift count
| #define BOARD_FPD_UB941_FPD3_LINK_RDY_SHIFT_CNT (7U) |
DUAL_STS_DUAL_STS_P1 Register Fields FPD Link3 ready status field shift count
| #define BOARD_FPD_UB941_FPD3_TX_STS_SHIFT_CNT (6U) |
FPD Link3 transmit status field shift count
| #define BOARD_FPD_UB941_DSI_CLK_DET_SHIFT_CNT (3U) |
DSI clock detect field shift count
| #define BOARD_FPD_UB941_NO_DSI_CLK_SHIFT_CNT (1U) |
No DSI clock detect field shift count
| #define BOARD_FPD_UB941_FREQ_STABLE_SHIFT_CNT (0U) |
DSI stable frequency detect field shift count
| #define BOARD_FPD_UB941_RX_CRC_CHECKER_ENABLE_SHIFT_CNT (7U) |
GENERAL_CFG Register Filed Receive CRC checker enable field shift count
| #define BOARD_FPD_UB941_FILTER_ENABLE_SHIFT_CNT (4U) |
Filter enable field shift count
| #define BOARD_FPD_UB941_I2C_PASS_THROUGH_SHIFT_CNT (3U) |
I2C pass through field shift count
| #define BOARD_FPD_UB941_PCLK_AUTO_SHIFT_CNT (1U) |
PCLK auto switch field shift count
| #define BOARD_FPD_UB941_FREEZE_DEV_ID_SHIFT_CNT (0U) |
DES_ID_DES_ID Register Filed Freeze device id field shift count
| #define BOARD_FPD_UB941_DSI_ERROR_SHIFT_CNT (6U) |
GENERAL_STS Register Filed DSI Error field shift count
| #define BOARD_FPD_UB941_DPHY_ERROR_SHIFT_CNT (5U) |
DPHY Error field shift count
| #define BOARD_FPD_UB941_LINK_LOST_SHIFT_CNT (4U) |
Link lost field shift count
| #define BOARD_FPD_UB941_BIST_CRC_ERROR_SHIFT_CNT (3U) |
Built In Self Test CRC field shift count
| #define BOARD_FPD_UB941_PCLK_DETECT_SHIFT_CNT (2U) |
PCLK detect field shift count
| #define BOARD_FPD_UB941_DES_ERROR_SHIFT_CNT (1U) |
Deserailizer error field shift count
| #define BOARD_FPD_UB941_LINK_DETECT_SHIFT_CNT (0U) |
Link detect field shift count
| #define BOARD_FPD_UB941_I2C_PASS_ALL_SHIFT_CNT (7U) |
I2C_CONTROL Register Filed I2C pass all field shift count
| #define BOARD_FPD_UB941_PATTERN_GENERATOR_SHIFT_CNT (0U) |
Pattern generator field bit mask
| #define BOARD_FPD_UB941_COLORS_BAR_PATTERN_SEL_SHIFT_CNT (2U) |
Color bars pattern select shift count
| #define BOARD_FPD_UB941_PATTERN_SEL_SHIFT_CNT (4U) |
Pattern select shift count
| #define BOARD_FPD_UB941_AUTO_SCROLL_PATTERN_SHIFT_CNT (0U) |
Auto scroll Pattern field shift count
| #define BOARD_FPD_UB941_INVERTED_COLOR_PATTERN_SHIFT_CNT (1U) |
Inverted color Pattern field shift count
| #define BOARD_FPD_UB941_PG_18B_SHIFT_CNT (4U) |
Pattern generator 18-bit field shift count
| #define BOARD_FPD_UB941_PG_EXTCLK_SHIFT_CNT (5U) |
Pattern generator external clock field shift count
| #define BOARD_FPD_UB941_PG_TSEL_SHIFT_CNT (6U) |
Pattern generator timiing select field shift count
| #define BOARD_FPD_UB941_DISABLE_DSI_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DISABLE_DSI_SHIFT_CNT) |
DISABLE DSI field bit mask
| #define BOARD_FPD_UB941_DIGITAL_RESET1_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DIGITAL_RESET1_SHIFT_CNT) |
Digital reset1 field bit mask
| #define BOARD_FPD_UB941_DIGITAL_RESET0_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DIGITAL_RESET0_SHIFT_CNT) |
Digital reset0 field bit mask
| #define BOARD_FPD_UB941_DSI1_CLK_PN_SWAP_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DSI1_CLK_PN_SWAP_SHIFT_CNT) |
DSI1 clock P/N swap field bit mask
| #define BOARD_FPD_UB941_DSI1_DATA_PN_SWAP_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DSI1_DATA_PN_SWAP_SHIFT_CNT) |
DSI1 data P/N swap field bit mask
| #define BOARD_FPD_UB941_DSI0_CLK_PN_SWAP_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DSI0_CLK_PN_SWAP_SHIFT_CNT) |
DSI0 clock P/N swap field bit mask
| #define BOARD_FPD_UB941_DSI0_DATA_PN_SWAP_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DSI0_DATA_PN_SWAP_SHIFT_CNT) |
DSI0 data P/N swap field bit mask
| #define BOARD_FPD_UB941_IND_ACC_SEL_BIT_MASK (uint8_t)(0x07 << BOARD_FPD_UB941_IND_ACC_SEL_SHIFT_CNT) |
IND_ACC_CTL Register Fields Indirect access select field bit mask
| #define BOARD_FPD_UB941_IND_ACC_READ_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_IND_ACC_READ_SHIFT_CNT) |
Indirect access read field bit mask
| #define BOARD_FPD_UB941_RX_CRC_CHECKER_ENABLE_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_RX_CRC_CHECKER_ENABLE_SHIFT_CNT) |
GENERAL_CFG Register Filed Receive CRC checker enable field bit mask
| #define BOARD_FPD_UB941_FILTER_ENABLE_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_FILTER_ENABLE_SHIFT_CNT) |
Filter enable field bit mask
| #define BOARD_FPD_UB941_I2C_PASS_THROUGH_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_I2C_PASS_THROUGH_SHIFT_CNT) |
I2C pass through field bit mask
| #define BOARD_FPD_UB941_PCLK_AUTO_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_PCLK_AUTO_SHIFT_CNT) |
PCLK auto switch field bit mask
| #define BOARD_FPD_UB941_DSI_ERROR_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DSI_ERROR_SHIFT_CNT) |
GENERAL_STS Register Filed DSI Error field bit mask
| #define BOARD_FPD_UB941_DPHY_ERROR_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DPHY_ERROR_SHIFT_CNT) |
DPHY Error field bit mask
| #define BOARD_FPD_UB941_LINK_LOST_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_LINK_LOST_SHIFT_CNT) |
Link lost field bit mask
| #define BOARD_FPD_UB941_BIST_CRC_ERROR_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_BIST_CRC_ERROR_SHIFT_CNT) |
Built In Self Test CRC field bit mask
| #define BOARD_FPD_UB941_PCLK_DETECT_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_PCLK_DETECT_SHIFT_CNT) |
PCLK detect field bit mask
| #define BOARD_FPD_UB941_DES_ERROR_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DES_ERROR_SHIFT_CNT) |
Deserailizer error field bit mask
| #define BOARD_FPD_UB941_LINK_DETECT_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_LINK_DETECT_SHIFT_CNT) |
Link detect field bit mask
| #define BOARD_FPD_UB941_I2C_PASS_ALL_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_I2C_PASS_ALL_SHIFT_CNT) |
I2C_CONTROL Register Filed I2C pass all field bit mask
| #define BOARD_FPD_UB941_FREEZE_DEV_ID_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_FREEZE_DEV_ID_SHIFT_CNT) |
DES_ID_DES_ID Register Filed Freeze device id field bit mask
| #define BOARD_FPD_UB941_DSI_BYTES_PER_PIXEL_BIT_MASK (uint8_t)(0x03 << BOARD_FPD_UB941_DSI_BYTES_PER_PIXEL_SHIFT_CNT) |
BRIDGE_CFG Register Fields DSI bytes per pixel field bit mask
| #define BOARD_FPD_UB941_BRIDGE_LANE_MODE_BIT_MASK (uint8_t)(0x03 << BOARD_FPD_UB941_BRIDGE_LANE_MODE_SHIFT_CNT) |
BRIDGE_CFG2 Register Fields Bridge clock mode field bit mask
| #define BOARD_FPD_UB941_FREQ_STBL_THR_BIT_MASK (uint8_t)(0x03 << BOARD_FPD_UB941_FREQ_STBL_THR_SHIFT_CNT) |
DUAL_CTL2 Register Fields Frequency stability threshold field bit mask
| #define BOARD_FPD_UB941_FPD3_LINK_RDY_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_FPD3_LINK_RDY_SHIFT_CNT) |
DUAL_STS_DUAL_STS_P1 Register Fields FPD Link3 ready status field bit mask
| #define BOARD_FPD_UB941_FPD3_TX_STS_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_FPD3_TX_STS_SHIFT_CNT) |
FPD Link3 transmit status field bit mask
| #define BOARD_FPD_UB941_DSI_CLK_DET_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DSI_CLK_DET_SHIFT_CNT) |
DSI clock detect field bit mask
| #define BOARD_FPD_UB941_NO_DSI_CLK_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_NO_DSI_CLK_SHIFT_CNT) |
No DSI clock detect field bit mask
| #define BOARD_FPD_UB941_FREQ_STABLE_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_FREQ_STABLE_SHIFT_CNT) |
DSI stable frequency detect field bit mask
| #define BOARD_FPD_UB941_PATTERN_GENERATOR_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_PATTERN_GENERATOR_SHIFT_CNT) |
Pattern generator field bit mask
| #define BOARD_FPD_UB941_COLORS_BAR_PATTERN_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_COLORS_BAR_PATTERN_SEL_SHIFT_CNT) |
Color bars pattern select bit mask
| #define BOARD_FPD_UB941_PATTERN_SEL_BIT_MASK (uint8_t)(0x0F << BOARD_FPD_UB941_PATTERN_SEL_SHIFT_CNT) |
Pattern select bit mask
| #define BOARD_FPD_UB941_AUTO_SCROLL_PATTERN_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_AUTO_SCROLL_PATTERN_SHIFT_CNT) |
Auto scroll Pattern field bit mask
| #define BOARD_FPD_UB941_INVERTED_COLOR_PATTERN_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_INVERTED_COLOR_PATTERN_SHIFT_CNT) |
Inverted color Pattern field bit mask
| #define BOARD_FPD_UB941_PG_18B_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_PG_18B_SHIFT_CNT) |
Pattern generator 18-bit field bit mask
| #define BOARD_FPD_UB941_PG_EXTCLK_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_PG_EXTCLK_SHIFT_CNT) |
Pattern generator external clock field bit mask
| #define BOARD_FPD_UB941_PG_TSEL_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_PG_TSEL_SHIFT_CNT) |
Pattern generator timing select field bit mask
| #define BOARD_FPD_UB941_DSI_CONTINUOUS_CLK_ENABLE (1U) |
The DSI logic will assume the clock input is always in HS Mode and will bypass initialization requirements for the clock lane
| #define BOARD_FPD_UB941_DSI_CONTINUOUS_CLK_DISABLE (0U) |
In Independent 2:2 mode, this controls the selected FPD-Link III port DSI_CONTINUOUS_CLK is initially loaded from the MODE_SEL1 strap options
| #define BOARD_FPD_UB941_CLK_LANE_PN_MAINTIAN (0U) |
DSI Port 1 clock Lane P inputs mapped to P, N inputs mapped to N
| #define BOARD_FPD_UB941_CLK_LANE_PN_SWAP (1U) |
DSI Port 1 clock Lane P inputs mapped to N, N inputs mapped to P
| #define BOARD_FPD_UB941_DATA_LANE_PN_MAINTIAN (0U) |
DSI Port 1 Data Lane P inputs mapped to P, N inputs mapped to N
| #define BOARD_FPD_UB941_DATA_LANE_PN_SWAP (1U) |
DSI Port 1 Data Lane P inputs mapped to N, N inputs mapped to P
| #define BOARD_FPD_UB941_LINK_DETECT (0U) |
FPD Link error detected
| #define BOARD_FPD_UB941_DES_ERROR (1U) |
FPD Link detect error status
| #define BOARD_FPD_UB941_PCLK_DETECT (2U) |
FPD Link detect error status
| #define BOARD_FPD_UB941_BIST_CRC_ERROR (3U) |
FPD Link detect error status
| #define BOARD_FPD_UB941_LINK_LOST (4U) |
FPD Link detect error status
| #define BOARD_FPD_UB941_DPHY_ERROR (5U) |
FPD Link detect error status
| #define BOARD_FPD_UB941_DSI_ERROR (6U) |
FPD Link detect error status
| #define BOARD_FPD_UB941_LANES_1 (0U) |
FPD lane-1 select
| #define BOARD_FPD_UB941_LANES_2 (1U) |
FPD lane-2 select
| #define BOARD_FPD_UB941_LANES_3 (2U) |
FPD lane-3 select
| #define BOARD_FPD_UB941_LANES_4 (3U) |
FPD lane-4 select
| #define BOARD_FPD_UB941_PORT0_SEL (1U) |
FPD port-0 select
| #define BOARD_FPD_UB941_PORT1_SEL (2U) |
FPD port-1 select
| #define BOARD_FPD_UB941_PORT1_I2C_EN (4U) |
FPD port-1 I2C enable
| #define BOARD_FPD_UB941_DSI_PORT_INDIRECT_ACCESS (0U) |
DSI/D-PHY Port 0 indirect register access
| #define BOARD_FPD_UB941_PATTERN_GEN_INDIRECT_ACESS (1U) |
Pattern generator indirect register access
| #define BOARD_FPD_UB941_DSI_PORT0_REG (1U) |
DSI/D-PHY Port 0 Digital Registers
| #define BOARD_FPD_UB941_DSI_PORT1_REG (2U) |
DSI/D-PHY Port 1 Digital Registers
| #define BOARD_FPD_UB941_RESEVED (3U) |
Reserved
| #define BOARD_FPD_UB941_DSI_ANALOG_PLL_CNTRL_REG (4U) |
DSI Analog and PLL Control Registers
| #define BOARD_FPD_UB941_FPD_LINK_III_PORT0_REG (5U) |
FPD-Link III TX Port 0 Registers
| #define BOARD_FPD_UB941_FPD_LINK_III_PORT1_REG (6U) |
FPD-Link III TX Port 1 Registers
| #define BOARD_FPD_UB941_FPD_LINK_III_PORT0_PORT1_REG (7U) |
Simultaneous access to FPD-Link III TX Port 0/1 Registers
| #define BOARD_FPD_UB941_READ_ACCESS (0U) |
Select indirect read access mode
| #define BOARD_FPD_UB941_WRITE_ACCESS (1U) |
Select indirect write access mode
| #define BOARD_FPD_UB941_DSI_REF_CLK_MODE (0U) |
DSI Reference Clock Mode
| #define BOARD_FPD_UB941_EXT_REF_CLK_MODE (1U) |
External Reference Clock Mode.
| #define BOARD_FPD_UB941_INT_REF_CLK_MODE (2U) |
Internal Reference Clock Mode.
| #define BOARD_FPD_UB941_EXT_REF_CLK_MODE_2_2 (3U) |
External Reference Clock Mode for Independent 2:2 Mode.
| #define BOARD_FPD_UB941_FREQ_STBL_40 (0U) |
Confiures the FPD serializer freqency stability timing to 40 micro sec
| #define BOARD_FPD_UB941_FREQ_STBL_80 (1U) |
Confiures the FPD serializer freqency stability timing to 80 micro sec
| #define BOARD_FPD_UB941_FREQ_STBL_320 (2U) |
Confiures the FPD serializer freqency stability timing to 320 micro sec
| #define BOARD_FPD_UB941_FREQ_STBL_1280 (3U) |
Confiures the FPD serializer freqency stability timing to 1280 micro sec
| #define BOARD_FPD_UB941_READY_STS_UNSUCCESSFUL (0U) |
Ready status unsuccessful
| #define BOARD_FPD_UB941_READY_STS_SUCCESSFUL (1U) |
Ready status successful
| #define BOARD_FPD_UB941_TX_STS_UNSUCCESFUL (0U) |
Transmit status unsuccessful
| #define BOARD_FPD_UB941_TX_STS_SUCCESSFUL (1U) |
Transmit status successful
| #define BOARD_FPD_UB941_DSI_CLK_DET_STS_UNSUCCESFUL (0U) |
DSI clock detect status unsuccessful
| #define BOARD_FPD_UB941_DSI_CLK_DET_STS_SUCCESSFUL (1U) |
DSI clock detect status successful
| #define BOARD_FPD_UB941_NO_DSI_CLK_DETECTED (0U) |
No DSI clock detected
| #define BOARD_FPD_UB941_DSI_CLK_DETECTED (1U) |
DSI clock detected
| #define BOARD_FPD_UB941_DSI_FREQ_UNSTABLE (0U) |
No DSI clock detected
| #define BOARD_FPD_UB941_DSI_FREQ_STABLE (1U) |
No DSI clock detected
| #define BOARD_FPD_UB941_MODE_SEL_24 (0U) |
No DSI clock detected
| #define BOARD_FPD_UB941_MODE_SEL_18 (1U) |
No DSI clock detected
| #define BOARD_FPD_UB941_INT_CLK_SRC (0U) |
To select pattern generator internal clock source
| #define BOARD_FPD_UB941_EXT_CLK_SRC (1U) |
To select pattern generator external clock source
| #define BOARD_FPD_UB941_EXT_VIDEO_TIMING (0U) |
To select pattern generator external video timing source
| #define BOARD_FPD_UB941_OWN_VIDEO_TIMING (1U) |
To select pattern generator internal clock source
| #define BOARD_FPD_UB941_Indirect_Register_Read_ENABLE (1U) |
To enable the indirect register read
| #define BOARD_FPD_UB941_INDIRECT_REG_RD_DISABLE (0U) |
To disable the indirect register read
| #define BOARD_FPD_UB941_PATTERN_CHECKERBOARD (0U) |
Pattern - Checkerboard
| #define BOARD_FPD_UB941_PATTERN_WHITE_BLACK (1U) |
Pattern - White/Black
| #define BOARD_FPD_UB941_PATTERN_BLACK_WHITE (2U) |
Pattern - Black/White
| #define BOARD_FPD_UB941_PATTERN_RED_CYAN (3U) |
Pattern - Red/Cyan
| #define BOARD_FPD_UB941_PATTERN_GREEN_MAGNETA (4U) |
Pattern - Green/Magenta
| #define BOARD_FPD_UB941_PATTERN_BLUE_YELLOW (5U) |
Pattern - Blue/Yellow
| #define BOARD_FPD_UB941_PATTERN_HORIZONTALLY_SCALE_BLK2WHT_WHT2BLK (6U) |
Pattern - Horizontally Scaled Black to White/White to Black
| #define BOARD_FPD_UB941_PATTERN_HORIZONTALLY_SCALE_BLK2RED_WHT2CYN (7U) |
Pattern - Horizontally Scaled Black to Red/White to Cyan
| #define BOARD_FPD_UB941_PATTERN_HORIZONTALLY_SCALE_BLK2GRN_WHT2MAG (8U) |
Pattern - Horizontally Scaled Black to Green/White to Magenta
| #define BOARD_FPD_UB941_PATTERN_HORIZONTALLY_SCALE_BLK2BLU_WHT2YEL (9U) |
Pattern - Horizontally Scaled Black to Blue/White to Yellow
| #define BOARD_FPD_UB941_PATTERN_VERTICALLY_SCALE_BLK2WHT_WHT2BLK (10U) |
Pattern - Vertically Scaled Black to White/White to Black
| #define BOARD_FPD_UB941_PATTERN_VERTICALLY_SCALE_BLK2RED_WHT2CYN (11U) |
Pattern - Vertically Scaled Black to Red/White to Cyan
| #define BOARD_FPD_UB941_PATTERN_VERTICALLY_SCALE_BLK2GRN_WHT2MAG (12U) |
Pattern - Vertically Scaled Black to Green/White to Magenta
| #define BOARD_FPD_UB941_PATTERN_VERTICALLY_SCALE_BLK2BLU_WHT2YEL (13U) |
Pattern - Vertically Scaled Black to Blue/White to Yellow
| #define BOARD_FPD_UB941_PATTERN_CUSTOM_COLORS (14U) |
Pattern - Custom color (or its inversion) configured in PGRS, PGGS,PGBS registers
| #define BOARD_FPD_UB941_PATTERN_VCOM (15U) |
Pattern - VCOM
| #define BOARD_FPD_UB941_IND_ACC_CTL_READ_WRITE_BIT_MASK (1U) |
Indirect Access Register Read bit mask
| #define BOARD_FPD_UB941_FPD3_TX_MODE_BIT_MASK (7U) |
FPD-Link III TX Mode bit mask
| #define BOARD_FPD_UB941_AUTO_DETECT_FPD3_MODE (0U) |
Auto-Detect FPD-Link III mode (Single, Dual, or Replicate)
| #define BOARD_FPD_UB941_FORCED_SINGLE_FPD3_TRANSMITTER_MODE (1U) |
Forced Single FPD-Link III Transmitter mode (Port 1 disabled)
| #define BOARD_FPD_UB941_FORCED_DUAL_FPD3_TRANSMITTER_MODE (3U) |
Forced Dual FPD-Link III Transmitter mode
| #define BOARD_FPD_UB941_AUTO_DETECT_FPD3_SINGLE_MODE (4U) |
Auto-Detect FPD-Link III mode (Single or Replicate only, Dual disabled)
| #define BOARD_FPD_UB941_FORCED_INDEPENDENT_2_2_MODE (5U) |
Forced Independent 2:2 mode
| #define BOARD_FPD_UB941_FORCED_SPLITTER_MODE (7U) |
Forced Splitter Mode (half of video stream on each port)
| #define BOARD_FPD_UB941_DSI_CONTINUOUS_CLK_SHIFT_CNT (7U) |
DSI Continuous Clock Mode shift count
| #define BOARD_FPD_UB941_DSI_CONTINUOUS_CLK_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DSI_CONTINUOUS_CLK_SHIFT_CNT) |
DSI Continuous Clock Mode bit mask
| #define BOARD_FPD_UB941_DIGITAL_RESET_BIT_MASK (uint8_t)(0x01 << BOARD_FPD_UB941_DIGITAL_RESET_SHIFT_CNT) |
Digital reset 1 bit mask
| #define BOARD_FPD_UB941_DIGITAL_RESET_SHIFT_CNT (1U) |
Digital reset 1 shift count
| #define BOARD_FPD_UB941_I2C_ACCESS_PORT_MASK (7U) |
Select i2c access port mask
1.8.11 
