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PDK API Guide for J721E
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Data types used by PCM3168 Audio Codec library.
| #define BOARD_PCM3168_MODECTRL_REG_ADDR (0x40U) |
ADC/DAC mode control register address
| #define BOARD_PCM3168_DAC_PWR_MST_FMT_REG_ADDR (0x41U) |
DAC Control 1 register address
| #define BOARD_PCM3168_DAC_OP_FLT_REG_ADDR (0x42U) |
DAC Control 2 register address
| #define BOARD_PCM3168_DAC_INV_REG_ADDR (0x43U) |
DAC Output Phase control register address
| #define BOARD_PCM3168_DAC_MUTE_REG_ADDR (0x44U) |
DAC Soft Mute Control register address
| #define BOARD_PCM3168_DAC_ZERO_REG_ADDR (0x45U) |
DAC Zero Flag register address
| #define BOARD_PCM3168_DAC_ATT_DEMP_ZF_REG_ADDR (0x46U) |
DAC Control 3 register address
| #define BOARD_PCM3168_DAC_VOL_MASTER_REG_ADDR (0x47U) |
DAC master volume contol register address
| #define BOARD_PCM3168_DAC_VOL_CHAN_START_REG_ADDR (0x48U) |
DAC Channel0 volume control register address
| #define BOARD_PCM3168_ADC_SMODE_REG_ADDR (0x50U) |
ADC Sampling Mode control register address
| #define BOARD_PCM3168_ADC_MST_FMT_REG_ADDR (0x51U) |
ADC Control 1 register address
| #define BOARD_PCM3168_ADC_PWR_HPFB_REG_ADDR (0x52U) |
ADC Control 2 register address
| #define BOARD_PCM3168_ADC_SEAD_REG_ADDR (0x53U) |
ADC Input Configuration register address
| #define BOARD_PCM3168_ADC_INV_REG_ADDR (0x54U) |
ADC Input Phase control register address
| #define BOARD_PCM3168_ADC_MUTE_REG_ADDR (0x55U) |
ADC Soft Mute control register address
| #define BOARD_PCM3168_ADC_OV_REG_ADDR (0x56U) |
ADC Overflow Flag register address
| #define BOARD_PCM3168_ADC_ATT_OVF_REG_ADDR (0x57U) |
ADC Control 3 register address
| #define BOARD_PCM3168_ADC_VOL_MASTER_REG_ADDR (0x58U) |
ADC master volume contol register address
| #define BOARD_PCM3168_ADC_VOL_CHAN_START_REG_ADDR (0x59U) |
ADC Channel0 volume control register address
| #define BOARD_I2C_NUM_OF_BYTES_1 (0x1U) |
I2C number of bytes
| #define BOARD_PCM3168_MRST_SHIFT_CNT (0x07U) |
Reset control register bit fields
| #define BOARD_PCM3168_SRST_SHIFT_CNT (0x06U) |
| #define BOARD_PCM3168_SRDA_SHIFT_CNT (0x0U) |
| #define BOARD_PCM3168_MRST_BIT_MASK (0x01 << BOARD_PCM3168_MRST_SHIFT_CNT) |
| #define BOARD_PCM3168_SRST_BIT_MASK (0x01 << BOARD_PCM3168_SRST_SHIFT_CNT) |
| #define BOARD_PCM3168_SRDA_BIT_MASK (0x03 << BOARD_PCM3168_SRDA_SHIFT_CNT) |
| #define BOARD_PCM3168_PSMDA_SHIFT_CNT (0x07U) |
DAC Power save mode select register bit fileds
| #define BOARD_PCM3168_MSDA_SHIFT_CNT (0x04U) |
| #define BOARD_PCM3168_FMTDA_SHIFT_CNT (0x0U) |
| #define BOARD_PCM3168_PSMDA_BIT_MASK (0x01 << BOARD_PCM3168_PSMDA_SHIFT_CNT) |
| #define BOARD_PCM3168_MSDA_BIT_MASK (0x07 << BOARD_PCM3168_MSDA_SHIFT_CNT) |
| #define BOARD_PCM3168_FMTDA_BIT_MASK (0x0F << BOARD_PCM3168_FMTDA_SHIFT_CNT) |
| #define BOARD_PCM3168_OPED_SHIFT_CNT (0x04U) |
DAC operational control register bit fields
| #define BOARD_PCM3168_OPED_BIT_MASK (0x0F << BOARD_PCM3168_PSMDA_SHIFT_CNT) |
| #define BOARD_PCM3168_SRAD_SHIFT_CNT (0x0U) |
ADC Sampling Mode register bit fields
| #define BOARD_PCM3168_SRAD_BIT_MASK (0x03 << BOARD_PCM3168_SRAD_SHIFT_CNT) |
| #define BOARD_PCM3168_MSAD_SHIFT_CNT (0x04U) |
ADC Control 1 register bit fields
| #define BOARD_PCM3168_FMTAD_SHIFT_CNT (0x0U) |
| #define BOARD_PCM3168_MSAD_BIT_MASK (0x07 << BOARD_PCM3168_MSAD_SHIFT_CNT) |
| #define BOARD_PCM3168_FMTAD_BIT_MASK (0x07 << BOARD_PCM3168_FMTAD_SHIFT_CNT) |
| #define BOARD_PCM3168_PSVAD_SHIFT_CNT (0x04U) |
ADC Control 2 register bit fields
| #define BOARD_PCM3168_PSVAD_BIT_MASK (0x07 << BOARD_PCM3168_PSVAD_SHIFT_CNT) |
| #define BOARD_PCM3168_CHANNEL_0 (0x0U) |
Chaneel number
| #define BOARD_PCM3168_CHANNEL_1 (0x1U) |
| #define BOARD_PCM3168_CHANNEL_2 (0x2U) |
| #define BOARD_PCM3168_CHANNEL_3 (0x3U) |
| #define BOARD_PCM3168_CHANNEL_4 (0x4U) |
| #define BOARD_PCM3168_CHANNEL_5 (0x5U) |
| #define BOARD_PCM3168_CHANNEL_6 (0x6U) |
| #define BOARD_PCM3168_CHANNEL_7 (0x7U) |
| #define BOARD_PCM3168_CHANNEL_8 (0x8U) |
| #define BOARD_PCM3168_CFG_DAC (0U) |
Defines the codec config path.
Configure the DAC channel
| #define BOARD_PCM3168_CFG_ADC (1U) |
Configure the ADC channel
| #define BOARD_PCM3168_CFG_ALL (2U) |
Configure both ADC and DAC channels
| #define BOARD_PCM3168_MODE_PWROFF (0) |
Defines the codec mode control options.
Sets the codec to power down mode
| #define BOARD_PCM3168_MODE_NORMAL (1U) |
Sets the codec to normal operation mode
| #define BOARD_PCM3168_SAMPLE_AUTO (0) |
Defines the codec Sampling mode options.
Sampling mode is automatically set
| #define BOARD_PCM3168_SINGLE_RATE (1U) |
Sets the single rate for 512 fS and 768 fS
| #define BOARD_PCM3168_DUAL_RATE (2U) |
Sets the dual rate for 256 fS or 384 fS
| #define BOARD_PCM3168_QUAD_RATE (3U) |
Sets the quad rate for 128 fS and 192 fS
| #define BOARD_PCM3168_POWERSAVE_ENABLE (0) |
Defines the DAC power save mode options.
Enable Power save mode
| #define BOARD_PCM3168_POWERSAVE_DISABLE (1U) |
Disable Power save mode
| #define BOARD_PCM3168_NORMAL_MODE (0U) |
Defines the ADC power save mode options.
Normal mode
| #define BOARD_PCM3168_POWERSAVE_MODE (1U) |
Enable Power save mode
| #define BOARD_PCM3168_SLAVE_MODE (0) |
Defines the codec master slave configuration.
Configure the Codec in slave mode
| #define BOARD_PCM3168_MASTER_MODE_768FS (1U) |
Configure the Codec in Master mode with 768 fs
| #define BOARD_PCM3168_MASTER_MODE_512FS (2U) |
Configure the Codec in Master mode with 512 fs
| #define BOARD_PCM3168_MASTER MODE_384FS (3U) |
Configure the Codec in Master mode with 384 fs
| #define BOARD_PCM3168_MASTER_MODE_256FS (4U) |
Configure the Codec in Master mode with 256 fs
| #define BOARD_PCM3168_MASTER_MODE_192FS (5U) |
Configure the Codec in Master mode with 192 fs
| #define BOARD_PCM3168_MASTER_MODE_128FS (6U) |
Configure the Codec in Master mode with 128 fs
| #define BOARD_PCM3168_24B_I2S_FMT (0) |
Defines the codec data format.
Sets the codec data format to 24-bit I2S format
| #define BOARD_PCM3168_24B_LJ_FMT (1U) |
Sets the codec data format to 24-bit left-justified format
| #define BOARD_PCM3168_24B_RJ_FMT (2U) |
Sets the codec data format to 24-bit right-justified format
| #define BOARD_PCM3168_16B_RJ_FMT (3U) |
Sets the codec data format to 16-bit right-justified format
| #define BOARD_PCM3168_24B_I2S_DSP_FMT (4U) |
Sets the codec data format to 24-bit I2S mode DSP format
| #define BOARD_PCM3168_24B_LJ_DSP_FMT (5U) |
Sets the codec data format to 24-bit left-justified mode DSP format
| #define BOARD_PCM3168_24B_I2S_TDM_FMT (6U) |
Sets the codec data format to 24-bit I2S mode TDM format
| #define BOARD_PCM3168_24B_LJ_TDM_FMT (7U) |
Sets the codec data format to 24-bit left-justified mode TDM format
| #define BOARD_PCM3168_24B_HS_I2S_TDM_FMT (8U) |
Sets the codec data format to 24-bit high-speed I2S mode TDM format
| #define BOARD_PCM3168_24B_HS_LJ_TDM_FMT (9U) |
Sets the codec data format to 24-bit high-speed left-justified mode TDM format
| #define BOARD_PCM3168_DAC_NORMAL_OPERATION (0) |
Defines the DAC Operation mode.
Configures the DAC in normal operation mode
| #define BOARD_PCM3168_DAC_OPERATION_DISABLE (1U) |
Diables the DAC operation with or with out Power save
| #define BOARD_PCM3168_MUTE_DISABLE (0) |
Defines the Codec soft mute control.
Disables the codec soft mute function
| #define BOARD_PCM3168_MUTE_ENABLE (1U) |
Enables the codec soft mute function
1.8.11 
