PDK Documentation
tisci_rm_udmap.h File Reference

Go to the source code of this file.

Data Structures

struct  tisci_msg_rm_udmap_gcfg_cfg_req
 Configures a Navigator Subsystem UDMAP global configuration region. Configures the non-real-time registers of a Navigator Subsystem UDMAP global configuration region. The GCFG region being programmed must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment array. Individual fields for registers specified as valid are not checked for correctness. It is the application's responsibility to verify if the register fields are being set according to the device specification. More...
 
struct  tisci_msg_rm_udmap_gcfg_cfg_resp
 Response to configuring UDMAP global configuration. More...
 
struct  tisci_msg_rm_udmap_gcfg_get_cfg_req
 Get Navigator Subsystem UDMAP global configuration's non-real-time register configuration. Gets the configuration of the non-real-time register fields of a UDMAP global configuration. The host, or a supervisor of the host, who owns the gcfg region must be the requesting host. The values of the non-real-time registers are returned in tisci_msg_rm_udmap_gcfg_get_cfg_resp. The reset_cfg parameter is used to request either the existing non-real-time register values or the hardware reset values for the UDMAP global configuration register fields. More...
 
struct  tisci_msg_rm_udmap_gcfg_get_cfg_resp
 UDMAP global configuration get configuration response message. Response received by host processor after RM has handled tisci_msg_rm_udmap_gcfg_get_cfg_req. The response contains the global configuration's non-real-time register values. More...
 
struct  tisci_msg_rm_udmap_tx_ch_cfg_req
 Configures a Navigator Subsystem UDMAP transmit channel. More...
 
struct  tisci_msg_rm_udmap_tx_ch_cfg_resp
 Response to configuring a UDMAP transmit channel. More...
 
struct  tisci_msg_rm_udmap_tx_ch_get_cfg_req
 Get Navigator Subsystem UDMAP transmit channel's non-real-time register configuration. More...
 
struct  tisci_msg_rm_udmap_tx_ch_get_cfg_resp
 UDMAP transmit channel get configuration response message. More...
 
struct  tisci_msg_rm_udmap_rx_ch_cfg_req
 Configures a Navigator Subsystem UDMAP receive channel. More...
 
struct  tisci_msg_rm_udmap_rx_ch_cfg_resp
 Response to configuring a UDMAP receive channel. More...
 
struct  tisci_msg_rm_udmap_rx_ch_get_cfg_req
 Get Navigator Subsystem UDMAP receive channel's non-real-time register configuration. More...
 
struct  tisci_msg_rm_udmap_rx_ch_get_cfg_resp
 UDMAP receive channel get configuration response message. More...
 
struct  tisci_msg_rm_udmap_flow_cfg_req
 Configures a Navigator Subsystem UDMAP receive flow. More...
 
struct  tisci_msg_rm_udmap_flow_cfg_resp
 Response to configuring a Navigator Subsystem UDMAP receive flow. More...
 
struct  tisci_msg_rm_udmap_flow_get_cfg_req
 Get Navigator Subsystem UDMAP receive flow's non-real-time register configuration. More...
 
struct  tisci_msg_rm_udmap_flow_get_cfg_resp
 UDMAP receive flow get configuration response message. More...
 
struct  tisci_msg_rm_udmap_flow_size_thresh_cfg_req
 Configures a Navigator Subsystem UDMAP receive flow's size threshold fields. More...
 
struct  tisci_msg_rm_udmap_flow_size_thresh_cfg_resp
 Response to configuring a Navigator Subsystem UDMAP receive flow's size threshold fields. More...
 
struct  tisci_msg_rm_udmap_flow_size_thresh_get_cfg_req
 Get Navigator Subsystem UDMAP receive flow's non-real-time size threshold based queue routing register configuration. More...
 
struct  tisci_msg_rm_udmap_flow_size_thresh_get_cfg_resp
 UDMAP receive flow get size threshold configuration response message. More...
 

Macros

#define TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID   ((uint32_t) 1u << 0u)
 This file contains: More...
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID   ((uint32_t) 1u << 1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID   ((uint32_t) 1u << 2u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID   ((uint32_t) 1u << 3u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID   ((uint32_t) 1u << 4u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID   ((uint32_t) 1u << 5u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID   ((uint32_t) 1u << 6u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID   ((uint32_t) 1u << 7u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID   ((uint32_t) 1u << 8u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID   ((uint32_t) 1u << 14U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_ENABLED   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_INTERMEDIATE   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VIRTUAL   (2u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET   (2u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET_SINGLE_BUF   (3u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF   (10u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_VAL   (11u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF   (12u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_VAL   (13u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDLOW   (2u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_LOW   (3u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_MAX   (127u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_QNUM_SUPPRESS   (0xFFFFu)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_MAX   (7u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_QOS_MAX   (7u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_MAX   (15u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES   (1U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES   (2U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_256_BYTES   (3U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_REG   (0x0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_GET_CFG_RESET   (0x1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID   ((uint32_t) 1U << 9U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID   ((uint32_t) 1U << 10U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID   ((uint32_t) 1U << 11U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID   ((uint32_t) 1U << 12U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID   ((uint32_t) 1U << 13U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID   ((uint32_t) 1U << 15U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_DISABLED   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_ENABLED   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_DISABLED   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_ENABLED   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_ENABLED   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_CREDIT_CNT_MAX   (7u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_TDTYPE_IMMEDIATE   (0U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_TDTYPE_WAIT   (1U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID   ((uint32_t) 1u << 9u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID   ((uint32_t) 1u << 10u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID   ((uint32_t) 1u << 11u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID   ((uint32_t) 1u << 12u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_IGNORED   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_CH_FLOW_CNT_NONE   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID   ((uint32_t) 1u << 0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID   ((uint32_t) 1u << 1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID   ((uint32_t) 1u << 2u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID   ((uint32_t) 1u << 3u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID   ((uint32_t) 1u << 4u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID   ((uint32_t) 1u << 5u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID   ((uint32_t) 1u << 6u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID   ((uint32_t) 1u << 7u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID   ((uint32_t) 1u << 8u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID   ((uint32_t) 1u << 9u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID   ((uint32_t) 1u << 10u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID   ((uint32_t) 1u << 11u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID   ((uint32_t) 1u << 12u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID   ((uint32_t) 1u << 13u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID   ((uint32_t) 1u << 14u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID   ((uint32_t) 1u << 15u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID   ((uint32_t) 1u << 16u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID   ((uint32_t) 1u << 17u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID   ((uint32_t) 1u << 18u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH0_VALID   ((uint32_t) 1u << 0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH1_VALID   ((uint32_t) 1u << 1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH2_VALID   ((uint32_t) 1u << 2u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ1_QNUM_VALID   ((uint32_t) 1u << 3u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ2_QNUM_VALID   ((uint32_t) 1u << 4u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ3_QNUM_VALID   ((uint32_t) 1u << 5u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH_EN_VALID   ((uint32_t) 1u << 6u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_EINFO_NOT_PRESENT   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_EINFO_PRESENT   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PSINFO_NOT_PRESENT   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PSINFO_PRESENT   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_ERR_DROP   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_ERR_RETRY   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PS_END_PD   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PS_BEGIN_DB   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DESC_HOST   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DESC_MONO   (2u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_NONE   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_CFG_TAG   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_FLOW_ID   (2u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_SRC_TAG   (4u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_NONE   (0u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_CFG_TAG   (1u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_FLOW_ID   (2u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_DEST_TAG_LO   (4u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_DEST_TAG_HI   (5u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SOP_MAX   (255u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_MAX   (7u)
 
#define TISCI_MSG_VALUE_RM_UDMAP_GCFG_PERF_CTRL_VALID   ((uint32_t) 1U << 0U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_GCFG_EMU_CTRL_VALID   ((uint32_t) 1U << 1U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_GCFG_PSIL_TO_VALID   ((uint32_t) 1U << 2U)
 
#define TISCI_MSG_VALUE_RM_UDMAP_GCFG_RFLOWFWSTAT_VALID   ((uint32_t) 1U << 3U)
 

Functions

struct tisci_msg_rm_udmap_gcfg_cfg_req __attribute__ ((__packed__))
 

Variables

struct tisci_header hdr
 
uint32_t valid_params
 
uint16_t nav_id
 
uint32_t perf_ctrl
 
uint32_t emu_ctrl
 
uint32_t psil_to
 
uint32_t rflowfwstat
 
uint8_t get_reset_cfg
 
uint32_t revision
 
uint32_t utc_ctrl
 
uint32_t cap0
 
uint32_t cap1
 
uint32_t cap2
 
uint32_t cap3
 
uint16_t index
 
uint8_t tx_pause_on_err
 
uint8_t tx_filt_einfo
 
uint8_t tx_filt_pswords
 
uint8_t tx_atype
 
uint8_t tx_chan_type
 
uint8_t tx_supr_tdpkt
 
uint16_t tx_fetch_size
 
uint8_t tx_credit_count
 
uint16_t txcq_qnum
 
uint8_t tx_priority
 
uint8_t tx_qos
 
uint8_t tx_orderid
 
uint16_t fdepth
 
uint8_t tx_sched_priority
 
uint8_t tx_burst_size
 
uint8_t tx_tdtype
 
uint16_t rx_fetch_size
 
uint16_t rxcq_qnum
 
uint8_t rx_priority
 
uint8_t rx_qos
 
uint8_t rx_orderid
 
uint8_t rx_sched_priority
 
uint16_t flowid_start
 
uint16_t flowid_cnt
 
uint8_t rx_pause_on_err
 
uint8_t rx_atype
 
uint8_t rx_chan_type
 
uint8_t rx_ignore_short
 
uint8_t rx_ignore_long
 
uint8_t rx_burst_size
 
uint16_t flow_index
 
uint8_t rx_einfo_present
 
uint8_t rx_psinfo_present
 
uint8_t rx_error_handling
 
uint8_t rx_desc_type
 
uint16_t rx_sop_offset
 
uint16_t rx_dest_qnum
 
uint8_t rx_src_tag_hi
 
uint8_t rx_src_tag_lo
 
uint8_t rx_dest_tag_hi
 
uint8_t rx_dest_tag_lo
 
uint8_t rx_src_tag_hi_sel
 
uint8_t rx_src_tag_lo_sel
 
uint8_t rx_dest_tag_hi_sel
 
uint8_t rx_dest_tag_lo_sel
 
uint16_t rx_fdq0_sz0_qnum
 
uint16_t rx_fdq1_qnum
 
uint16_t rx_fdq2_qnum
 
uint16_t rx_fdq3_qnum
 
uint8_t rx_ps_location
 
uint16_t rx_size_thresh0
 
uint16_t rx_size_thresh1
 
uint16_t rx_size_thresh2
 
uint16_t rx_fdq0_sz1_qnum
 
uint16_t rx_fdq0_sz2_qnum
 
uint16_t rx_fdq0_sz3_qnum
 
uint8_t rx_size_thresh_en
 

Variable Documentation

◆ hdr

struct tisci_header hdr

◆ valid_params

uint32_t valid_params

◆ nav_id

uint16_t nav_id

◆ perf_ctrl

uint32_t perf_ctrl

◆ emu_ctrl

uint32_t emu_ctrl

◆ psil_to

uint32_t psil_to

◆ rflowfwstat

uint32_t rflowfwstat

◆ get_reset_cfg

uint8_t get_reset_cfg

◆ revision

uint32_t revision

◆ utc_ctrl

uint32_t utc_ctrl

◆ cap0

uint32_t cap0

◆ cap1

uint32_t cap1

◆ cap2

uint32_t cap2

◆ cap3

uint32_t cap3

◆ index

uint16_t index

◆ tx_pause_on_err

uint8_t tx_pause_on_err

◆ tx_filt_einfo

uint8_t tx_filt_einfo

◆ tx_filt_pswords

uint8_t tx_filt_pswords

◆ tx_atype

uint8_t tx_atype

◆ tx_chan_type

uint8_t tx_chan_type

◆ tx_supr_tdpkt

uint8_t tx_supr_tdpkt

◆ tx_fetch_size

uint16_t tx_fetch_size

◆ tx_credit_count

uint8_t tx_credit_count

◆ txcq_qnum

uint16_t txcq_qnum

◆ tx_priority

uint8_t tx_priority

◆ tx_qos

uint8_t tx_qos

◆ tx_orderid

uint8_t tx_orderid

◆ fdepth

uint16_t fdepth

◆ tx_sched_priority

uint8_t tx_sched_priority

◆ tx_burst_size

uint8_t tx_burst_size

◆ tx_tdtype

uint8_t tx_tdtype

◆ rx_fetch_size

uint16_t rx_fetch_size

◆ rxcq_qnum

uint16_t rxcq_qnum

◆ rx_priority

uint8_t rx_priority

◆ rx_qos

uint8_t rx_qos

◆ rx_orderid

uint8_t rx_orderid

◆ rx_sched_priority

uint8_t rx_sched_priority

◆ flowid_start

uint16_t flowid_start

◆ flowid_cnt

uint16_t flowid_cnt

◆ rx_pause_on_err

uint8_t rx_pause_on_err

◆ rx_atype

uint8_t rx_atype

◆ rx_chan_type

uint8_t rx_chan_type

◆ rx_ignore_short

uint8_t rx_ignore_short

◆ rx_ignore_long

uint8_t rx_ignore_long

◆ rx_burst_size

uint8_t rx_burst_size

◆ flow_index

uint16_t flow_index

◆ rx_einfo_present

uint8_t rx_einfo_present

◆ rx_psinfo_present

uint8_t rx_psinfo_present

◆ rx_error_handling

uint8_t rx_error_handling

◆ rx_desc_type

uint8_t rx_desc_type

◆ rx_sop_offset

uint16_t rx_sop_offset

◆ rx_dest_qnum

uint16_t rx_dest_qnum

◆ rx_src_tag_hi

uint8_t rx_src_tag_hi

◆ rx_src_tag_lo

uint8_t rx_src_tag_lo

◆ rx_dest_tag_hi

uint8_t rx_dest_tag_hi

◆ rx_dest_tag_lo

uint8_t rx_dest_tag_lo

◆ rx_src_tag_hi_sel

uint8_t rx_src_tag_hi_sel

◆ rx_src_tag_lo_sel

uint8_t rx_src_tag_lo_sel

◆ rx_dest_tag_hi_sel

uint8_t rx_dest_tag_hi_sel

◆ rx_dest_tag_lo_sel

uint8_t rx_dest_tag_lo_sel

◆ rx_fdq0_sz0_qnum

uint16_t rx_fdq0_sz0_qnum

◆ rx_fdq1_qnum

uint16_t rx_fdq1_qnum

◆ rx_fdq2_qnum

uint16_t rx_fdq2_qnum

◆ rx_fdq3_qnum

uint16_t rx_fdq3_qnum

◆ rx_ps_location

uint8_t rx_ps_location

◆ rx_size_thresh0

uint16_t rx_size_thresh0

◆ rx_size_thresh1

uint16_t rx_size_thresh1

◆ rx_size_thresh2

uint16_t rx_size_thresh2

◆ rx_fdq0_sz1_qnum

uint16_t rx_fdq0_sz1_qnum

◆ rx_fdq0_sz2_qnum

uint16_t rx_fdq0_sz2_qnum

◆ rx_fdq0_sz3_qnum

uint16_t rx_fdq0_sz3_qnum

◆ rx_size_thresh_en

uint8_t rx_size_thresh_en