This module is a Graph compiler to parse Deep Neural Network and generate required information to have inference on TI Hardware. Currently it is designed for ADAS/AD SOC of Jacinto7 family. These SOCs have TI’s next generation DSP (C7x) and a specialized hardware accelerator (MMA) for deep learning network inference. The network compiler considers the capability of these processor and available memory sub system and provide network execution information and memory layout for a given network. This compiler also predicts the execution time of the network and provides a expected performance summary report.

TIDL Graph Compiler References

Reference	Description
Release Summary	Release Summary
Execution Details	Execution Infomration
Configuration Parameters	Configuration Parameters
Supported Networks	Network Information
Known Issues	Known Issues
Disclaimer	Disclaimer