Configures a peripheral to processor interrupt.
Configures peripherals within the interrupt subsystem according to the valid configuration provided. The following tisci_msg_rm_irq_set_req::valid_params valid bit combinations are allowed:
Non-Event Sourced Direct Interrupt - Non-event peripheral interrupt direct to destination processor. One thing to note is an IA unmapped VINT route can be configured via this combination by passing the IA ID and VINT values as the src_id and src_index parameters. An IA unmapped VINT route is considered a non-event sourced direct interrupt route until a global event is mapped to the IA VINT: tisci_msg_rm_irq_set_req::dst_id valid bit == STRUE tisci_msg_rm_irq_set_req::dst_host_irq valid bit == STRUE tisci_msg_rm_irq_set_req::ia_id valid bit == SFALSE tisci_msg_rm_irq_set_req::vint valid bit == SFALSE tisci_msg_rm_irq_set_req::global_event valid bit == SFALSE tisci_msg_rm_irq_set_req::vint_status_bit_index valid bit == SFALSE
Event Sourced Direct Interrupt - Event-based peripheral interrupt direct to destination processor: tisci_msg_rm_irq_set_req::dst_id valid bit == STRUE tisci_msg_rm_irq_set_req::dst_host_irq valid bit == STRUE tisci_msg_rm_irq_set_req::ia_id valid bit == STRUE tisci_msg_rm_irq_set_req::vint valid bit == STRUE tisci_msg_rm_irq_set_req::global_event valid bit == STRUE tisci_msg_rm_irq_set_req::vint_status_bit_index valid bit == STRUE
Unmapped VINT Direct Interrupt - Event-based peripheral interrupt direct to processor with no global event to VINT status bit mapping configured on allocation of the VINT. Allows all event to VINT status bit mappings to take place at a later time: tisci_msg_rm_irq_set_req::dst_id valid bit == STRUE tisci_msg_rm_irq_set_req::dst_host_irq valid bit == STRUE tisci_msg_rm_irq_set_req::ia_id valid bit == STRUE tisci_msg_rm_irq_set_req::vint valid bit == STRUE tisci_msg_rm_irq_set_req::global_event valid bit == SFALSE tisci_msg_rm_irq_set_req::vint_status_bit_index valid bit == SFALSE
Event to VINT Mapping Only - Configure, or add a mapping to, an event-based peripheral interrupt polled from IA VINT real-time registers. Can also be used to add an event to VINT status bit mapping to an event-based direct interrupt route: tisci_msg_rm_irq_set_req::dst_id valid bit == SFALSE tisci_msg_rm_irq_set_req::dst_host_irq valid bit == SFALSE tisci_msg_rm_irq_set_req::ia_id valid bit == STRUE tisci_msg_rm_irq_set_req::vint valid bit == STRUE tisci_msg_rm_irq_set_req::global_event valid bit == STRUE tisci_msg_rm_irq_set_req::vint_status_bit_index valid bit == STRUE
OES Register Programming Only - Only programs the OES register of the source. Useful for setting UDMAP trigger events and any other events that are not translated to the interrupt domain: tisci_msg_rm_irq_set_req::dst_id valid bit == SFALSE tisci_msg_rm_irq_set_req::dst_host_irq valid bit == SFALSE tisci_msg_rm_irq_set_req::ia_id valid bit == SFALSE tisci_msg_rm_irq_set_req::vint valid bit == SFALSE tisci_msg_rm_irq_set_req::global_event valid bit == STRUE tisci_msg_rm_irq_set_req::vint_status_bit_index valid bit == SFALSE
The shortest route between the peripheral and the host processor that satisfies the requirements for non-event and event direct interrupts is programmed. The host processor interrupt controller is not programmed as part of the configuration.
Standard TISCI header
- Parameters
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This field is only valid if TISCI_MSG_VALUE_RM_DST_ID_VALID is set in tisci_msg_rm_irq_set_req::valid_params.
- Parameters
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| dst_host_irq | Destination host processor interrupt controller IRQ input |
This field is only valid if TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID is set in tisci_msg_rm_irq_set_req::valid_params.
- Parameters
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| ia_id | Device ID of interrupt aggregator in which the virtual interrupt resides. |
This field is only valid if TISCI_MSG_VALUE_RM_IA_ID_VALID is set in tisci_msg_rm_irq_set_req::valid_params.
- Parameters
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| vint | Virtual interrupt number if the interrupt route is through an interrupt aggregator. |
This field is only valid if TISCI_MSG_VALUE_RM_VINT_VALID is set in tisci_msg_rm_irq_set_req::valid_params.
- Parameters
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| global_event | Global event mapped to interrupt aggregator virtual interrupt status bit. The event is programmed into the OES register of the interrupt source. This field is only applicable for interrupt source's capable of generating global events. |
This field is only valid if TISCI_MSG_VALUE_RM_GLOBAL_EVENT_VALID is set in tisci_msg_rm_irq_set_req::valid_params.
- Parameters
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| vint_status_bit_index | Virtual interrupt status bit to set if the interrupt route utilizes an interrupt aggregator virtual interrupt. The host processor uses the status bit value within the interrupt aggregator's vint status register to find the source event which triggered the interrupt. |
This field is only valid if TISCI_MSG_VALUE_RM_VINT_STATUS_BIT_INDEX_VALID is set in tisci_msg_rm_irq_set_req::valid_params.
- Parameters
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| secondary_host | The interrupt route destination is the specified secondary host if the secondary_host's corresponding valid bit is set in tisci_msg_rm_irq_set_req::valid_params. Otherwise, the host within the TISCI message header is the route destination. |
1.8.13