9.6. J784S4 UDMA Resources¶
9.6.1. Introduction¶
This chapter provides information of list of udma resources associated with various modules in SOC.
9.6.2. UDMA Channels and PSIL Threads¶
PSIL is the backbone for UDMA transfers, for every UDMA transfer we need to pair PSIL threads involved.
For example: In order transfer data from memory to UART TX, we need to pair PSIL thread corresponding to UART TX with UDMA Tx PSIL Thread.
Users needs to make sure enough channels are allocated to core according to their usecase:
For example: If user wants to use Main MCSPI0 instance from Main R50, since there 4 MCSPI Tx channels available and for each channel there is corresponding PSIL associated, we need to allocate atleast 4 UDMA Tx channels.
Please refer J784S4 DMA Device Descriptions.
9.6.3. UDMA Rings¶
Each channel will have a ring associated to it submit descriptors to the channel, users needs to make sure they allocated both the channel and the associated ring to same core. Apart from associated rings there are GP(general purpose) rings, these rings can be used as compeletion and teardown compeletion rings. It is recommended to have a compeletion and teardown compeletion ring for each channel.
Please refer J784S4 Ring Accelerator Device Descriptions
9.6.4. UDMA Proxy¶
Proxy are helpful in submitting data to ring atomically when ring is not in TISCI_MSG_VALUE_RM_RING_MODE_RING, udma driver will allocate default proxy for each driver handle. It is recommended to allocate one proxy ring if the ring expected not to be used in TISCI_MSG_VALUE_RM_RING_MODE_RING.
Please refer J784S4 Proxy Device Descriptions
9.6.5. UDMA Event¶
There are 3 components involved in UDMA Interrupt Architecture: 1. Interrupt Aggregator Global Events 2. Interrupt Aggregator Virtual Interrupts 3. Interrupt Routers
9.6.5.1. Global Events¶
UDMA Interrupt Architecture involves 3 different components:
DMA resources like channels, rings, ring monitors have OES(Output Event Steering) registers. Each OES register can be programmed with a global event. This global event can be a channel trigger event, which will trigger channel transfer or associated to an IA(Interrupt Aggregator). Each global event associated with an Interrupt Aggregator has corresponding register, in which user can program VINT and VINT bit number. When a resource tries to generate event, it will set the bit in VINT number programmed in global event register. Each VINT is a 64 bit register, i.e. each VINT can combine 64 global events and generate single interrupt to input line of IR. Interrupt Router is MUX which can route input event to any one of the output lines.
UDMA LLD allows user to program 7 different event types:
Master Event This is special event which reserves one Virtual Interrupt, which helps to club 64 different events and generate single interrupt core.
DMA Compeletion Event This is per compeletion ring event. This event will be generated after every job compeletion.
DMA Teardown Packet Event This is per teardown packet ring event. This event will be generated when channel teardown happens while dma processing descriptor.
TR Event This is per channel event. This will be used to generate intermediate data transfer events.
Ring Event This event will generated for every empty to non-empty transition of the ring.
Flow Error Event This is per udma instance event. This will be used to register an event for trapping an out of range flow ID received on a packet
Ring Monitor Event This is per ring monitor event.
Note
It is recommended allocate 1 global-events per udma ring/channel to core through RM board config.
Number of IR Output lines allocated recommended to be closure VINTs allocated to core.