FFTLIB User Guide
c7100/FFTLIB_configurations.cpp
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13 **| Copyright (c) 2007-2012 Texas Instruments Incorporated |**
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28 
29 #include "../FFTLIB_types.h"
30 
31 /* -------------------------------------------------------------------------- */
32 /* MISRAC Rule 4.9(DEFINE.FUNC) Deviation: The advisory is not being */
33 /* addressed so as not to lose portability across different platforms. */
34 /* -------------------------------------------------------------------------- */
35 #ifdef WIN32
36 #define ASSIGN(param, value) value
37 #else
38 #define ASSIGN(param, value) .param = value
39 #endif
40 const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i32s_i32s_o32s =
41 {
42  /* -------------------------------------------------------------------- */
43  /* MISRAC Rule 10.3(ETYPE.ASSIGN.2012) Deviation: The data types of */
44  /* fields and the enum values are set by compiler according to the */
45  /* hardware specification, and are used as is. */
46  /* -------------------------------------------------------------------- */
47  ASSIGN(A_ATYPE , __MMA_A_CONFIG_ATYPE_INT32),
48  ASSIGN(A_RSVD1 , 0),
49  ASSIGN(A_ALUTEN , __MMA_A_CONFIG_NOLUT),
50  ASSIGN(A_RSVD2 , 0),
51  ASSIGN(A_ARF_CTRL , __MMA_A_CONFIG_ARF_DISABLE),
52  ASSIGN(A_ARF_BASE , 0),
53  ASSIGN(A_RSVD3 , 0),
54  ASSIGN(A_ARF_SIZE , 0),
55  ASSIGN(A_RSVD4 , 0),
56 
57  ASSIGN(B_BSWPER , FFTLIB_MMA_SIZE_32_BIT), // 32 bits
58  ASSIGN(B_BRSTPER , FFTLIB_MMA_SIZE_32_BIT), // 8 bits
59  ASSIGN(B_BTYPE , __MMA_B_CONFIG_SIZE32), // 2 bits
60  ASSIGN(B_LDBOPT , __MMA_LDBOPT_MMA1),
61  ASSIGN(B_B4EXP , __MMA_B_CONFIG_B4EXP_MMA1),
62  ASSIGN(B_RSVD1 , 0),
63  ASSIGN(B_ORDER , __MMA_B_CONFIG_ROW), // 1 bit
64  ASSIGN(B_RSVD2 , 0),
65  ASSIGN(B_BSTART , 0), // 1 bits
66  ASSIGN(B_BCNT1_ENABLE , 0),
67  ASSIGN(B_RSVD3 , 0),
68  ASSIGN(B_BOFFSET , 0), // 8 bits
69  ASSIGN(B_RSVD4 , 0),
70 
71  ASSIGN(C_ATYPE , __MMA_C_CONFIG_ATYPE_SA),
72  ASSIGN(C_ARF_BASE , 0),
73  ASSIGN(C_ARF_C7 , 0),
74  ASSIGN(C_BTYPE , __MMA_C_CONFIG_BTYPE_INT32),
75  ASSIGN(C_RSVD2 , 0),
76  ASSIGN(C_OPERATION0 , __MMA_C_CONFIG_MUL),
77  ASSIGN(C_LOP0, __MMA_C_CONFIG_LOP_C),
78  ASSIGN(C_RSVD3 , 0),
79  ASSIGN(C_OPERATION1 , __MMA_C_CONFIG_MULPLUS),
80  ASSIGN(C_LOP1, __MMA_C_CONFIG_LOP_C),
81  ASSIGN(C_BIASORDER , __MMA_C_CONFIG_BIAS_ORDER_COLUMN),
82  ASSIGN(C_RSVD4 , 0),
83  ASSIGN(C_HWLDDST , __MMA_C_CONFIG_HWLDDST_X4_0),
84  ASSIGN(C_RSVD5 , 0),
85  ASSIGN(C_HWLDTYPE , __MMA_C_CONFIG_HWLDTYPE_INT32),
86  ASSIGN(C_RSVD6 , 0),
87 
88  ASSIGN(C_OPSTART , __MMA_C_CONFIG_OPSTART_OPERATION0), // No enum in MMA spec? Initial C operand selections
89  ASSIGN(C_BSTART , 0x0), // Initial B bank selection for reading B matrix data
90  ASSIGN(C_CRSTART , 0x0), // Initial C bank selection for reading operands
91  ASSIGN(C_CWSTART , 0x0), // Initial C bank selection for writing computation results
92  ASSIGN(C_CLSTART , 0x0), // Initial C bank selection for writing operands from HWALD*
93  ASSIGN(C_RSVD7 , 0),
94  ASSIGN(C_CROFFSET , 0x0), // 6-bits C row read offset
95  ASSIGN(C_RSVD8 , 0),
96  ASSIGN(C_CWOFFSET , 0x0), // C row write offset for computations
97  ASSIGN(C_RSVD9 , 0),
98  ASSIGN(C_CLOFFSET , 0x0), // C row write offset for HWALD* instructions
99  ASSIGN(C_RSVD10 , 0),
100  ASSIGN(C_CLSWPER , 0), // C bank switch period for HWALD* instruction writes
101  ASSIGN(C_CLRSTPER , 0), // C write row offset reset period for HWALD*
102  ASSIGN(C_OP1PER , 0), // Operation 1 period
103  ASSIGN(C_OP0PER , FFTLIB_MMA_SIZE_32_BIT), // Operation 0 period
104  ASSIGN(C_BSWPER , FFTLIB_MMA_SIZE_32_BIT), // B bank switch period
105  ASSIGN(C_CRSWPER , 0), // C bank switch period for read instructions
106  ASSIGN(C_CWSWPER , 0), // C bank switch period for computation writes
107  ASSIGN(C_CRRSTPER , FFTLIB_MMA_SIZE_32_BIT), // C read row offset reset period
108  ASSIGN(C_CWRSTPER , FFTLIB_MMA_SIZE_32_BIT), // C write row offset reset period for computations
109 
110  ASSIGN(X_ReLU , 0x0), // Enable Rectified Linear Units non-linearity after optional saturation
111  ASSIGN(X_PSAT , 0),
112  ASSIGN(X_SAT_MIN_5_0 , 0),
113  ASSIGN(X_SAT , 0x1), // Enable saturation in the transfer buffer element type after optional rounding
114  ASSIGN(X_SAT_MIN_12_6 , 0),
115  ASSIGN(X_RE , 0x1), // Enable routing via 1/2 LSB addition after shifting
116  ASSIGN(X_SAT_MIN_15_13, 0),
117  ASSIGN(X_RANGE, __MMA_X_CONFIG_RANGE_DISABLE_NOINIT),
118  ASSIGN(X_SCALE_SHIFT_CTRL, __MMA_X_CONFIG_SCALE_SHIFT_CTRL_DISABLE),
119  ASSIGN(X_RSVD3 , 0),
120  ASSIGN(X_SHIFT , 0), // 7 bits Right shift amount), signed or unsigned depending on CTYPE fieldASSIGN(
121  ASSIGN(X_VPACKN , __MMA_X_CONFIG_VPACKN_DISABLE),
122  ASSIGN(X_XTYPE , __MMA_X_CONFIG_XTYPE_INT32), // Transfer buffer element typeASSIGN( Not all combinations of CTYPE and XTYPE are supported
123  ASSIGN(X_SAT_MAX_3_0 , 0),
124  ASSIGN(X_CTYPE , __MMA_X_CONFIG_CTYPE_INT128), // C matrix element typeASSIGN( This must be consistent with the B FSM setting
125  ASSIGN(X_SAT_MAX_8_4 , 0),
126  ASSIGN(X_CSWPER , FFTLIB_MMA_SIZE_32_BIT), // C read bank switch period
127  ASSIGN(X_CRRSTPER , FFTLIB_MMA_SIZE_32_BIT), // C read row offset reset period
128  ASSIGN(X_COFFSET , 0x0), // C matrix row read address offset
129  ASSIGN(X_CSTART , 0x0), // Initial C bank selection
130  ASSIGN(X_SAT_MAX_15_9 , 0x0),
131 
132  ASSIGN(RSVD , 0),
133  ASSIGN(PARITYCTRL , __MMA_NORMAL)
134 };
135 
136 /*********************************
137  * Typical 16-bit configurations *
138  *********************************/
139 
140 const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i16s_i16s_o16s =
141 {
142  ASSIGN(A_ATYPE , __MMA_A_CONFIG_ATYPE_INT16),
143  ASSIGN(A_RSVD1 , 0),
144  ASSIGN(A_ALUTEN , __MMA_A_CONFIG_NOLUT),
145  ASSIGN(A_RSVD2 , 0),
146  ASSIGN(A_ARF_CTRL , __MMA_A_CONFIG_ARF_DISABLE),
147  ASSIGN(A_ARF_BASE , 0),
148  ASSIGN(A_RSVD3 , 0),
149  ASSIGN(A_ARF_SIZE , 0),
150  ASSIGN(A_RSVD4 , 0),
151 
152  ASSIGN(B_BSWPER , FFTLIB_MMA_SIZE_16_BIT), // 32 bits
153  ASSIGN(B_BRSTPER , FFTLIB_MMA_SIZE_16_BIT), // 8 bits
154  ASSIGN(B_BTYPE , __MMA_B_CONFIG_SIZE16), // 2 bits
155  ASSIGN(B_LDBOPT , __MMA_LDBOPT_MMA1),
156  ASSIGN(B_B4EXP , __MMA_B_CONFIG_B4EXP_MMA1),
157  ASSIGN(B_RSVD1 , 0),
158  ASSIGN(B_ORDER , __MMA_B_CONFIG_ROW), // 1 bit
159  ASSIGN(B_RSVD2 , 0),
160  ASSIGN(B_BSTART , 0), // 1 bits
161  ASSIGN(B_BCNT1_ENABLE , 0),
162  ASSIGN(B_RSVD3 , 0),
163  ASSIGN(B_BOFFSET , 0), // 8 bits
164  ASSIGN(B_RSVD4 , 0),
165 
166  ASSIGN(C_ATYPE , __MMA_C_CONFIG_ATYPE_SA),
167  ASSIGN(C_ARF_BASE , 0),
168  ASSIGN(C_ARF_C7 , 0),
169  ASSIGN(C_BTYPE , __MMA_C_CONFIG_BTYPE_INT16),
170  ASSIGN(C_RSVD2 , 0),
171  ASSIGN(C_OPERATION0 , __MMA_C_CONFIG_MUL),
172  ASSIGN(C_LOP0, __MMA_C_CONFIG_LOP_C),
173  ASSIGN(C_RSVD3 , 0),
174  ASSIGN(C_OPERATION1 , __MMA_C_CONFIG_MULPLUS),
175  ASSIGN(C_LOP1, __MMA_C_CONFIG_LOP_C),
176  ASSIGN(C_BIASORDER , __MMA_C_CONFIG_BIAS_ORDER_COLUMN),
177  ASSIGN(C_RSVD4 , 0),
178  ASSIGN(C_HWLDDST , __MMA_C_CONFIG_HWLDDST_X4_0),
179  ASSIGN(C_RSVD5 , 0),
180  ASSIGN(C_HWLDTYPE , __MMA_C_CONFIG_HWLDTYPE_INT16),
181  ASSIGN(C_RSVD6 , 0),
182 
183  ASSIGN(C_OPSTART , __MMA_C_CONFIG_OPSTART_OPERATION0), // No enum in MMA spec? Initial C operand selections
184  ASSIGN(C_BSTART , 0x0), // Initial B bank selection for reading B matrix data
185  ASSIGN(C_CRSTART , 0x0), // Initial C bank selection for reading operands
186  ASSIGN(C_CWSTART , 0x0), // Initial C bank selection for writing computation results
187  ASSIGN(C_CLSTART , 0x0), // Initial C bank selection for writing operands from HWALD*
188  ASSIGN(C_RSVD7 , 0),
189  ASSIGN(C_CROFFSET , 0x0), // 6-bits C row read offset
190  ASSIGN(C_RSVD8 , 0),
191  ASSIGN(C_CWOFFSET , 0x0), // C row write offset for computations
192  ASSIGN(C_RSVD9 , 0),
193  ASSIGN(C_CLOFFSET , 0x0), // C row write offset for HWALD* instructions
194  ASSIGN(C_RSVD10 , 0),
195  ASSIGN(C_CLSWPER , 0), // C bank switch period for HWALD* instruction writes
196  ASSIGN(C_CLRSTPER , 0), // C write row offset reset period for HWALD*
197  ASSIGN(C_OP1PER , 0), // Operation 1 period
198  ASSIGN(C_OP0PER , FFTLIB_MMA_SIZE_16_BIT), // Operation 0 period
199  ASSIGN(C_BSWPER , FFTLIB_MMA_SIZE_16_BIT), // B bank switch period
200  ASSIGN(C_CRSWPER , 0), // C bank switch period for read instructions
201  ASSIGN(C_CWSWPER , 0), // C bank switch period for computation writes
202  ASSIGN(C_CRRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C read row offset reset period
203  ASSIGN(C_CWRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C write row offset reset period for computations
204 
205  ASSIGN(X_ReLU , 0x0), // Enable Rectified Linear Units non-linearity after optional saturation
206  ASSIGN(X_PSAT , 0),
207  ASSIGN(X_SAT_MIN_5_0 , 0),
208  ASSIGN(X_SAT , 0x1), // Enable saturation in the transfer buffer element type after optional rounding
209  ASSIGN(X_SAT_MIN_12_6 , 0),
210  ASSIGN(X_RE , 0x1), // Enable routing via 1/2 LSB addition after shifting
211  ASSIGN(X_SAT_MIN_15_13, 0),
212  ASSIGN(X_RANGE, __MMA_X_CONFIG_RANGE_DISABLE_NOINIT),
213  ASSIGN(X_SCALE_SHIFT_CTRL, __MMA_X_CONFIG_SCALE_SHIFT_CTRL_DISABLE),
214  ASSIGN(X_RSVD3 , 0),
215  ASSIGN(X_SHIFT , 0), // 7 bits Right shift amount), signed or unsigned depending on CTYPE fieldASSIGN(
216  ASSIGN(X_VPACKN , __MMA_X_CONFIG_VPACKN_DISABLE),
217  ASSIGN(X_XTYPE , __MMA_X_CONFIG_XTYPE_INT16), // Transfer buffer element typeASSIGN( Not all combinations of CTYPE and XTYPE are supported
218  ASSIGN(X_SAT_MAX_3_0 , 0),
219  ASSIGN(X_CTYPE , __MMA_X_CONFIG_CTYPE_INT64), // C matrix element typeASSIGN( This must be consistent with the B FSM setting
220  ASSIGN(X_SAT_MAX_8_4 , 0),
221  ASSIGN(X_CSWPER , FFTLIB_MMA_SIZE_16_BIT), // C read bank switch period
222  ASSIGN(X_CRRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C read row offset reset period
223  ASSIGN(X_COFFSET , 0x0), // C matrix row read address offset
224  ASSIGN(X_CSTART , 0x0), // Initial C bank selection
225  ASSIGN(X_SAT_MAX_15_9 , 0x0),
226 
227  ASSIGN(RSVD , 0),
228  ASSIGN(PARITYCTRL , __MMA_NORMAL)
229 };
230 
231 
232 const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i16s_i16s_o16u =
233 {
234  ASSIGN(A_ATYPE , __MMA_A_CONFIG_ATYPE_INT16),
235  ASSIGN(A_RSVD1 , 0),
236  ASSIGN(A_ALUTEN , __MMA_A_CONFIG_NOLUT),
237  ASSIGN(A_RSVD2 , 0),
238  ASSIGN(A_ARF_CTRL , __MMA_A_CONFIG_ARF_DISABLE),
239  ASSIGN(A_ARF_BASE , 0),
240  ASSIGN(A_RSVD3 , 0),
241  ASSIGN(A_ARF_SIZE , 0),
242  ASSIGN(A_RSVD4 , 0),
243 
244  ASSIGN(B_BSWPER , FFTLIB_MMA_SIZE_16_BIT), // 32 bits
245  ASSIGN(B_BRSTPER , FFTLIB_MMA_SIZE_16_BIT), // 8 bits
246  ASSIGN(B_BTYPE , __MMA_B_CONFIG_SIZE16), // 2 bits
247  ASSIGN(B_LDBOPT , __MMA_LDBOPT_MMA1),
248  ASSIGN(B_B4EXP , __MMA_B_CONFIG_B4EXP_MMA1),
249  ASSIGN(B_RSVD1 , 0),
250  ASSIGN(B_ORDER , __MMA_B_CONFIG_ROW), // 1 bit
251  ASSIGN(B_RSVD2 , 0),
252  ASSIGN(B_BSTART , 0), // 1 bits
253  ASSIGN(B_BCNT1_ENABLE , 0),
254  ASSIGN(B_RSVD3 , 0),
255  ASSIGN(B_BOFFSET , 0), // 8 bits
256  ASSIGN(B_RSVD4 , 0),
257 
258  ASSIGN(C_ATYPE , __MMA_C_CONFIG_ATYPE_SA),
259  ASSIGN(C_ARF_BASE , 0),
260  ASSIGN(C_ARF_C7 , 0),
261  ASSIGN(C_BTYPE , __MMA_C_CONFIG_BTYPE_INT16),
262  ASSIGN(C_RSVD2 , 0),
263  ASSIGN(C_OPERATION0 , __MMA_C_CONFIG_MUL),
264  ASSIGN(C_LOP0, __MMA_C_CONFIG_LOP_C),
265  ASSIGN(C_RSVD3 , 0),
266  ASSIGN(C_OPERATION1 , __MMA_C_CONFIG_MULPLUS),
267  ASSIGN(C_LOP1, __MMA_C_CONFIG_LOP_C),
268  ASSIGN(C_BIASORDER , __MMA_C_CONFIG_BIAS_ORDER_COLUMN),
269  ASSIGN(C_RSVD4 , 0),
270  ASSIGN(C_HWLDDST , __MMA_C_CONFIG_HWLDDST_X4_0),
271  ASSIGN(C_RSVD5 , 0),
272  ASSIGN(C_HWLDTYPE , __MMA_C_CONFIG_HWLDTYPE_INT16),
273  ASSIGN(C_RSVD6 , 0),
274 
275  ASSIGN(C_OPSTART , __MMA_C_CONFIG_OPSTART_OPERATION0), // No enum in MMA spec? Initial C operand selections
276  ASSIGN(C_BSTART , 0x0), // Initial B bank selection for reading B matrix data
277  ASSIGN(C_CRSTART , 0x0), // Initial C bank selection for reading operands
278  ASSIGN(C_CWSTART , 0x0), // Initial C bank selection for writing computation results
279  ASSIGN(C_CLSTART , 0x0), // Initial C bank selection for writing operands from HWALD*
280  ASSIGN(C_RSVD7 , 0),
281  ASSIGN(C_CROFFSET , 0x0), // 6-bits C row read offset
282  ASSIGN(C_RSVD8 , 0),
283  ASSIGN(C_CWOFFSET , 0x0), // C row write offset for computations
284  ASSIGN(C_RSVD9 , 0),
285  ASSIGN(C_CLOFFSET , 0x0), // C row write offset for HWALD* instructions
286  ASSIGN(C_RSVD10 , 0),
287  ASSIGN(C_CLSWPER , 0), // C bank switch period for HWALD* instruction writes
288  ASSIGN(C_CLRSTPER , 0), // C write row offset reset period for HWALD*
289  ASSIGN(C_OP1PER , 0), // Operation 1 period
290  ASSIGN(C_OP0PER , FFTLIB_MMA_SIZE_16_BIT), // Operation 0 period
291  ASSIGN(C_BSWPER , FFTLIB_MMA_SIZE_16_BIT), // B bank switch period
292  ASSIGN(C_CRSWPER , 0), // C bank switch period for read instructions
293  ASSIGN(C_CWSWPER , 0), // C bank switch period for computation writes
294  ASSIGN(C_CRRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C read row offset reset period
295  ASSIGN(C_CWRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C write row offset reset period for computations
296 
297  ASSIGN(X_ReLU , 0x1), // Enable Rectified Linear Units non-linearity after optional saturation
298  ASSIGN(X_PSAT , 0),
299  ASSIGN(X_SAT_MIN_5_0 , 0),
300  ASSIGN(X_SAT , 0x0), // Enable saturation in the transfer buffer element type after optional rounding
301  ASSIGN(X_SAT_MIN_12_6 , 0),
302  ASSIGN(X_RE , 0x1), // Enable routing via 1/2 LSB addition after shifting
303  ASSIGN(X_SAT_MIN_15_13, 0),
304  ASSIGN(X_RANGE, __MMA_X_CONFIG_RANGE_DISABLE_NOINIT),
305  ASSIGN(X_SCALE_SHIFT_CTRL, __MMA_X_CONFIG_SCALE_SHIFT_CTRL_DISABLE),
306  ASSIGN(X_RSVD3, 0),
307 
308  ASSIGN(X_SHIFT , 0), // 7 bits Right shift amount), signed or unsigned depending on CTYPE fieldASSIGN(
309  ASSIGN(X_VPACKN , __MMA_X_CONFIG_VPACKN_DISABLE),
310  ASSIGN(X_XTYPE , __MMA_X_CONFIG_XTYPE_UINT16), // Transfer buffer element typeASSIGN( Not all combinations of CTYPE and XTYPE are supported
311  ASSIGN(X_SAT_MAX_3_0 , 0),
312  ASSIGN(X_CTYPE , __MMA_X_CONFIG_CTYPE_INT64), // C matrix element typeASSIGN( This must be consistent with the B FSM setting
313  ASSIGN(X_SAT_MAX_8_4 , 0),
314  ASSIGN(X_CSWPER , FFTLIB_MMA_SIZE_16_BIT), // C read bank switch period
315  ASSIGN(X_CRRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C read row offset reset period
316  ASSIGN(X_COFFSET , 0x0), // C matrix row read address offset
317  ASSIGN(X_CSTART , 0x0), // Initial C bank selection
318  ASSIGN(X_SAT_MAX_15_9 , 0x0),
319 
320  ASSIGN(RSVD , 0),
321  ASSIGN(PARITYCTRL , __MMA_NORMAL)
322 };
323 
324 const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i16u_i16s_o16s =
325 {
326  ASSIGN(A_ATYPE , __MMA_A_CONFIG_ATYPE_UINT16),
327  ASSIGN(A_RSVD1 , 0),
328  ASSIGN(A_ALUTEN , __MMA_A_CONFIG_NOLUT),
329  ASSIGN(A_RSVD2 , 0),
330  ASSIGN(A_ARF_CTRL , __MMA_A_CONFIG_ARF_DISABLE),
331  ASSIGN(A_ARF_BASE , 0),
332  ASSIGN(A_RSVD3 , 0),
333  ASSIGN(A_ARF_SIZE , 0),
334  ASSIGN(A_RSVD4 , 0),
335 
336  ASSIGN(B_BSWPER , FFTLIB_MMA_SIZE_16_BIT), // 32 bits
337  ASSIGN(B_BRSTPER , FFTLIB_MMA_SIZE_16_BIT), // 8 bits
338  ASSIGN(B_BTYPE , __MMA_B_CONFIG_SIZE16), // 2 bits
339  ASSIGN(B_LDBOPT , __MMA_LDBOPT_MMA1),
340  ASSIGN(B_B4EXP , __MMA_B_CONFIG_B4EXP_MMA1),
341  ASSIGN(B_RSVD1 , 0),
342  ASSIGN(B_ORDER , __MMA_B_CONFIG_ROW), // 1 bit
343  ASSIGN(B_RSVD2 , 0),
344  ASSIGN(B_BSTART , 0), // 1 bits
345  ASSIGN(B_BCNT1_ENABLE , 0),
346  ASSIGN(B_RSVD3 , 0),
347  ASSIGN(B_BOFFSET , 0), // 8 bits
348  ASSIGN(B_RSVD4 , 0),
349 
350  ASSIGN(C_ATYPE , __MMA_C_CONFIG_ATYPE_UA),
351  ASSIGN(C_ARF_BASE , 0),
352  ASSIGN(C_ARF_C7 , 0),
353  ASSIGN(C_BTYPE , __MMA_C_CONFIG_BTYPE_INT16),
354  ASSIGN(C_RSVD2 , 0),
355  ASSIGN(C_OPERATION0 , __MMA_C_CONFIG_MUL),
356  ASSIGN(C_LOP0, __MMA_C_CONFIG_LOP_C),
357  ASSIGN(C_RSVD3 , 0),
358  ASSIGN(C_OPERATION1 , __MMA_C_CONFIG_MULPLUS),
359  ASSIGN(C_LOP1, __MMA_C_CONFIG_LOP_C),
360  ASSIGN(C_BIASORDER , __MMA_C_CONFIG_BIAS_ORDER_COLUMN),
361  ASSIGN(C_RSVD4 , 0),
362  ASSIGN(C_HWLDDST , __MMA_C_CONFIG_HWLDDST_X4_0),
363  ASSIGN(C_RSVD5 , 0),
364  ASSIGN(C_HWLDTYPE , __MMA_C_CONFIG_HWLDTYPE_INT16),
365  ASSIGN(C_RSVD6 , 0),
366 
367  ASSIGN(C_OPSTART , __MMA_C_CONFIG_OPSTART_OPERATION0), // No enum in MMA spec? Initial C operand selections
368  ASSIGN(C_BSTART , 0x0), // Initial B bank selection for reading B matrix data
369  ASSIGN(C_CRSTART , 0x0), // Initial C bank selection for reading operands
370  ASSIGN(C_CWSTART , 0x0), // Initial C bank selection for writing computation results
371  ASSIGN(C_CLSTART , 0x0), // Initial C bank selection for writing operands from HWALD*
372  ASSIGN(C_RSVD7 , 0),
373  ASSIGN(C_CROFFSET , 0x0), // 6-bits C row read offset
374  ASSIGN(C_RSVD8 , 0),
375  ASSIGN(C_CWOFFSET , 0x0), // C row write offset for computations
376  ASSIGN(C_RSVD9 , 0),
377  ASSIGN(C_CLOFFSET , 0x0), // C row write offset for HWALD* instructions
378  ASSIGN(C_RSVD10 , 0),
379  ASSIGN(C_CLSWPER , 0), // C bank switch period for HWALD* instruction writes
380  ASSIGN(C_CLRSTPER , 0), // C write row offset reset period for HWALD*
381  ASSIGN(C_OP1PER , 0), // Operation 1 period
382  ASSIGN(C_OP0PER , FFTLIB_MMA_SIZE_16_BIT), // Operation 0 period
383  ASSIGN(C_BSWPER , FFTLIB_MMA_SIZE_16_BIT), // B bank switch period
384  ASSIGN(C_CRSWPER , 0), // C bank switch period for read instructions
385  ASSIGN(C_CWSWPER , 0), // C bank switch period for computation writes
386  ASSIGN(C_CRRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C read row offset reset period
387  ASSIGN(C_CWRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C write row offset reset period for computations
388 
389  ASSIGN(X_ReLU , 0x0), // Enable Rectified Linear Units non-linearity after optional saturation
390  ASSIGN(X_PSAT , 0),
391  ASSIGN(X_SAT_MIN_5_0 , 0),
392  ASSIGN(X_SAT , 0x1), // Enable saturation in the transfer buffer element type after optional rounding
393  ASSIGN(X_SAT_MIN_12_6 , 0),
394  ASSIGN(X_RE , 0x1), // Enable routing via 1/2 LSB addition after shifting
395  ASSIGN(X_SAT_MIN_15_13, 0),
396  ASSIGN(X_RANGE, __MMA_X_CONFIG_RANGE_DISABLE_NOINIT),
397  ASSIGN(X_SCALE_SHIFT_CTRL, __MMA_X_CONFIG_SCALE_SHIFT_CTRL_DISABLE),
398  ASSIGN(X_RSVD3 , 0),
399  ASSIGN(X_SHIFT , 0), // 7 bits Right shift amount), signed or unsigned depending on CTYPE fieldASSIGN(
400  ASSIGN(X_VPACKN , __MMA_X_CONFIG_VPACKN_DISABLE),
401  ASSIGN(X_XTYPE , __MMA_X_CONFIG_XTYPE_INT16), // Transfer buffer element typeASSIGN( Not all combinations of CTYPE and XTYPE are supported
402  ASSIGN(X_SAT_MAX_3_0 , 0),
403  ASSIGN(X_CTYPE , __MMA_X_CONFIG_CTYPE_INT64), // C matrix element typeASSIGN( This must be consistent with the B FSM setting
404  ASSIGN(X_SAT_MAX_8_4 , 0),
405  ASSIGN(X_CSWPER , FFTLIB_MMA_SIZE_16_BIT), // C read bank switch period
406  ASSIGN(X_CRRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C read row offset reset period
407  ASSIGN(X_COFFSET , 0x0), // C matrix row read address offset
408  ASSIGN(X_CSTART , 0x0), // Initial C bank selection
409  ASSIGN(X_SAT_MAX_15_9 , 0x0),
410 
411  ASSIGN(RSVD , 0),
412  ASSIGN(PARITYCTRL , __MMA_NORMAL)
413 };
414 
415 const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i16u_i16s_o16u =
416 {
417  ASSIGN(A_ATYPE , __MMA_A_CONFIG_ATYPE_UINT16),
418  ASSIGN(A_RSVD1 , 0),
419  ASSIGN(A_ALUTEN , __MMA_A_CONFIG_NOLUT),
420  ASSIGN(A_RSVD2 , 0),
421  ASSIGN(A_ARF_CTRL , __MMA_A_CONFIG_ARF_DISABLE),
422  ASSIGN(A_ARF_BASE , 0),
423  ASSIGN(A_RSVD3 , 0),
424  ASSIGN(A_ARF_SIZE , 0),
425  ASSIGN(A_RSVD4 , 0),
426 
427  ASSIGN(B_BSWPER , FFTLIB_MMA_SIZE_16_BIT), // 32 bits
428  ASSIGN(B_BRSTPER , FFTLIB_MMA_SIZE_16_BIT), // 8 bits
429  ASSIGN(B_BTYPE , __MMA_B_CONFIG_SIZE16), // 2 bits
430  ASSIGN(B_LDBOPT , __MMA_LDBOPT_MMA1),
431  ASSIGN(B_B4EXP , __MMA_B_CONFIG_B4EXP_MMA1),
432  ASSIGN(B_RSVD1 , 0),
433  ASSIGN(B_ORDER , __MMA_B_CONFIG_ROW), // 1 bit
434  ASSIGN(B_RSVD2 , 0),
435  ASSIGN(B_BSTART , 0), // 1 bits
436  ASSIGN(B_BCNT1_ENABLE , 0),
437  ASSIGN(B_RSVD3 , 0),
438  ASSIGN(B_BOFFSET , 0), // 8 bits
439  ASSIGN(B_RSVD4 , 0),
440 
441  ASSIGN(C_ATYPE , __MMA_C_CONFIG_ATYPE_UA),
442  ASSIGN(C_ARF_BASE , 0),
443  ASSIGN(C_ARF_C7 , 0),
444  ASSIGN(C_BTYPE , __MMA_C_CONFIG_BTYPE_INT16),
445  ASSIGN(C_RSVD2 , 0),
446  ASSIGN(C_OPERATION0 , __MMA_C_CONFIG_MUL),
447  ASSIGN(C_LOP0, __MMA_C_CONFIG_LOP_C),
448  ASSIGN(C_RSVD3 , 0),
449  ASSIGN(C_OPERATION1 , __MMA_C_CONFIG_MULPLUS),
450  ASSIGN(C_LOP1, __MMA_C_CONFIG_LOP_C),
451  ASSIGN(C_BIASORDER , __MMA_C_CONFIG_BIAS_ORDER_COLUMN),
452  ASSIGN(C_RSVD4 , 0),
453  ASSIGN(C_HWLDDST , __MMA_C_CONFIG_HWLDDST_X4_0),
454  ASSIGN(C_RSVD5 , 0),
455  ASSIGN(C_HWLDTYPE , __MMA_C_CONFIG_HWLDTYPE_INT16),
456  ASSIGN(C_RSVD6 , 0),
457  ASSIGN(C_OPSTART , __MMA_C_CONFIG_OPSTART_OPERATION0), // No enum in MMA spec? Initial C operand selections
458  ASSIGN(C_BSTART , 0x0), // Initial B bank selection for reading B matrix data
459  ASSIGN(C_CRSTART , 0x0), // Initial C bank selection for reading operands
460  ASSIGN(C_CWSTART , 0x0), // Initial C bank selection for writing computation results
461  ASSIGN(C_CLSTART , 0x0), // Initial C bank selection for writing operands from HWALD*
462  ASSIGN(C_RSVD7 , 0),
463  ASSIGN(C_CROFFSET , 0x0), // 6-bits C row read offset
464  ASSIGN(C_RSVD8 , 0),
465  ASSIGN(C_CWOFFSET , 0x0), // C row write offset for computations
466  ASSIGN(C_RSVD9 , 0),
467  ASSIGN(C_CLOFFSET , 0x0), // C row write offset for HWALD* instructions
468  ASSIGN(C_RSVD10 , 0),
469  ASSIGN(C_CLSWPER , 0), // C bank switch period for HWALD* instruction writes
470  ASSIGN(C_CLRSTPER , 0), // C write row offset reset period for HWALD*
471  ASSIGN(C_OP1PER , 0), // Operation 1 period
472  ASSIGN(C_OP0PER , FFTLIB_MMA_SIZE_16_BIT), // Operation 0 period
473  ASSIGN(C_BSWPER , FFTLIB_MMA_SIZE_16_BIT), // B bank switch period
474  ASSIGN(C_CRSWPER , 0), // C bank switch period for read instructions
475  ASSIGN(C_CWSWPER , 0), // C bank switch period for computation writes
476  ASSIGN(C_CRRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C read row offset reset period
477  ASSIGN(C_CWRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C write row offset reset period for computations
478 
479  ASSIGN(X_ReLU , 0x1), // Enable Rectified Linear Units non-linearity after optional saturation
480  ASSIGN(X_PSAT , 0),
481  ASSIGN(X_SAT_MIN_5_0 , 0),
482  ASSIGN(X_SAT , 0x1), // Enable saturation in the transfer buffer element type after optional rounding
483  ASSIGN(X_SAT_MIN_12_6 , 0),
484  ASSIGN(X_RE , 0x1), // Enable routing via 1/2 LSB addition after shifting
485  ASSIGN(X_SAT_MIN_15_13, 0),
486  ASSIGN(X_RANGE, __MMA_X_CONFIG_RANGE_DISABLE_NOINIT),
487  ASSIGN(X_SCALE_SHIFT_CTRL, __MMA_X_CONFIG_SCALE_SHIFT_CTRL_DISABLE),
488  ASSIGN(X_RSVD3 , 0),
489  ASSIGN(X_SHIFT , 0), // 7 bits Right shift amount), signed or unsigned depending on CTYPE fieldASSIGN(
490  ASSIGN(X_VPACKN , __MMA_X_CONFIG_VPACKN_DISABLE),
491  ASSIGN(X_XTYPE , __MMA_X_CONFIG_XTYPE_UINT16), // Transfer buffer element typeASSIGN( Not all combinations of CTYPE and XTYPE are supported
492  ASSIGN(X_SAT_MAX_3_0 , 0),
493  ASSIGN(X_CTYPE , __MMA_X_CONFIG_CTYPE_INT64), // C matrix element typeASSIGN( This must be consistent with the B FSM setting
494  ASSIGN(X_SAT_MAX_8_4 , 0),
495  ASSIGN(X_CSWPER , FFTLIB_MMA_SIZE_16_BIT), // C read bank switch period
496  ASSIGN(X_CRRSTPER , FFTLIB_MMA_SIZE_16_BIT), // C read row offset reset period
497  ASSIGN(X_COFFSET , 0x0), // C matrix row read address offset
498  ASSIGN(X_CSTART , 0x0), // Initial C bank selection
499  ASSIGN(X_SAT_MAX_15_9 , 0x0),
500 
501  ASSIGN(RSVD , 0),
502  ASSIGN(PARITYCTRL , __MMA_NORMAL)
503 };
504 
505 
506 /********************************
507  * Typical 8-bit configurations *
508  ********************************/
509 
510 const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i8s_i8s_o8s =
511 {
512  ASSIGN(A_ATYPE , __MMA_A_CONFIG_ATYPE_INT8),
513  ASSIGN(A_RSVD1 , 0),
514  ASSIGN(A_ALUTEN , __MMA_A_CONFIG_NOLUT),
515  ASSIGN(A_RSVD2 , 0),
516  ASSIGN(A_ARF_CTRL , __MMA_A_CONFIG_ARF_DISABLE),
517  ASSIGN(A_ARF_BASE , 0),
518  ASSIGN(A_RSVD3 , 0),
519  ASSIGN(A_ARF_SIZE , 0),
520  ASSIGN(A_RSVD4 , 0),
521 
522  ASSIGN(B_BSWPER , FFTLIB_MMA_SIZE_8_BIT), // 32 bits
523  ASSIGN(B_BRSTPER , FFTLIB_MMA_SIZE_8_BIT), // 8 bits
524  ASSIGN(B_BTYPE , __MMA_B_CONFIG_SIZE8), // 2 bits
525  ASSIGN(B_LDBOPT , __MMA_LDBOPT_MMA1),
526  ASSIGN(B_B4EXP , __MMA_B_CONFIG_B4EXP_MMA1),
527  ASSIGN(B_RSVD1 , 0),
528  ASSIGN(B_ORDER , __MMA_B_CONFIG_ROW), // 1 bit
529  ASSIGN(B_RSVD2 , 0),
530  ASSIGN(B_BSTART , 0), // 1 bits
531  ASSIGN(B_BCNT1_ENABLE , 0),
532  ASSIGN(B_RSVD3 , 0),
533  ASSIGN(B_BOFFSET , 0), // 8 bits
534  ASSIGN(B_RSVD4 , 0),
535 
536  ASSIGN(C_ATYPE , __MMA_C_CONFIG_ATYPE_SA),
537  ASSIGN(C_ARF_BASE , 0),
538  ASSIGN(C_ARF_C7 , 0),
539  ASSIGN(C_BTYPE , __MMA_C_CONFIG_BTYPE_INT8),
540  ASSIGN(C_RSVD2 , 0),
541  ASSIGN(C_OPERATION0 , __MMA_C_CONFIG_MUL),
542  ASSIGN(C_LOP0, __MMA_C_CONFIG_LOP_C),
543  ASSIGN(C_RSVD3 , 0),
544  ASSIGN(C_OPERATION1 , __MMA_C_CONFIG_MULPLUS),
545  ASSIGN(C_LOP1, __MMA_C_CONFIG_LOP_C),
546  ASSIGN(C_BIASORDER , __MMA_C_CONFIG_BIAS_ORDER_COLUMN),
547  ASSIGN(C_RSVD4 , 0),
548  ASSIGN(C_HWLDDST , __MMA_C_CONFIG_HWLDDST_X4_0),
549  ASSIGN(C_RSVD5 , 0),
550  ASSIGN(C_HWLDTYPE , __MMA_C_CONFIG_HWLDTYPE_INT8),
551  ASSIGN(C_RSVD6 , 0),
552 
553  ASSIGN(C_OPSTART , __MMA_C_CONFIG_OPSTART_OPERATION0), // No enum in MMA spec? Initial C operand selections
554  ASSIGN(C_BSTART , 0x0), // Initial B bank selection for reading B matrix data
555  ASSIGN(C_CRSTART , 0x0), // Initial C bank selection for reading operands
556  ASSIGN(C_CWSTART , 0x0), // Initial C bank selection for writing computation results
557  ASSIGN(C_CLSTART , 0x0), // Initial C bank selection for writing operands from HWALD*
558  ASSIGN(C_RSVD7 , 0),
559  ASSIGN(C_CROFFSET , 0x0), // 6-bits C row read offset
560  ASSIGN(C_RSVD8 , 0),
561  ASSIGN(C_CWOFFSET , 0x0), // C row write offset for computations
562  ASSIGN(C_RSVD9 , 0),
563  ASSIGN(C_CLOFFSET , 0x0), // C row write offset for HWALD* instructions
564  ASSIGN(C_RSVD10 , 0),
565  ASSIGN(C_CLSWPER , 0), // C bank switch period for HWALD* instruction writes
566  ASSIGN(C_CLRSTPER , 0), // C write row offset reset period for HWALD*
567  ASSIGN(C_OP1PER , 0), // Operation 1 period
568  ASSIGN(C_OP0PER , FFTLIB_MMA_SIZE_8_BIT), // Operation 0 period
569  ASSIGN(C_BSWPER , FFTLIB_MMA_SIZE_8_BIT), // B bank switch period
570  ASSIGN(C_CRSWPER , 0), // C bank switch period for read instructions
571  ASSIGN(C_CWSWPER , 0), // C bank switch period for computation writes
572  ASSIGN(C_CRRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C read row offset reset period
573  ASSIGN(C_CWRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C write row offset reset period for computations
574 
575  ASSIGN(X_ReLU , 0x0), // Enable Rectified Linear Units non-linearity after optional saturation
576  ASSIGN(X_PSAT , 0),
577  ASSIGN(X_SAT_MIN_5_0 , 0),
578  ASSIGN(X_SAT , 0x1), // Enable saturation in the transfer buffer element type after optional rounding
579  ASSIGN(X_SAT_MIN_12_6 , 0),
580  ASSIGN(X_RE , 0x1), // Enable routing via 1/2 LSB addition after shifting
581  ASSIGN(X_SAT_MIN_15_13, 0),
582  ASSIGN(X_RANGE, __MMA_X_CONFIG_RANGE_DISABLE_NOINIT),
583  ASSIGN(X_SCALE_SHIFT_CTRL, __MMA_X_CONFIG_SCALE_SHIFT_CTRL_DISABLE),
584  ASSIGN(X_RSVD3 , 0),
585  ASSIGN(X_SHIFT , 0), // 7 bits Right shift amount), signed or unsigned depending on CTYPE fieldASSIGN(
586  ASSIGN(X_VPACKN , __MMA_X_CONFIG_VPACKN_DISABLE),
587  ASSIGN(X_XTYPE , __MMA_X_CONFIG_XTYPE_INT8), // Transfer buffer element typeASSIGN( Not all combinations of CTYPE and XTYPE are supported
588  ASSIGN(X_SAT_MAX_3_0 , 0),
589  ASSIGN(X_CTYPE , __MMA_X_CONFIG_CTYPE_INT32), // C matrix element typeASSIGN( This must be consistent with the B FSM setting
590  ASSIGN(X_SAT_MAX_8_4 , 0),
591  ASSIGN(X_CSWPER , FFTLIB_MMA_SIZE_8_BIT), // C read bank switch period
592  ASSIGN(X_CRRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C read row offset reset period
593  ASSIGN(X_COFFSET , 0x0), // C matrix row read address offset
594  ASSIGN(X_CSTART , 0x0), // Initial C bank selection
595  ASSIGN(X_SAT_MAX_15_9 , 0x0),
596 
597  ASSIGN(RSVD , 0),
598  ASSIGN(PARITYCTRL , __MMA_NORMAL)
599 };
600 
601 
602 const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i8s_i8s_o8u =
603 {
604  ASSIGN(A_ATYPE , __MMA_A_CONFIG_ATYPE_INT8),
605  ASSIGN(A_RSVD1 , 0),
606  ASSIGN(A_ALUTEN , __MMA_A_CONFIG_NOLUT),
607  ASSIGN(A_RSVD2 , 0),
608  ASSIGN(A_ARF_CTRL , __MMA_A_CONFIG_ARF_DISABLE),
609  ASSIGN(A_ARF_BASE , 0),
610  ASSIGN(A_RSVD3 , 0),
611  ASSIGN(A_ARF_SIZE , 0),
612  ASSIGN(A_RSVD4 , 0),
613 
614  ASSIGN(B_BSWPER , FFTLIB_MMA_SIZE_8_BIT), // 32 bits
615  ASSIGN(B_BRSTPER , FFTLIB_MMA_SIZE_8_BIT), // 8 bits
616  ASSIGN(B_BTYPE , __MMA_B_CONFIG_SIZE8), // 2 bits
617  ASSIGN(B_LDBOPT , __MMA_LDBOPT_MMA1),
618  ASSIGN(B_B4EXP , __MMA_B_CONFIG_B4EXP_MMA1),
619  ASSIGN(B_RSVD1 , 0),
620  ASSIGN(B_ORDER , __MMA_B_CONFIG_ROW), // 1 bit
621  ASSIGN(B_RSVD2 , 0),
622  ASSIGN(B_BSTART , 0), // 1 bits
623  ASSIGN(B_BCNT1_ENABLE , 0),
624  ASSIGN(B_RSVD3 , 0),
625  ASSIGN(B_BOFFSET , 0), // 8 bits
626  ASSIGN(B_RSVD4 , 0),
627 
628  ASSIGN(C_ATYPE , __MMA_C_CONFIG_ATYPE_SA),
629  ASSIGN(C_ARF_BASE , 0),
630  ASSIGN(C_ARF_C7 , 0),
631  ASSIGN(C_BTYPE , __MMA_C_CONFIG_BTYPE_INT8),
632  ASSIGN(C_RSVD2 , 0),
633  ASSIGN(C_OPERATION0 , __MMA_C_CONFIG_MUL),
634  ASSIGN(C_LOP0, __MMA_C_CONFIG_LOP_C),
635  ASSIGN(C_RSVD3 , 0),
636  ASSIGN(C_OPERATION1 , __MMA_C_CONFIG_MULPLUS),
637  ASSIGN(C_LOP1, __MMA_C_CONFIG_LOP_C),
638  ASSIGN(C_BIASORDER , __MMA_C_CONFIG_BIAS_ORDER_COLUMN),
639  ASSIGN(C_RSVD4 , 0),
640  ASSIGN(C_HWLDDST , __MMA_C_CONFIG_HWLDDST_X4_0),
641  ASSIGN(C_RSVD5 , 0),
642  ASSIGN(C_HWLDTYPE , __MMA_C_CONFIG_HWLDTYPE_INT8),
643  ASSIGN(C_RSVD6 , 0),
644 
645  ASSIGN(C_OPSTART , __MMA_C_CONFIG_OPSTART_OPERATION0), // No enum in MMA spec? Initial C operand selections
646  ASSIGN(C_BSTART , 0x0), // Initial B bank selection for reading B matrix data
647  ASSIGN(C_CRSTART , 0x0), // Initial C bank selection for reading operands
648  ASSIGN(C_CWSTART , 0x0), // Initial C bank selection for writing computation results
649  ASSIGN(C_CLSTART , 0x0), // Initial C bank selection for writing operands from HWALD*
650  ASSIGN(C_RSVD7 , 0),
651  ASSIGN(C_CROFFSET , 0x0), // 6-bits C row read offset
652  ASSIGN(C_RSVD8 , 0),
653  ASSIGN(C_CWOFFSET , 0x0), // C row write offset for computations
654  ASSIGN(C_RSVD9 , 0),
655  ASSIGN(C_CLOFFSET , 0x0), // C row write offset for HWALD* instructions
656  ASSIGN(C_RSVD10 , 0),
657  ASSIGN(C_CLSWPER , 0), // C bank switch period for HWALD* instruction writes
658  ASSIGN(C_CLRSTPER , 0), // C write row offset reset period for HWALD*
659  ASSIGN(C_OP1PER , 0), // Operation 1 period
660  ASSIGN(C_OP0PER , FFTLIB_MMA_SIZE_8_BIT), // Operation 0 period
661  ASSIGN(C_BSWPER , FFTLIB_MMA_SIZE_8_BIT), // B bank switch period
662  ASSIGN(C_CRSWPER , 0), // C bank switch period for read instructions
663  ASSIGN(C_CWSWPER , 0), // C bank switch period for computation writes
664  ASSIGN(C_CRRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C read row offset reset period
665  ASSIGN(C_CWRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C write row offset reset period for computations
666 
667  ASSIGN(X_ReLU , 0x1), // Enable Rectified Linear Units non-linearity after optional saturation
668  ASSIGN(X_PSAT , 0),
669  ASSIGN(X_SAT_MIN_5_0 , 0),
670  ASSIGN(X_SAT , 0x0), // Enable saturation in the transfer buffer element type after optional rounding
671  ASSIGN(X_SAT_MIN_12_6 , 0),
672  ASSIGN(X_RE , 0x1), // Enable routing via 1/2 LSB addition after shifting
673  ASSIGN(X_SAT_MIN_15_13, 0),
674  ASSIGN(X_RANGE, __MMA_X_CONFIG_RANGE_DISABLE_NOINIT),
675  ASSIGN(X_SCALE_SHIFT_CTRL, __MMA_X_CONFIG_SCALE_SHIFT_CTRL_DISABLE),
676  ASSIGN(X_RSVD3 , 0),
677  ASSIGN(X_SHIFT , 0), // 7 bits Right shift amount), signed or unsigned depending on CTYPE fieldASSIGN(
678  ASSIGN(X_VPACKN , __MMA_X_CONFIG_VPACKN_DISABLE),
679  ASSIGN(X_XTYPE , __MMA_X_CONFIG_XTYPE_UINT8), // Transfer buffer element typeASSIGN( Not all combinations of CTYPE and XTYPE are supported
680  ASSIGN(X_SAT_MAX_3_0 , 0),
681  ASSIGN(X_CTYPE , __MMA_X_CONFIG_CTYPE_INT32), // C matrix element typeASSIGN( This must be consistent with the B FSM setting
682  ASSIGN(X_SAT_MAX_8_4 , 0),
683  ASSIGN(X_CSWPER , FFTLIB_MMA_SIZE_8_BIT), // C read bank switch period
684  ASSIGN(X_CRRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C read row offset reset period
685  ASSIGN(X_COFFSET , 0x0), // C matrix row read address offset
686  ASSIGN(X_CSTART , 0x0), // Initial C bank selection
687  ASSIGN(X_SAT_MAX_15_9 , 0x0),
688 
689  ASSIGN(RSVD , 0),
690  ASSIGN(PARITYCTRL , __MMA_NORMAL)
691 };
692 
693 
694 const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i8u_i8s_o8s =
695 {
696  ASSIGN(A_ATYPE , __MMA_A_CONFIG_ATYPE_UINT8),
697  ASSIGN(A_RSVD1 , 0),
698  ASSIGN(A_ALUTEN , __MMA_A_CONFIG_NOLUT),
699  ASSIGN(A_RSVD2 , 0),
700  ASSIGN(A_ARF_CTRL , __MMA_A_CONFIG_ARF_DISABLE),
701  ASSIGN(A_ARF_BASE , 0),
702  ASSIGN(A_RSVD3 , 0),
703  ASSIGN(A_ARF_SIZE , 0),
704  ASSIGN(A_RSVD4 , 0),
705 
706  ASSIGN(B_BSWPER , FFTLIB_MMA_SIZE_8_BIT), // 32 bits
707  ASSIGN(B_BRSTPER , FFTLIB_MMA_SIZE_8_BIT), // 8 bits
708  ASSIGN(B_BTYPE , __MMA_B_CONFIG_SIZE8), // 2 bits
709  ASSIGN(B_LDBOPT , __MMA_LDBOPT_MMA1),
710  ASSIGN(B_B4EXP , __MMA_B_CONFIG_B4EXP_MMA1),
711  ASSIGN(B_RSVD1 , 0),
712  ASSIGN(B_ORDER , __MMA_B_CONFIG_ROW), // 1 bit
713  ASSIGN(B_RSVD2 , 0),
714  ASSIGN(B_BSTART , 0), // 1 bits
715  ASSIGN(B_BCNT1_ENABLE , 0),
716  ASSIGN(B_RSVD3 , 0),
717  ASSIGN(B_BOFFSET , 0), // 8 bits
718  ASSIGN(B_RSVD4 , 0),
719 
720  ASSIGN(C_ATYPE , __MMA_C_CONFIG_ATYPE_UA),
721  ASSIGN(C_ARF_BASE , 0),
722  ASSIGN(C_ARF_C7 , 0),
723  ASSIGN(C_BTYPE , __MMA_C_CONFIG_BTYPE_INT8),
724  ASSIGN(C_RSVD2 , 0),
725  ASSIGN(C_OPERATION0 , __MMA_C_CONFIG_MUL),
726  ASSIGN(C_LOP0, __MMA_C_CONFIG_LOP_C),
727  ASSIGN(C_RSVD3 , 0),
728  ASSIGN(C_OPERATION1 , __MMA_C_CONFIG_MULPLUS),
729  ASSIGN(C_LOP1, __MMA_C_CONFIG_LOP_C),
730  ASSIGN(C_BIASORDER , __MMA_C_CONFIG_BIAS_ORDER_COLUMN),
731  ASSIGN(C_RSVD4 , 0),
732  ASSIGN(C_HWLDDST , __MMA_C_CONFIG_HWLDDST_X4_0),
733  ASSIGN(C_RSVD5 , 0),
734  ASSIGN(C_HWLDTYPE , __MMA_C_CONFIG_HWLDTYPE_INT8),
735  ASSIGN(C_RSVD6 , 0),
736 
737  ASSIGN(C_OPSTART , __MMA_C_CONFIG_OPSTART_OPERATION0), // No enum in MMA spec? Initial C operand selections
738  ASSIGN(C_BSTART , 0x0), // Initial B bank selection for reading B matrix data
739  ASSIGN(C_CRSTART , 0x0), // Initial C bank selection for reading operands
740  ASSIGN(C_CWSTART , 0x0), // Initial C bank selection for writing computation results
741  ASSIGN(C_CLSTART , 0x0), // Initial C bank selection for writing operands from HWALD*
742  ASSIGN(C_RSVD7 , 0),
743  ASSIGN(C_CROFFSET , 0x0), // 6-bits C row read offset
744  ASSIGN(C_RSVD8 , 0),
745  ASSIGN(C_CWOFFSET , 0x0), // C row write offset for computations
746  ASSIGN(C_RSVD9 , 0),
747  ASSIGN(C_CLOFFSET , 0x0), // C row write offset for HWALD* instructions
748  ASSIGN(C_RSVD10 , 0),
749  ASSIGN(C_CLSWPER , 0), // C bank switch period for HWALD* instruction writes
750  ASSIGN(C_CLRSTPER , 0), // C write row offset reset period for HWALD*
751  ASSIGN(C_OP1PER , 0), // Operation 1 period
752  ASSIGN(C_OP0PER , FFTLIB_MMA_SIZE_8_BIT), // Operation 0 period
753  ASSIGN(C_BSWPER , FFTLIB_MMA_SIZE_8_BIT), // B bank switch period
754  ASSIGN(C_CRSWPER , 0), // C bank switch period for read instructions
755  ASSIGN(C_CWSWPER , 0), // C bank switch period for computation writes
756  ASSIGN(C_CRRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C read row offset reset period
757  ASSIGN(C_CWRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C write row offset reset period for computations
758 
759  ASSIGN(X_ReLU , 0x0), // Enable Rectified Linear Units non-linearity after optional saturation
760  ASSIGN(X_PSAT , 0),
761  ASSIGN(X_SAT_MIN_5_0 , 0),
762  ASSIGN(X_SAT , 0x1), // Enable saturation in the transfer buffer element type after optional rounding
763  ASSIGN(X_SAT_MIN_12_6 , 0),
764  ASSIGN(X_RE , 0x1), // Enable routing via 1/2 LSB addition after shifting
765  ASSIGN(X_SAT_MIN_15_13, 0),
766  ASSIGN(X_RANGE, __MMA_X_CONFIG_RANGE_DISABLE_NOINIT),
767  ASSIGN(X_SCALE_SHIFT_CTRL, __MMA_X_CONFIG_SCALE_SHIFT_CTRL_DISABLE),
768  ASSIGN(X_RSVD3 , 0),
769  ASSIGN(X_SHIFT , 0), // 7 bits Right shift amount), signed or unsigned depending on CTYPE fieldASSIGN(
770  ASSIGN(X_VPACKN , __MMA_X_CONFIG_VPACKN_DISABLE),
771  ASSIGN(X_XTYPE , __MMA_X_CONFIG_XTYPE_INT8), // Transfer buffer element typeASSIGN( Not all combinations of CTYPE and XTYPE are supported
772  ASSIGN(X_SAT_MAX_3_0 , 0),
773  ASSIGN(X_CTYPE , __MMA_X_CONFIG_CTYPE_INT32), // C matrix element typeASSIGN( This must be consistent with the B FSM setting
774  ASSIGN(X_SAT_MAX_8_4 , 0),
775  ASSIGN(X_CSWPER , FFTLIB_MMA_SIZE_8_BIT), // C read bank switch period
776  ASSIGN(X_CRRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C read row offset reset period
777  ASSIGN(X_COFFSET , 0x0), // C matrix row read address offset
778  ASSIGN(X_CSTART , 0x0), // Initial C bank selection
779  ASSIGN(X_SAT_MAX_15_9 , 0x0),
780 
781  ASSIGN(RSVD , 0),
782  ASSIGN(PARITYCTRL , __MMA_NORMAL)
783 };
784 
785 const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i8u_i8s_o8u =
786 {
787  ASSIGN(A_ATYPE , __MMA_A_CONFIG_ATYPE_UINT8),
788  ASSIGN(A_RSVD1 , 0),
789  ASSIGN(A_ALUTEN , __MMA_A_CONFIG_NOLUT),
790  ASSIGN(A_RSVD2 , 0),
791  ASSIGN(A_ARF_CTRL , __MMA_A_CONFIG_ARF_DISABLE),
792  ASSIGN(A_ARF_BASE , 0),
793  ASSIGN(A_RSVD3 , 0),
794  ASSIGN(A_ARF_SIZE , 0),
795  ASSIGN(A_RSVD4 , 0),
796 
797  ASSIGN(B_BSWPER , FFTLIB_MMA_SIZE_8_BIT), // 32 bits
798  ASSIGN(B_BRSTPER , FFTLIB_MMA_SIZE_8_BIT), // 8 bits
799  ASSIGN(B_BTYPE , __MMA_B_CONFIG_SIZE8), // 2 bits
800  ASSIGN(B_LDBOPT , __MMA_LDBOPT_MMA1),
801  ASSIGN(B_B4EXP , __MMA_B_CONFIG_B4EXP_MMA1),
802  ASSIGN(B_RSVD1 , 0),
803  ASSIGN(B_ORDER , __MMA_B_CONFIG_ROW), // 1 bit
804  ASSIGN(B_RSVD2 , 0),
805  ASSIGN(B_BSTART , 0), // 1 bits
806  ASSIGN(B_BCNT1_ENABLE , 0),
807  ASSIGN(B_RSVD3 , 0),
808  ASSIGN(B_BOFFSET , 0), // 8 bits
809  ASSIGN(B_RSVD4 , 0),
810 
811  ASSIGN(C_ATYPE , __MMA_C_CONFIG_ATYPE_UA),
812  ASSIGN(C_ARF_BASE , 0),
813  ASSIGN(C_ARF_C7 , 0),
814  ASSIGN(C_BTYPE , __MMA_C_CONFIG_BTYPE_INT8),
815  ASSIGN(C_RSVD2 , 0),
816  ASSIGN(C_OPERATION0 , __MMA_C_CONFIG_MUL),
817  ASSIGN(C_LOP0, __MMA_C_CONFIG_LOP_C),
818  ASSIGN(C_RSVD3 , 0),
819  ASSIGN(C_OPERATION1 , __MMA_C_CONFIG_MULPLUS),
820  ASSIGN(C_LOP1, __MMA_C_CONFIG_LOP_C),
821  ASSIGN(C_BIASORDER , __MMA_C_CONFIG_BIAS_ORDER_COLUMN),
822  ASSIGN(C_RSVD4 , 0),
823  ASSIGN(C_HWLDDST , __MMA_C_CONFIG_HWLDDST_X4_0),
824  ASSIGN(C_RSVD5 , 0),
825  ASSIGN(C_HWLDTYPE , __MMA_C_CONFIG_HWLDTYPE_INT8),
826  ASSIGN(C_RSVD6 , 0),
827  ASSIGN(C_OPSTART , __MMA_C_CONFIG_OPSTART_OPERATION0), // No enum in MMA spec? Initial C operand selections
828  ASSIGN(C_BSTART , 0x0), // Initial B bank selection for reading B matrix data
829  ASSIGN(C_CRSTART , 0x0), // Initial C bank selection for reading operands
830  ASSIGN(C_CWSTART , 0x0), // Initial C bank selection for writing computation results
831  ASSIGN(C_CLSTART , 0x0), // Initial C bank selection for writing operands from HWALD*
832  ASSIGN(C_RSVD7 , 0),
833  ASSIGN(C_CROFFSET , 0x0), // 6-bits C row read offset
834  ASSIGN(C_RSVD8 , 0),
835  ASSIGN(C_CWOFFSET , 0x0), // C row write offset for computations
836  ASSIGN(C_RSVD9 , 0),
837  ASSIGN(C_CLOFFSET , 0x0), // C row write offset for HWALD* instructions
838  ASSIGN(C_RSVD10 , 0),
839  ASSIGN(C_CLSWPER , 0), // C bank switch period for HWALD* instruction writes
840  ASSIGN(C_CLRSTPER , 0), // C write row offset reset period for HWALD*
841  ASSIGN(C_OP1PER , 0), // Operation 1 period
842  ASSIGN(C_OP0PER , FFTLIB_MMA_SIZE_8_BIT), // Operation 0 period
843  ASSIGN(C_BSWPER , FFTLIB_MMA_SIZE_8_BIT), // B bank switch period
844  ASSIGN(C_CRSWPER , 0), // C bank switch period for read instructions
845  ASSIGN(C_CWSWPER , 0), // C bank switch period for computation writes
846  ASSIGN(C_CRRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C read row offset reset period
847  ASSIGN(C_CWRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C write row offset reset period for computations
848 
849  ASSIGN(X_ReLU , 0x1), // Enable Rectified Linear Units non-linearity after optional saturation
850  ASSIGN(X_PSAT , 0),
851  ASSIGN(X_SAT_MIN_5_0 , 0),
852  ASSIGN(X_SAT , 0x1), // Enable saturation in the transfer buffer element type after optional rounding
853  ASSIGN(X_SAT_MIN_12_6 , 0),
854  ASSIGN(X_RE , 0x1), // Enable routing via 1/2 LSB addition after shifting
855  ASSIGN(X_SAT_MIN_15_13, 0),
856  ASSIGN(X_RANGE, __MMA_X_CONFIG_RANGE_DISABLE_NOINIT),
857  ASSIGN(X_SCALE_SHIFT_CTRL, __MMA_X_CONFIG_SCALE_SHIFT_CTRL_DISABLE),
858  ASSIGN(X_RSVD3 , 0),
859  ASSIGN(X_SHIFT , 0), // 7 bits Right shift amount), signed or unsigned depending on CTYPE fieldASSIGN(
860  ASSIGN(X_VPACKN , __MMA_X_CONFIG_VPACKN_DISABLE),
861  ASSIGN(X_XTYPE , __MMA_X_CONFIG_XTYPE_UINT8), // Transfer buffer element typeASSIGN( Not all combinations of CTYPE and XTYPE are supported
862  ASSIGN(X_SAT_MAX_3_0 , 0),
863  ASSIGN(X_CTYPE , __MMA_X_CONFIG_CTYPE_INT32), // C matrix element typeASSIGN( This must be consistent with the B FSM setting
864  ASSIGN(X_SAT_MAX_8_4 , 0),
865  ASSIGN(X_CSWPER , FFTLIB_MMA_SIZE_8_BIT), // C read bank switch period
866  ASSIGN(X_CRRSTPER , FFTLIB_MMA_SIZE_8_BIT), // C read row offset reset period
867  ASSIGN(X_COFFSET , 0x0), // C matrix row read address offset
868  ASSIGN(X_CSTART , 0x0), // Initial C bank selection
869  ASSIGN(X_SAT_MAX_15_9 , 0x0),
870 
871  ASSIGN(RSVD , 0),
872  ASSIGN(PARITYCTRL , __MMA_NORMAL)
873 };
874 
875 /* -------------------------------------------------------------------------- */
876 /* MISRAC Rule 4.9(DEFINE.FUNC) Deviation: The advisory is not being */
877 /* addressed so as not to lose portability across different platforms. */
878 /* -------------------------------------------------------------------------- */
879 #ifdef WIN32
880 #define ASSIGN(param, value) value
881 #else
882 #define ASSIGN(param, value) .param = value
883 #endif
884 const __HWA_OFFSET_REG offsetRegStruct_zeros =
885 {
886  ASSIGN(offset0 , 0),
887  ASSIGN(offset1 , 0),
888  ASSIGN(offset2 , 0),
889  ASSIGN(offset3 , 0),
890  ASSIGN(A_LUT_VAL_0 , 0),
891  ASSIGN(offset4 , 0),
892  ASSIGN(offset5 , 0),
893  ASSIGN(offset6 , 0),
894  ASSIGN(offset7 , 0),
895  ASSIGN(A_LUT_VAL_1 , 0),
896  ASSIGN(offset8 , 0),
897  ASSIGN(offset9 , 0),
898  ASSIGN(offset10 , 0),
899  ASSIGN(offset11 , 0),
900  ASSIGN(A_LUT_VAL_2 , 0),
901  ASSIGN(offset12 , 0),
902  ASSIGN(offset13 , 0),
903  ASSIGN(offset14 , 0),
904  ASSIGN(offset15 , 0),
905  ASSIGN(A_LUT_VAL_3 , 0),
906  ASSIGN(offset16 , 0),
907  ASSIGN(offset17 , 0),
908  ASSIGN(offset18 , 0),
909  ASSIGN(offset19 , 0),
910  ASSIGN(A_LUT_VAL_4 , 0),
911  ASSIGN(offset20 , 0),
912  ASSIGN(offset21 , 0),
913  ASSIGN(offset22 , 0),
914  ASSIGN(offset23 , 0),
915  ASSIGN(A_LUT_VAL_5 , 0),
916  ASSIGN(offset24 , 0),
917  ASSIGN(offset25 , 0),
918  ASSIGN(offset26 , 0),
919  ASSIGN(offset27 , 0),
920  ASSIGN(A_LUT_VAL_6 , 0),
921  ASSIGN(offset28 , 0),
922  ASSIGN(offset29 , 0),
923  ASSIGN(offset30 , 0),
924  ASSIGN(offset31 , 0),
925  ASSIGN(A_LUT_VAL_7 , 0),
926  ASSIGN(offset32 , 0),
927  ASSIGN(offset33 , 0),
928  ASSIGN(offset34 , 0),
929  ASSIGN(offset35 , 0),
930  ASSIGN(A_LUT_VAL_8 , 0),
931  ASSIGN(offset36 , 0),
932  ASSIGN(offset37 , 0),
933  ASSIGN(offset38 , 0),
934  ASSIGN(offset39 , 0),
935  ASSIGN(A_LUT_VAL_9 , 0),
936  ASSIGN(offset40 , 0),
937  ASSIGN(offset41 , 0),
938  ASSIGN(offset42 , 0),
939  ASSIGN(offset43 , 0),
940  ASSIGN(A_LUT_VAL_10 , 0),
941  ASSIGN(offset44 , 0),
942  ASSIGN(offset45 , 0),
943  ASSIGN(offset46 , 0),
944  ASSIGN(offset47 , 0),
945  ASSIGN(A_LUT_VAL_11 , 0),
946  ASSIGN(offset48 , 0),
947  ASSIGN(offset49 , 0),
948  ASSIGN(offset50 , 0),
949  ASSIGN(offset51 , 0),
950  ASSIGN(A_LUT_VAL_12 , 0),
951  ASSIGN(offset52 , 0),
952  ASSIGN(offset53 , 0),
953  ASSIGN(offset54 , 0),
954  ASSIGN(offset55 , 0),
955  ASSIGN(A_LUT_VAL_13 , 0),
956  ASSIGN(offset56 , 0),
957  ASSIGN(offset57 , 0),
958  ASSIGN(offset58 , 0),
959  ASSIGN(offset59 , 0),
960  ASSIGN(A_LUT_VAL_14 , 0),
961  ASSIGN(offset60 , 0),
962  ASSIGN(offset61 , 0),
963  ASSIGN(offset62 , 0),
964  ASSIGN(offset63 , 0),
965  ASSIGN(A_LUT_VAL_15 , 0)
966 };
967 
968 const __HWA_OFFSET_REG offsetRegStruct_diagonal_32bit =
969 {
970  ASSIGN(offset0 , 0),
971  ASSIGN(offset1 , 0),
972  ASSIGN(offset2 , 0),
973  ASSIGN(offset3 , 0),
974  ASSIGN(A_LUT_VAL_0 , 0),
975  ASSIGN(offset4 , 1),
976  ASSIGN(offset5 , 0),
977  ASSIGN(offset6 , 0),
978  ASSIGN(offset7 , 0),
979  ASSIGN(A_LUT_VAL_1 , 0),
980  ASSIGN(offset8 , 2),
981  ASSIGN(offset9 , 0),
982  ASSIGN(offset10 , 0),
983  ASSIGN(offset11 , 0),
984  ASSIGN(A_LUT_VAL_2 , 0),
985  ASSIGN(offset12 , 3),
986  ASSIGN(offset13 , 0),
987  ASSIGN(offset14 , 0),
988  ASSIGN(offset15 , 0),
989  ASSIGN(A_LUT_VAL_3 , 0),
990  ASSIGN(offset16 , 4),
991  ASSIGN(offset17 , 0),
992  ASSIGN(offset18 , 0),
993  ASSIGN(offset19 , 0),
994  ASSIGN(A_LUT_VAL_4 , 0),
995  ASSIGN(offset20 , 5),
996  ASSIGN(offset21 , 0),
997  ASSIGN(offset22 , 0),
998  ASSIGN(offset23 , 0),
999  ASSIGN(A_LUT_VAL_5 , 0),
1000  ASSIGN(offset24 , 6),
1001  ASSIGN(offset25 , 0),
1002  ASSIGN(offset26 , 0),
1003  ASSIGN(offset27 , 0),
1004  ASSIGN(A_LUT_VAL_6 , 0),
1005  ASSIGN(offset28 , 7),
1006  ASSIGN(offset29 , 0),
1007  ASSIGN(offset30 , 0),
1008  ASSIGN(offset31 , 0),
1009  ASSIGN(A_LUT_VAL_7 , 0),
1010  ASSIGN(offset32 , 8),
1011  ASSIGN(offset33 , 0),
1012  ASSIGN(offset34 , 0),
1013  ASSIGN(offset35 , 0),
1014  ASSIGN(A_LUT_VAL_8 , 0),
1015  ASSIGN(offset36 , 9),
1016  ASSIGN(offset37 , 0),
1017  ASSIGN(offset38 , 0),
1018  ASSIGN(offset39 , 0),
1019  ASSIGN(A_LUT_VAL_9 , 0),
1020  ASSIGN(offset40 , 10),
1021  ASSIGN(offset41 , 0),
1022  ASSIGN(offset42 , 0),
1023  ASSIGN(offset43 , 0),
1024  ASSIGN(A_LUT_VAL_10 , 0),
1025  ASSIGN(offset44 , 11),
1026  ASSIGN(offset45 , 0),
1027  ASSIGN(offset46 , 0),
1028  ASSIGN(offset47 , 0),
1029  ASSIGN(A_LUT_VAL_11 , 0),
1030  ASSIGN(offset48 , 12),
1031  ASSIGN(offset49 , 0),
1032  ASSIGN(offset50 , 0),
1033  ASSIGN(offset51 , 0),
1034  ASSIGN(A_LUT_VAL_12 , 0),
1035  ASSIGN(offset52 , 13),
1036  ASSIGN(offset53 , 0),
1037  ASSIGN(offset54 , 0),
1038  ASSIGN(offset55 , 0),
1039  ASSIGN(A_LUT_VAL_13 , 0),
1040  ASSIGN(offset56 , 14),
1041  ASSIGN(offset57 , 0),
1042  ASSIGN(offset58 , 0),
1043  ASSIGN(offset59 , 0),
1044  ASSIGN(A_LUT_VAL_14 , 0),
1045  ASSIGN(offset60 , 15),
1046  ASSIGN(offset61 , 0),
1047  ASSIGN(offset62 , 0),
1048  ASSIGN(offset63 , 0),
1049  ASSIGN(A_LUT_VAL_15 , 0)
1050 };
1051 
1052 const __HWA_OFFSET_REG offsetRegStruct_diagonal_16bit =
1053 {
1054  ASSIGN(offset0 , 0),
1055  ASSIGN(offset1 , 0),
1056  ASSIGN(offset2 , 1),
1057  ASSIGN(offset3 , 0),
1058  ASSIGN(A_LUT_VAL_0 , 0),
1059  ASSIGN(offset4 , 2),
1060  ASSIGN(offset5 , 0),
1061  ASSIGN(offset6 , 3),
1062  ASSIGN(offset7 , 0),
1063  ASSIGN(A_LUT_VAL_1 , 0),
1064  ASSIGN(offset8 , 4),
1065  ASSIGN(offset9 , 0),
1066  ASSIGN(offset10 , 5),
1067  ASSIGN(offset11 , 0),
1068  ASSIGN(A_LUT_VAL_2 , 0),
1069  ASSIGN(offset12 , 6),
1070  ASSIGN(offset13 , 0),
1071  ASSIGN(offset14 , 7),
1072  ASSIGN(offset15 , 0),
1073  ASSIGN(A_LUT_VAL_3 , 0),
1074  ASSIGN(offset16 , 8),
1075  ASSIGN(offset17 , 0),
1076  ASSIGN(offset18 , 9),
1077  ASSIGN(offset19 , 0),
1078  ASSIGN(A_LUT_VAL_4 , 0),
1079  ASSIGN(offset20 , 10),
1080  ASSIGN(offset21 , 0),
1081  ASSIGN(offset22 , 11),
1082  ASSIGN(offset23 , 0),
1083  ASSIGN(A_LUT_VAL_5 , 0),
1084  ASSIGN(offset24 , 12),
1085  ASSIGN(offset25 , 0),
1086  ASSIGN(offset26 , 13),
1087  ASSIGN(offset27 , 0),
1088  ASSIGN(A_LUT_VAL_6 , 0),
1089  ASSIGN(offset28 , 14),
1090  ASSIGN(offset29 , 0),
1091  ASSIGN(offset30 , 15),
1092  ASSIGN(offset31 , 0),
1093  ASSIGN(A_LUT_VAL_7 , 0),
1094  ASSIGN(offset32 , 16),
1095  ASSIGN(offset33 , 0),
1096  ASSIGN(offset34 , 17),
1097  ASSIGN(offset35 , 0),
1098  ASSIGN(A_LUT_VAL_8 , 0),
1099  ASSIGN(offset36 , 18),
1100  ASSIGN(offset37 , 0),
1101  ASSIGN(offset38 , 19),
1102  ASSIGN(offset39 , 0),
1103  ASSIGN(A_LUT_VAL_9 , 0),
1104  ASSIGN(offset40 , 20),
1105  ASSIGN(offset41 , 0),
1106  ASSIGN(offset42 , 21),
1107  ASSIGN(offset43 , 0),
1108  ASSIGN(A_LUT_VAL_10 , 0),
1109  ASSIGN(offset44 , 22),
1110  ASSIGN(offset45 , 0),
1111  ASSIGN(offset46 , 23),
1112  ASSIGN(offset47 , 0),
1113  ASSIGN(A_LUT_VAL_11 , 0),
1114  ASSIGN(offset48 , 24),
1115  ASSIGN(offset49 , 0),
1116  ASSIGN(offset50 , 25),
1117  ASSIGN(offset51 , 0),
1118  ASSIGN(A_LUT_VAL_12 , 0),
1119  ASSIGN(offset52 , 26),
1120  ASSIGN(offset53 , 0),
1121  ASSIGN(offset54 , 27),
1122  ASSIGN(offset55 , 0),
1123  ASSIGN(A_LUT_VAL_13 , 0),
1124  ASSIGN(offset56 , 28),
1125  ASSIGN(offset57 , 0),
1126  ASSIGN(offset58 , 29),
1127  ASSIGN(offset59 , 0),
1128  ASSIGN(A_LUT_VAL_14 , 0),
1129  ASSIGN(offset60 , 30),
1130  ASSIGN(offset61 , 0),
1131  ASSIGN(offset62 , 31),
1132  ASSIGN(offset63 , 0),
1133  ASSIGN(A_LUT_VAL_15 , 0)
1134 };
1135 
1136 const __HWA_OFFSET_REG offsetRegStruct_diagonal_8bit =
1137 {
1138  ASSIGN(offset0 , 0),
1139  ASSIGN(offset1 , 1),
1140  ASSIGN(offset2 , 2),
1141  ASSIGN(offset3 , 3),
1142  ASSIGN(A_LUT_VAL_0 , 0),
1143  ASSIGN(offset4 , 4),
1144  ASSIGN(offset5 , 5),
1145  ASSIGN(offset6 , 6),
1146  ASSIGN(offset7 , 7),
1147  ASSIGN(A_LUT_VAL_1 , 0),
1148  ASSIGN(offset8 , 8),
1149  ASSIGN(offset9 , 9),
1150  ASSIGN(offset10 , 10),
1151  ASSIGN(offset11 , 11),
1152  ASSIGN(A_LUT_VAL_2 , 0),
1153  ASSIGN(offset12 , 12),
1154  ASSIGN(offset13 , 13),
1155  ASSIGN(offset14 , 14),
1156  ASSIGN(offset15 , 15),
1157  ASSIGN(A_LUT_VAL_3 , 0),
1158  ASSIGN(offset16 , 16),
1159  ASSIGN(offset17 , 17),
1160  ASSIGN(offset18 , 18),
1161  ASSIGN(offset19 , 19),
1162  ASSIGN(A_LUT_VAL_4 , 0),
1163  ASSIGN(offset20 , 20),
1164  ASSIGN(offset21 , 21),
1165  ASSIGN(offset22 , 22),
1166  ASSIGN(offset23 , 23),
1167  ASSIGN(A_LUT_VAL_5 , 0),
1168  ASSIGN(offset24 , 24),
1169  ASSIGN(offset25 , 25),
1170  ASSIGN(offset26 , 26),
1171  ASSIGN(offset27 , 27),
1172  ASSIGN(A_LUT_VAL_6 , 0),
1173  ASSIGN(offset28 , 28),
1174  ASSIGN(offset29 , 29),
1175  ASSIGN(offset30 , 30),
1176  ASSIGN(offset31 , 31),
1177  ASSIGN(A_LUT_VAL_7 , 0),
1178  ASSIGN(offset32 , 32),
1179  ASSIGN(offset33 , 33),
1180  ASSIGN(offset34 , 34),
1181  ASSIGN(offset35 , 35),
1182  ASSIGN(A_LUT_VAL_8 , 0),
1183  ASSIGN(offset36 , 36),
1184  ASSIGN(offset37 , 37),
1185  ASSIGN(offset38 , 38),
1186  ASSIGN(offset39 , 39),
1187  ASSIGN(A_LUT_VAL_9 , 0),
1188  ASSIGN(offset40 , 40),
1189  ASSIGN(offset41 , 41),
1190  ASSIGN(offset42 , 42),
1191  ASSIGN(offset43 , 43),
1192  ASSIGN(A_LUT_VAL_10 , 0),
1193  ASSIGN(offset44 , 44),
1194  ASSIGN(offset45 , 45),
1195  ASSIGN(offset46 , 46),
1196  ASSIGN(offset47 , 47),
1197  ASSIGN(A_LUT_VAL_11 , 0),
1198  ASSIGN(offset48 , 48),
1199  ASSIGN(offset49 , 49),
1200  ASSIGN(offset50 , 50),
1201  ASSIGN(offset51 , 51),
1202  ASSIGN(A_LUT_VAL_12 , 0),
1203  ASSIGN(offset52 , 52),
1204  ASSIGN(offset53 , 53),
1205  ASSIGN(offset54 , 54),
1206  ASSIGN(offset55 , 55),
1207  ASSIGN(A_LUT_VAL_13 , 0),
1208  ASSIGN(offset56 , 56),
1209  ASSIGN(offset57 , 57),
1210  ASSIGN(offset58 , 58),
1211  ASSIGN(offset59 , 59),
1212  ASSIGN(A_LUT_VAL_14 , 0),
1213  ASSIGN(offset60 , 60),
1214  ASSIGN(offset61 , 61),
1215  ASSIGN(offset62 , 62),
1216  ASSIGN(offset63 , 63),
1217  ASSIGN(A_LUT_VAL_15 , 0)
1218 };
1219 
1220 
1221 /* ======================================================================== */
1222 /* End of file: FFTLIB_configurations.c */
1223 /* ======================================================================== */
offsetRegStruct_zeros
const __HWA_OFFSET_REG offsetRegStruct_zeros
Definition: c7100/FFTLIB_configurations.cpp:884
configRegisterStruct_i16s_i16s_o16u
const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i16s_i16s_o16u
Definition: c7100/FFTLIB_configurations.cpp:232
configRegisterStruct_i16s_i16s_o16s
const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i16s_i16s_o16s
Definition: c7100/FFTLIB_configurations.cpp:140
offsetRegStruct_diagonal_16bit
const __HWA_OFFSET_REG offsetRegStruct_diagonal_16bit
Definition: c7100/FFTLIB_configurations.cpp:1052
configRegisterStruct_i32s_i32s_o32s
const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i32s_i32s_o32s
Definition: c7100/FFTLIB_configurations.cpp:40
offsetRegStruct_diagonal_8bit
const __HWA_OFFSET_REG offsetRegStruct_diagonal_8bit
Definition: c7100/FFTLIB_configurations.cpp:1136
ASSIGN
#define ASSIGN(param, value)
Definition: c7100/FFTLIB_configurations.cpp:882
configRegisterStruct_i8u_i8s_o8u
const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i8u_i8s_o8u
Definition: c7100/FFTLIB_configurations.cpp:785
configRegisterStruct_i8s_i8s_o8s
const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i8s_i8s_o8s
Definition: c7100/FFTLIB_configurations.cpp:510
configRegisterStruct_i16u_i16s_o16s
const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i16u_i16s_o16s
Definition: c7100/FFTLIB_configurations.cpp:324
configRegisterStruct_i8u_i8s_o8s
const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i8u_i8s_o8s
Definition: c7100/FFTLIB_configurations.cpp:694
configRegisterStruct_i16u_i16s_o16u
const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i16u_i16s_o16u
Definition: c7100/FFTLIB_configurations.cpp:415
configRegisterStruct_i8s_i8s_o8u
const FFTLIB_MMA_CONFIG_REG configRegisterStruct_i8s_i8s_o8u
Definition: c7100/FFTLIB_configurations.cpp:602
offsetRegStruct_diagonal_32bit
const __HWA_OFFSET_REG offsetRegStruct_diagonal_32bit
Definition: c7100/FFTLIB_configurations.cpp:968
FFTLIB_MMA_CONFIG_REG
#define FFTLIB_MMA_CONFIG_REG
Definition: c7100/FFTLIB_defines.h:61
FFTLIB_MMA_SIZE_16_BIT
#define FFTLIB_MMA_SIZE_16_BIT
type is 16-bit integers
Definition: c7100/FFTLIB_types.h:100
FFTLIB_MMA_SIZE_8_BIT
#define FFTLIB_MMA_SIZE_8_BIT
MMA size as a function of precision.
Definition: c7100/FFTLIB_types.h:96
FFTLIB_MMA_SIZE_32_BIT
#define FFTLIB_MMA_SIZE_32_BIT
type is 32-bit integers
Definition: c7100/FFTLIB_types.h:104