Introduction

This section contains APIs for display controller remote service.

Data Structures
struct	app_dctrl_edge_info_t
	Structure containing edge information. Edge is a connection between two nodes i.e. two modules. DSS Hardware can be represented by a graph, where each module is node and edge is present between two nodes if they are connected. More...

struct	app_dctrl_path_info_t
	Structure containing DSS path information. More...

struct	app_dctrl_vp_params_t
	Structure containing Video Port information. More...

struct	app_dctrl_adv_vp_params_t
	Advance Signal Configuration for the LCD. More...

struct	app_dctrl_overlay_params_t
	Structure containing Overlay information. More...

struct	app_dctrl_layer_params_t
	Structure containing Overlay layer information. More...

struct	app_dctrl_dsi_params_t
	Structure for dsi parameters. More...

struct	app_dss_default_timings_prm_t
	Timing Parameters for display. More...

struct	app_dss_default_prm_t
	Parameters to use to init display. More...

struct	app_dss_dual_display_default_prm_t
	Parameters to use to init display in dual display mode. More...

Functions
static void	appDctrlPathInfoInit (app_dctrl_path_info_t *pathInfo)
	app_dctrl_path_info_t structure init function. More...

static void	appDctrlVpParamsInit (app_dctrl_vp_params_t *vpParams)
	app_dctrl_vp_params_t structure init function. More...

static void	appDctrlAdvVpParamsInit (app_dctrl_adv_vp_params_t *advVpParams)
	app_dctrl_adv_vp_params_t structure init function. More...

static void	appDctrlOverlayParamsInit (app_dctrl_overlay_params_t *overlayParams)
	app_dctrl_overlay_params_t structure init function. More...

static void	appDctrlLayerParamsInit (app_dctrl_layer_params_t *layerParams)
	app_dctrl_layer_params_t structure init function. More...

static void	appDctrlDsiParamsInit (app_dctrl_dsi_params_t *prms)
	app_dctrl_dsi_params_t structure init function. More...

int32_t	appDctrlInit (void)
	DCTRL initialization function. More...

int32_t	appDctrlDeInit (void)
	DCTRL de-initialization function. More...

void	appDssDefaultSetDefaultPrm (app_dss_default_prm_t *prm)
	Set default parameters to use for appDssDefaultInit() More...

int32_t	appDssDefaultInit (app_dss_default_prm_t *prm)
	DSS initialization wrapper function. More...

int32_t	appDssDefaultDeInit (void)
	DSS de-initialization wrapper function. More...

void	appDssDualDisplayDefaultSetDefaultPrm (app_dss_dual_display_default_prm_t *prm)
	Set default parameters to use for appDssDualDisplayDefaultInit() More...

int32_t	appDssDualDisplayDefaultInit (app_dss_dual_display_default_prm_t *prm)
	DSS initialization wrapper function for dual display mode. More...

int32_t	appDssDualDisplayDefaultDeInit (void)
	DSS de-initialization wrapper function for dual display mode. More...

Macros
#define	APP_DCTRL_REMOTE_SERVICE_NAME "com.ti.dctrl"
	Remote service for Display Controller. More...

#define	APP_DCTRL_MAX_EDGES (29U)
	Defines maximum number of edges for allocation. This is derived by looking at all possible DSS connections in the SoC. More...

#define	APP_DSS_DEFAULT_DISPLAY_TYPE_EDP (0u)
	On-chip eDP/DP display. More...

#define	APP_DSS_DEFAULT_DISPLAY_TYPE_DPI_HDMI (1u)
	Off-chip HDMI display using DPI output from SoC. More...

#define	APP_DSS_DEFAULT_DISPLAY_TYPE_DSI (2u)
	Enables DSI output on AOU LCD Display. More...

DCTRL Node Id
Node ids that are used by the set path to connect different modules and create a graph
#define	APP_DCTRL_NODE_INVALID (0x0U)

#define	APP_DCTRL_NODE_VID1 (0x1U)

#define	APP_DCTRL_NODE_VIDL1 (0x2U)

#define	APP_DCTRL_NODE_VID2 (0x3U)

#define	APP_DCTRL_NODE_VIDL2 (0x4U)

#define	APP_DCTRL_NODE_OVERLAY1 (0x5U)

#define	APP_DCTRL_NODE_OVERLAY2 (0x6U)

#define	APP_DCTRL_NODE_OVERLAY3 (0x7U)

#define	APP_DCTRL_NODE_OVERLAY4 (0x8U)

#define	APP_DCTRL_NODE_VP1 (0x9U)

#define	APP_DCTRL_NODE_VP2 (0xAU)

#define	APP_DCTRL_NODE_VP3 (0xBU)

#define	APP_DCTRL_NODE_VP4 (0xCU)

#define	APP_DCTRL_NODE_DPI_DPI0 (0xDU)

#define	APP_DCTRL_NODE_DPI_DPI1 (0xEU)

#define	APP_DCTRL_NODE_EDP_DPI0 (0xFU)

#define	APP_DCTRL_NODE_EDP_DPI1 (0x10U)

#define	APP_DCTRL_NODE_EDP_DPI2 (0x11U)

#define	APP_DCTRL_NODE_EDP_DPI3 (0x12U)

#define	APP_DCTRL_NODE_DSI_DPI2 (0x13U)

Video standards

#define	APP_DCTRL_VID_STD_NTSC ((uint32_t) 0x00U)
	720x480 30FPS interlaced NTSC standard. More...

#define	APP_DCTRL_VID_STD_PAL ((uint32_t) 0x01U)
	720x576 30FPS interlaced PAL standard. More...

#define	APP_DCTRL_VID_STD_480I ((uint32_t) 0x02U)
	720x480 30FPS interlaced SD standard. More...

#define	APP_DCTRL_VID_STD_576I ((uint32_t) 0x03U)
	720x576 30FPS interlaced SD standard. More...

#define	APP_DCTRL_VID_STD_CIF ((uint32_t) 0x04U)
	Interlaced, 360x120 per field NTSC, 360x144 per field PAL. More...

#define	APP_DCTRL_VID_STD_HALF_D1 ((uint32_t) 0x05U)
	Interlaced, 360x240 per field NTSC, 360x288 per field PAL. More...

#define	APP_DCTRL_VID_STD_D1 ((uint32_t) 0x06U)
	Interlaced, 720x240 per field NTSC, 720x288 per field PAL. More...

#define	APP_DCTRL_VID_STD_480P ((uint32_t) 0x07U)
	720x480 60FPS progressive ED standard. More...

#define	APP_DCTRL_VID_STD_576P ((uint32_t) 0x08U)
	720x576 60FPS progressive ED standard. More...

#define	APP_DCTRL_VID_STD_720P_60 ((uint32_t) 0x09U)
	1280x720 60FPS progressive HD standard. More...

#define	APP_DCTRL_VID_STD_720P_50 ((uint32_t) 0x0AU)
	1280x720 50FPS progressive HD standard. More...

#define	APP_DCTRL_VID_STD_1080I_60 ((uint32_t) 0x0BU)
	1920x1080 30FPS interlaced HD standard. More...

#define	APP_DCTRL_VID_STD_1080I_50 ((uint32_t) 0x0CU)
	1920x1080 50FPS interlaced HD standard. More...

#define	APP_DCTRL_VID_STD_1080P_60 ((uint32_t) 0x0DU)
	1920x1080 60FPS progressive HD standard. More...

#define	APP_DCTRL_VID_STD_1080P_50 ((uint32_t) 0x0EU)
	1920x1080 50FPS progressive HD standard. More...

#define	APP_DCTRL_VID_STD_1080P_24 ((uint32_t) 0x0FU)
	1920x1080 24FPS progressive HD standard. More...

#define	APP_DCTRL_VID_STD_1080P_30 ((uint32_t) 0x10U)
	1920x1080 30FPS progressive HD standard. More...

#define	APP_DCTRL_VID_STD_VGA_60 ((uint32_t) 0x11U)
	640x480 60FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_VGA_72 ((uint32_t) 0x12U)
	640x480 72FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_VGA_75 ((uint32_t) 0x13U)
	640x480 75FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_VGA_85 ((uint32_t) 0x14U)
	640x480 85FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_WVGA_60 ((uint32_t) 0x15U)
	800x480 60PFS WVGA More...

#define	APP_DCTRL_VID_STD_SVGA_60 ((uint32_t) 0x16U)
	800x600 60FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_SVGA_72 ((uint32_t) 0x17U)
	800x600 72FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_SVGA_75 ((uint32_t) 0x18U)
	800x600 75FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_SVGA_85 ((uint32_t) 0x19U)
	800x600 85FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_WSVGA_70 ((uint32_t) 0x1AU)
	1024x600 70FPS standard. More...

#define	APP_DCTRL_VID_STD_XGA_60 ((uint32_t) 0x1BU)
	1024x768 60FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_XGA_DSS_TDM_60 ((uint32_t) 0x1CU)
	1024x768 60FPS VESA standard. Applicable for DSS in 8-bit TDM mode. More...

#define	APP_DCTRL_VID_STD_XGA_70 ((uint32_t) 0x1DU)
	1024x768 72FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_XGA_75 ((uint32_t) 0x1EU)
	1024x768 75FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_XGA_85 ((uint32_t) 0x1FU)
	1024x768 85FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_1368_768_60 ((uint32_t) 0x20U)
	1368x768 60 PFS VESA. More...

#define	APP_DCTRL_VID_STD_1366_768_60 ((uint32_t) 0x21U)
	1366x768 60 PFS VESA. More...

#define	APP_DCTRL_VID_STD_1360_768_60 ((uint32_t) 0x22U)
	1360x768 60 PFS VESA. More...

#define	APP_DCTRL_VID_STD_WXGA_30 ((uint32_t) 0x23U)
	1280x800 30FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_WXGA_60 ((uint32_t) 0x24U)
	1280x800 60FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_WXGA_75 ((uint32_t) 0x25U)
	1280x800 75FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_WXGA_85 ((uint32_t) 0x26U)
	1280x800 85FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_1440_900_60 ((uint32_t) 0x27U)
	1440x900 60 PFS VESA standard. More...

#define	APP_DCTRL_VID_STD_SXGA_60 ((uint32_t) 0x28U)
	1280x1024 60FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_SXGA_75 ((uint32_t) 0x29U)
	1280x1024 75FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_SXGA_85 ((uint32_t) 0x2AU)
	1280x1024 85FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_WSXGAP_60 ((uint32_t) 0x2BU)
	1680x1050 60 PFS VESA standard. More...

#define	APP_DCTRL_VID_STD_SXGAP_60 ((uint32_t) 0x2CU)
	1400x1050 60FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_SXGAP_75 ((uint32_t) 0x2DU)
	1400x1050 75FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_UXGA_60 ((uint32_t) 0x2EU)
	1600x1200 60FPS VESA standard. More...

#define	APP_DCTRL_VID_STD_MUX_2CH_D1 ((uint32_t) 0x2FU)
	Interlaced, 2Ch D1, NTSC or PAL. More...

#define	APP_DCTRL_VID_STD_MUX_2CH_HALF_D1 ((uint32_t) 0x30U)
	Interlaced, 2ch half D1, NTSC or PAL. More...

#define	APP_DCTRL_VID_STD_MUX_2CH_CIF ((uint32_t) 0x31U)
	Interlaced, 2ch CIF, NTSC or PAL. More...

#define	APP_DCTRL_VID_STD_MUX_4CH_D1 ((uint32_t) 0x32U)
	Interlaced, 4Ch D1, NTSC or PAL. More...

#define	APP_DCTRL_VID_STD_MUX_4CH_CIF ((uint32_t) 0x33U)
	Interlaced, 4Ch CIF, NTSC or PAL. More...

#define	APP_DCTRL_VID_STD_MUX_4CH_HALF_D1 ((uint32_t) 0x34U)
	Interlaced, 4Ch Half-D1, NTSC or PAL. More...

#define	APP_DCTRL_VID_STD_MUX_8CH_CIF ((uint32_t) 0x35U)
	Interlaced, 8Ch CIF, NTSC or PAL. More...

#define	APP_DCTRL_VID_STD_MUX_8CH_HALF_D1 ((uint32_t) 0x36U)
	Interlaced, 8Ch Half-D1, NTSC or PAL. More...

#define	APP_DCTRL_VID_STD_WXGA_5x3_30 ((uint32_t) 0x37U)
	WXGA standard (1280x768) with the aspect ratio 5:3 at 30FPS. More...

#define	APP_DCTRL_VID_STD_WXGA_5x3_60 ((uint32_t) 0x38U)
	WXGA resolution (1280x768) with the aspect ratio 5:3 at 60FPS. More...

#define	APP_DCTRL_VID_STD_WXGA_5x3_75 ((uint32_t) 0x39U)
	WXGA resolution (1280x768) with the aspect ratio 5:3 at 75FPS. More...

#define	APP_DCTRL_VID_STD_AUTO_DETECT ((uint32_t) 0x3AU)
	Auto-detect standard. Used in capture mode. More...

#define	APP_DCTRL_VID_STD_CUSTOM ((uint32_t) 0x3BU)
	Custom standard used when connecting to external LCD etc... The video timing is provided by the application. More...

Digital Video Format

#define	APP_DCTRL_DV_BT656_EMBSYNC ((uint32_t) 0x00U)
	Video format is BT656 with embedded sync. More...

#define	APP_DCTRL_DV_BT1120_EMBSYNC ((uint32_t) 0x01U)
	Video format is BT1120 with embedded sync. More...

#define	APP_DCTRL_DV_GENERIC_DISCSYNC ((uint32_t) 0x02U)
	Video format is for any discrete sync. More...

Digital video interface width

#define	APP_DCTRL_VIFW_8BIT ((uint32_t) 0x00U)
	8-bit interface. More...

#define	APP_DCTRL_VIFW_10BIT ((uint32_t) 0x01U)
	10-bit interface. More...

#define	APP_DCTRL_VIFW_12BIT ((uint32_t) 0x02U)
	12-bit interface. More...

#define	APP_DCTRL_VIFW_14BIT ((uint32_t) 0x03U)
	14-bit interface. More...

#define	APP_DCTRL_VIFW_16BIT ((uint32_t) 0x04U)
	16-bit interface. More...

#define	APP_DCTRL_VIFW_18BIT ((uint32_t) 0x05U)
	18-bit interface. More...

#define	APP_DCTRL_VIFW_20BIT ((uint32_t) 0x06U)
	20-bit interface. More...

#define	APP_DCTRL_VIFW_24BIT ((uint32_t) 0x07U)
	24-bit interface. More...

#define	APP_DCTRL_VIFW_30BIT ((uint32_t) 0x08U)
	30-bit interface. More...

#define	APP_DCTRL_VIFW_36BIT ((uint32_t) 0x09U)
	36-bit interface. More...

#define	APP_DCTRL_VIFW_1LANES ((uint32_t) 0x0AU)
	CSI2 specific - 1 data lanes. More...

#define	APP_DCTRL_VIFW_2LANES ((uint32_t) 0x0BU)
	CSI2 specific - 2 data lanes. More...

#define	APP_DCTRL_VIFW_3LANES ((uint32_t) 0x0CU)
	CSI2 specific - 3 data lanes. More...

#define	APP_DCTRL_VIFW_4LANES ((uint32_t) 0x0DU)
	CSI2 / LVDS specific - 4 data lanes. More...

#define	APP_DCTRL_VIFW_MAX ((uint32_t) 0x0EU)
	Maximum modes. More...

Polarity type

#define	APP_DCTRL_POL_LOW ((uint32_t) 0U)
	Low Polarity. More...

#define	APP_DCTRL_POL_HIGH ((uint32_t) 1U)
	High Polarity. More...

#define	APP_DCTRL_POL_MAX ((uint32_t) 2U)
	Used by driver for validating the input parameters. More...

Edge Polarity type

#define	APP_DCTRL_EDGE_POL_RISING ((uint32_t) 0U)
	Rising Edge. More...

#define	APP_DCTRL_EDGE_POL_FALLING ((uint32_t) 1U)
	Falling Edge. More...

#define	APP_DCTRL_EDGE_POL_MAX ((uint32_t) 2U)
	Used by driver for validating the input parameters. More...

HS/VS alignment types

#define	APP_DCTRL_HVSYNC_ALIGN_OFF ((uint32_t) 0U)
	HS/VS not aligned. More...

#define	APP_DCTRL_HVSYNC_ALIGN_ON ((uint32_t) 1U)
	HS/VS aligned. More...

#define	APP_DCTRL_HVSYNC_ALIGN_MAX ((uint32_t) 2U)
	Used by driver for validating the input parameters. More...

HS/VS pixel clock control types

#define	APP_DCTRL_HVCLK_CTRL_OFF ((uint32_t) 0U)
	HSYNC and VSYNC are driven on opposite edges of the pixel clock than pixel data. More...

#define	APP_DCTRL_HVCLK_CTRL_ON ((uint32_t) 1U)
	HSYNC and VSYNC are driven according to hVClkRiseFall value. More...

#define	APP_DCTRL_HVCLK_CTRL_MAX ((uint32_t) 2U)
	Used by driver for validating the input parameters. More...

Overlay Transparency Color Key Selection

#define	APP_DCTRL_OVERLAY_TRANS_COLOR_DEST ((uint32_t) 0U)
	Destination transparency color key selected. More...

#define	APP_DCTRL_OVERLAY_TRANS_COLOR_SRC ((uint32_t) 1U)
	Source transparency color key selected. More...

Overlay Layer Number

#define	APP_DCTRL_OVERLAY_LAYER_NUM_0 ((uint32_t) 0x0U)
	Overlay Layer 0. More...

#define	APP_DCTRL_OVERLAY_LAYER_NUM_1 ((uint32_t) 0x1U)
	Overlay Layer 1. More...

#define	APP_DCTRL_OVERLAY_LAYER_NUM_2 ((uint32_t) 0x2U)
	Overlay Layer 2. More...

#define	APP_DCTRL_OVERLAY_LAYER_NUM_3 ((uint32_t) 0x3U)
	Overlay Layer 3. More...

#define	APP_DCTRL_OVERLAY_LAYER_NUM_4 ((uint32_t) 0x4U)
	Overlay Layer 3. More...

#define	APP_DCTRL_OVERLAY_LAYER_MAX ((uint32_t) 0x5U)
	Maximum overlay layers. More...

#define	APP_DCTRL_OVERLAY_LAYER_INVALID ((uint32_t) 0xFFU)
	Invalid Overlay Layer. More...

Display contorller CMD IDs to pass to appRemoteServiceRun()

#define	APP_DCTRL_CMD_BASE ((uint32_t) 0x0U)
	Base address for the display controller commands. More...

#define	APP_DCTRL_CMD_REGISTER_HANDLE (APP_DCTRL_CMD_BASE + 0x1U)
	Command to register the FVID2 Handle for display controller. More...

#define	APP_DCTRL_CMD_DELETE_HANDLE (APP_DCTRL_CMD_BASE + 0x2U)
	Command to unregister the FVID2 Handle for display controller. More...

#define	APP_DCTRL_CMD_SET_PATH (APP_DCTRL_CMD_BASE + 0x3U)
	Command to set the DSS display path configuration. More...

#define	APP_DCTRL_CMD_CLEAR_PATH (APP_DCTRL_CMD_BASE + 0x4U)
	Command to clear the DSS display path configuration. More...

#define	APP_DCTRL_CMD_SET_VP_PARAMS (APP_DCTRL_CMD_BASE + 0x5U)
	Command to set Video Port configuration. More...

#define	APP_DCTRL_CMD_SET_OVERLAY_PARAMS (APP_DCTRL_CMD_BASE + 0x6U)
	Command to set configuration of the given overlay. More...

#define	APP_DCTRL_CMD_SET_LAYER_PARAMS (APP_DCTRL_CMD_BASE + 0x7U)
	Command to set layer/Z-order configuration of the given overlay. More...

#define	APP_DCTRL_CMD_STOP_VP (APP_DCTRL_CMD_BASE + 0x8U)
	Command to disable Video Port. More...

#define	APP_DCTRL_CMD_SET_ADV_VP_PARAMS (APP_DCTRL_CMD_BASE + 0x9U)
	Command to to set advance Video Port configuration. More...

#define	APP_DCTRL_CMD_SET_DSI_PARAMS (APP_DCTRL_CMD_BASE + 0xAU)
	Command to to set DSI parameters/configuration. More...

#define	APP_DCTRL_CMD_IS_DP_CONNECTED (APP_DCTRL_CMD_BASE + 0xBU)
	Command to query whether DP is connected. More...

Macro Definition Documentation

◆ APP_DCTRL_REMOTE_SERVICE_NAME

#define APP_DCTRL_REMOTE_SERVICE_NAME "com.ti.dctrl"

Remote service for Display Controller.

◆ APP_DCTRL_NODE_INVALID

#define APP_DCTRL_NODE_INVALID (0x0U)

◆ APP_DCTRL_NODE_VID1

#define APP_DCTRL_NODE_VID1 (0x1U)

◆ APP_DCTRL_NODE_VIDL1

#define APP_DCTRL_NODE_VIDL1 (0x2U)

◆ APP_DCTRL_NODE_VID2

#define APP_DCTRL_NODE_VID2 (0x3U)

◆ APP_DCTRL_NODE_VIDL2

#define APP_DCTRL_NODE_VIDL2 (0x4U)

◆ APP_DCTRL_NODE_OVERLAY1

#define APP_DCTRL_NODE_OVERLAY1 (0x5U)

◆ APP_DCTRL_NODE_OVERLAY2

#define APP_DCTRL_NODE_OVERLAY2 (0x6U)

◆ APP_DCTRL_NODE_OVERLAY3

#define APP_DCTRL_NODE_OVERLAY3 (0x7U)

◆ APP_DCTRL_NODE_OVERLAY4

#define APP_DCTRL_NODE_OVERLAY4 (0x8U)

◆ APP_DCTRL_NODE_VP1

#define APP_DCTRL_NODE_VP1 (0x9U)

◆ APP_DCTRL_NODE_VP2

#define APP_DCTRL_NODE_VP2 (0xAU)

◆ APP_DCTRL_NODE_VP3

#define APP_DCTRL_NODE_VP3 (0xBU)

◆ APP_DCTRL_NODE_VP4

#define APP_DCTRL_NODE_VP4 (0xCU)

◆ APP_DCTRL_NODE_DPI_DPI0

#define APP_DCTRL_NODE_DPI_DPI0 (0xDU)

◆ APP_DCTRL_NODE_DPI_DPI1

#define APP_DCTRL_NODE_DPI_DPI1 (0xEU)

◆ APP_DCTRL_NODE_EDP_DPI0

#define APP_DCTRL_NODE_EDP_DPI0 (0xFU)

◆ APP_DCTRL_NODE_EDP_DPI1

#define APP_DCTRL_NODE_EDP_DPI1 (0x10U)

◆ APP_DCTRL_NODE_EDP_DPI2

#define APP_DCTRL_NODE_EDP_DPI2 (0x11U)

◆ APP_DCTRL_NODE_EDP_DPI3

#define APP_DCTRL_NODE_EDP_DPI3 (0x12U)

◆ APP_DCTRL_NODE_DSI_DPI2

#define APP_DCTRL_NODE_DSI_DPI2 (0x13U)

◆ APP_DCTRL_MAX_EDGES

#define APP_DCTRL_MAX_EDGES (29U)

Defines maximum number of edges for allocation. This is derived by looking at all possible DSS connections in the SoC.

◆ APP_DCTRL_VID_STD_NTSC

#define APP_DCTRL_VID_STD_NTSC ((uint32_t) 0x00U)

720x480 30FPS interlaced NTSC standard.

◆ APP_DCTRL_VID_STD_PAL

#define APP_DCTRL_VID_STD_PAL ((uint32_t) 0x01U)

720x576 30FPS interlaced PAL standard.

◆ APP_DCTRL_VID_STD_480I

#define APP_DCTRL_VID_STD_480I ((uint32_t) 0x02U)

720x480 30FPS interlaced SD standard.

◆ APP_DCTRL_VID_STD_576I

#define APP_DCTRL_VID_STD_576I ((uint32_t) 0x03U)

720x576 30FPS interlaced SD standard.

◆ APP_DCTRL_VID_STD_CIF

#define APP_DCTRL_VID_STD_CIF ((uint32_t) 0x04U)

Interlaced, 360x120 per field NTSC, 360x144 per field PAL.

◆ APP_DCTRL_VID_STD_HALF_D1

#define APP_DCTRL_VID_STD_HALF_D1 ((uint32_t) 0x05U)

Interlaced, 360x240 per field NTSC, 360x288 per field PAL.

◆ APP_DCTRL_VID_STD_D1

#define APP_DCTRL_VID_STD_D1 ((uint32_t) 0x06U)

Interlaced, 720x240 per field NTSC, 720x288 per field PAL.

◆ APP_DCTRL_VID_STD_480P

#define APP_DCTRL_VID_STD_480P ((uint32_t) 0x07U)

720x480 60FPS progressive ED standard.

◆ APP_DCTRL_VID_STD_576P

#define APP_DCTRL_VID_STD_576P ((uint32_t) 0x08U)

720x576 60FPS progressive ED standard.

◆ APP_DCTRL_VID_STD_720P_60

#define APP_DCTRL_VID_STD_720P_60 ((uint32_t) 0x09U)

1280x720 60FPS progressive HD standard.

◆ APP_DCTRL_VID_STD_720P_50

#define APP_DCTRL_VID_STD_720P_50 ((uint32_t) 0x0AU)

1280x720 50FPS progressive HD standard.

◆ APP_DCTRL_VID_STD_1080I_60

#define APP_DCTRL_VID_STD_1080I_60 ((uint32_t) 0x0BU)

1920x1080 30FPS interlaced HD standard.

◆ APP_DCTRL_VID_STD_1080I_50

#define APP_DCTRL_VID_STD_1080I_50 ((uint32_t) 0x0CU)

1920x1080 50FPS interlaced HD standard.

◆ APP_DCTRL_VID_STD_1080P_60

#define APP_DCTRL_VID_STD_1080P_60 ((uint32_t) 0x0DU)

1920x1080 60FPS progressive HD standard.

◆ APP_DCTRL_VID_STD_1080P_50

#define APP_DCTRL_VID_STD_1080P_50 ((uint32_t) 0x0EU)

1920x1080 50FPS progressive HD standard.

◆ APP_DCTRL_VID_STD_1080P_24

#define APP_DCTRL_VID_STD_1080P_24 ((uint32_t) 0x0FU)

1920x1080 24FPS progressive HD standard.

◆ APP_DCTRL_VID_STD_1080P_30

#define APP_DCTRL_VID_STD_1080P_30 ((uint32_t) 0x10U)

1920x1080 30FPS progressive HD standard.

◆ APP_DCTRL_VID_STD_VGA_60

#define APP_DCTRL_VID_STD_VGA_60 ((uint32_t) 0x11U)

640x480 60FPS VESA standard.

◆ APP_DCTRL_VID_STD_VGA_72

#define APP_DCTRL_VID_STD_VGA_72 ((uint32_t) 0x12U)

640x480 72FPS VESA standard.

◆ APP_DCTRL_VID_STD_VGA_75

#define APP_DCTRL_VID_STD_VGA_75 ((uint32_t) 0x13U)

640x480 75FPS VESA standard.

◆ APP_DCTRL_VID_STD_VGA_85

#define APP_DCTRL_VID_STD_VGA_85 ((uint32_t) 0x14U)

640x480 85FPS VESA standard.

◆ APP_DCTRL_VID_STD_WVGA_60

#define APP_DCTRL_VID_STD_WVGA_60 ((uint32_t) 0x15U)

800x480 60PFS WVGA

◆ APP_DCTRL_VID_STD_SVGA_60

#define APP_DCTRL_VID_STD_SVGA_60 ((uint32_t) 0x16U)

800x600 60FPS VESA standard.

◆ APP_DCTRL_VID_STD_SVGA_72

#define APP_DCTRL_VID_STD_SVGA_72 ((uint32_t) 0x17U)

800x600 72FPS VESA standard.

◆ APP_DCTRL_VID_STD_SVGA_75

#define APP_DCTRL_VID_STD_SVGA_75 ((uint32_t) 0x18U)

800x600 75FPS VESA standard.

◆ APP_DCTRL_VID_STD_SVGA_85

#define APP_DCTRL_VID_STD_SVGA_85 ((uint32_t) 0x19U)

800x600 85FPS VESA standard.

◆ APP_DCTRL_VID_STD_WSVGA_70

#define APP_DCTRL_VID_STD_WSVGA_70 ((uint32_t) 0x1AU)

1024x600 70FPS standard.

◆ APP_DCTRL_VID_STD_XGA_60

#define APP_DCTRL_VID_STD_XGA_60 ((uint32_t) 0x1BU)

1024x768 60FPS VESA standard.

◆ APP_DCTRL_VID_STD_XGA_DSS_TDM_60

#define APP_DCTRL_VID_STD_XGA_DSS_TDM_60 ((uint32_t) 0x1CU)

1024x768 60FPS VESA standard. Applicable for DSS in 8-bit TDM mode.

◆ APP_DCTRL_VID_STD_XGA_70

#define APP_DCTRL_VID_STD_XGA_70 ((uint32_t) 0x1DU)

1024x768 72FPS VESA standard.

◆ APP_DCTRL_VID_STD_XGA_75

#define APP_DCTRL_VID_STD_XGA_75 ((uint32_t) 0x1EU)

1024x768 75FPS VESA standard.

◆ APP_DCTRL_VID_STD_XGA_85

#define APP_DCTRL_VID_STD_XGA_85 ((uint32_t) 0x1FU)

1024x768 85FPS VESA standard.

◆ APP_DCTRL_VID_STD_1368_768_60

#define APP_DCTRL_VID_STD_1368_768_60 ((uint32_t) 0x20U)

1368x768 60 PFS VESA.

◆ APP_DCTRL_VID_STD_1366_768_60

#define APP_DCTRL_VID_STD_1366_768_60 ((uint32_t) 0x21U)

1366x768 60 PFS VESA.

◆ APP_DCTRL_VID_STD_1360_768_60

#define APP_DCTRL_VID_STD_1360_768_60 ((uint32_t) 0x22U)

1360x768 60 PFS VESA.

◆ APP_DCTRL_VID_STD_WXGA_30

#define APP_DCTRL_VID_STD_WXGA_30 ((uint32_t) 0x23U)

1280x800 30FPS VESA standard.

◆ APP_DCTRL_VID_STD_WXGA_60

#define APP_DCTRL_VID_STD_WXGA_60 ((uint32_t) 0x24U)

1280x800 60FPS VESA standard.

◆ APP_DCTRL_VID_STD_WXGA_75

#define APP_DCTRL_VID_STD_WXGA_75 ((uint32_t) 0x25U)

1280x800 75FPS VESA standard.

◆ APP_DCTRL_VID_STD_WXGA_85

#define APP_DCTRL_VID_STD_WXGA_85 ((uint32_t) 0x26U)

1280x800 85FPS VESA standard.

◆ APP_DCTRL_VID_STD_1440_900_60

#define APP_DCTRL_VID_STD_1440_900_60 ((uint32_t) 0x27U)

1440x900 60 PFS VESA standard.

◆ APP_DCTRL_VID_STD_SXGA_60

#define APP_DCTRL_VID_STD_SXGA_60 ((uint32_t) 0x28U)

1280x1024 60FPS VESA standard.

◆ APP_DCTRL_VID_STD_SXGA_75

#define APP_DCTRL_VID_STD_SXGA_75 ((uint32_t) 0x29U)

1280x1024 75FPS VESA standard.

◆ APP_DCTRL_VID_STD_SXGA_85

#define APP_DCTRL_VID_STD_SXGA_85 ((uint32_t) 0x2AU)

1280x1024 85FPS VESA standard.

◆ APP_DCTRL_VID_STD_WSXGAP_60

#define APP_DCTRL_VID_STD_WSXGAP_60 ((uint32_t) 0x2BU)

1680x1050 60 PFS VESA standard.

◆ APP_DCTRL_VID_STD_SXGAP_60

#define APP_DCTRL_VID_STD_SXGAP_60 ((uint32_t) 0x2CU)

1400x1050 60FPS VESA standard.

◆ APP_DCTRL_VID_STD_SXGAP_75

#define APP_DCTRL_VID_STD_SXGAP_75 ((uint32_t) 0x2DU)

1400x1050 75FPS VESA standard.

◆ APP_DCTRL_VID_STD_UXGA_60

#define APP_DCTRL_VID_STD_UXGA_60 ((uint32_t) 0x2EU)

1600x1200 60FPS VESA standard.

◆ APP_DCTRL_VID_STD_MUX_2CH_D1

#define APP_DCTRL_VID_STD_MUX_2CH_D1 ((uint32_t) 0x2FU)

Interlaced, 2Ch D1, NTSC or PAL.

◆ APP_DCTRL_VID_STD_MUX_2CH_HALF_D1

#define APP_DCTRL_VID_STD_MUX_2CH_HALF_D1 ((uint32_t) 0x30U)

Interlaced, 2ch half D1, NTSC or PAL.

◆ APP_DCTRL_VID_STD_MUX_2CH_CIF

#define APP_DCTRL_VID_STD_MUX_2CH_CIF ((uint32_t) 0x31U)

Interlaced, 2ch CIF, NTSC or PAL.

◆ APP_DCTRL_VID_STD_MUX_4CH_D1

#define APP_DCTRL_VID_STD_MUX_4CH_D1 ((uint32_t) 0x32U)

Interlaced, 4Ch D1, NTSC or PAL.

◆ APP_DCTRL_VID_STD_MUX_4CH_CIF

#define APP_DCTRL_VID_STD_MUX_4CH_CIF ((uint32_t) 0x33U)

Interlaced, 4Ch CIF, NTSC or PAL.

◆ APP_DCTRL_VID_STD_MUX_4CH_HALF_D1

#define APP_DCTRL_VID_STD_MUX_4CH_HALF_D1 ((uint32_t) 0x34U)

Interlaced, 4Ch Half-D1, NTSC or PAL.

◆ APP_DCTRL_VID_STD_MUX_8CH_CIF

#define APP_DCTRL_VID_STD_MUX_8CH_CIF ((uint32_t) 0x35U)

Interlaced, 8Ch CIF, NTSC or PAL.

◆ APP_DCTRL_VID_STD_MUX_8CH_HALF_D1

#define APP_DCTRL_VID_STD_MUX_8CH_HALF_D1 ((uint32_t) 0x36U)

Interlaced, 8Ch Half-D1, NTSC or PAL.

◆ APP_DCTRL_VID_STD_WXGA_5x3_30

#define APP_DCTRL_VID_STD_WXGA_5x3_30 ((uint32_t) 0x37U)

WXGA standard (1280x768) with the aspect ratio 5:3 at 30FPS.

◆ APP_DCTRL_VID_STD_WXGA_5x3_60

#define APP_DCTRL_VID_STD_WXGA_5x3_60 ((uint32_t) 0x38U)

WXGA resolution (1280x768) with the aspect ratio 5:3 at 60FPS.

◆ APP_DCTRL_VID_STD_WXGA_5x3_75

#define APP_DCTRL_VID_STD_WXGA_5x3_75 ((uint32_t) 0x39U)

WXGA resolution (1280x768) with the aspect ratio 5:3 at 75FPS.

◆ APP_DCTRL_VID_STD_AUTO_DETECT

#define APP_DCTRL_VID_STD_AUTO_DETECT ((uint32_t) 0x3AU)

Auto-detect standard. Used in capture mode.

◆ APP_DCTRL_VID_STD_CUSTOM

#define APP_DCTRL_VID_STD_CUSTOM ((uint32_t) 0x3BU)

Custom standard used when connecting to external LCD etc... The video timing is provided by the application.

◆ APP_DCTRL_DV_BT656_EMBSYNC

#define APP_DCTRL_DV_BT656_EMBSYNC ((uint32_t) 0x00U)

Video format is BT656 with embedded sync.

◆ APP_DCTRL_DV_BT1120_EMBSYNC

#define APP_DCTRL_DV_BT1120_EMBSYNC ((uint32_t) 0x01U)

Video format is BT1120 with embedded sync.

◆ APP_DCTRL_DV_GENERIC_DISCSYNC

#define APP_DCTRL_DV_GENERIC_DISCSYNC ((uint32_t) 0x02U)

Video format is for any discrete sync.

◆ APP_DCTRL_VIFW_8BIT

#define APP_DCTRL_VIFW_8BIT ((uint32_t) 0x00U)

8-bit interface.

◆ APP_DCTRL_VIFW_10BIT

#define APP_DCTRL_VIFW_10BIT ((uint32_t) 0x01U)

10-bit interface.

◆ APP_DCTRL_VIFW_12BIT

#define APP_DCTRL_VIFW_12BIT ((uint32_t) 0x02U)

12-bit interface.

◆ APP_DCTRL_VIFW_14BIT

#define APP_DCTRL_VIFW_14BIT ((uint32_t) 0x03U)

14-bit interface.

◆ APP_DCTRL_VIFW_16BIT

#define APP_DCTRL_VIFW_16BIT ((uint32_t) 0x04U)

16-bit interface.

◆ APP_DCTRL_VIFW_18BIT

#define APP_DCTRL_VIFW_18BIT ((uint32_t) 0x05U)

18-bit interface.

◆ APP_DCTRL_VIFW_20BIT

#define APP_DCTRL_VIFW_20BIT ((uint32_t) 0x06U)

20-bit interface.

◆ APP_DCTRL_VIFW_24BIT

#define APP_DCTRL_VIFW_24BIT ((uint32_t) 0x07U)

24-bit interface.

◆ APP_DCTRL_VIFW_30BIT

#define APP_DCTRL_VIFW_30BIT ((uint32_t) 0x08U)

30-bit interface.

◆ APP_DCTRL_VIFW_36BIT

#define APP_DCTRL_VIFW_36BIT ((uint32_t) 0x09U)

36-bit interface.

◆ APP_DCTRL_VIFW_1LANES

#define APP_DCTRL_VIFW_1LANES ((uint32_t) 0x0AU)

CSI2 specific - 1 data lanes.

◆ APP_DCTRL_VIFW_2LANES

#define APP_DCTRL_VIFW_2LANES ((uint32_t) 0x0BU)

CSI2 specific - 2 data lanes.

◆ APP_DCTRL_VIFW_3LANES

#define APP_DCTRL_VIFW_3LANES ((uint32_t) 0x0CU)

CSI2 specific - 3 data lanes.

◆ APP_DCTRL_VIFW_4LANES

#define APP_DCTRL_VIFW_4LANES ((uint32_t) 0x0DU)

CSI2 / LVDS specific - 4 data lanes.

◆ APP_DCTRL_VIFW_MAX

#define APP_DCTRL_VIFW_MAX ((uint32_t) 0x0EU)

Maximum modes.

◆ APP_DCTRL_POL_LOW

#define APP_DCTRL_POL_LOW ((uint32_t) 0U)

Low Polarity.

◆ APP_DCTRL_POL_HIGH

#define APP_DCTRL_POL_HIGH ((uint32_t) 1U)

High Polarity.

◆ APP_DCTRL_POL_MAX

#define APP_DCTRL_POL_MAX ((uint32_t) 2U)

Used by driver for validating the input parameters.

◆ APP_DCTRL_EDGE_POL_RISING

#define APP_DCTRL_EDGE_POL_RISING ((uint32_t) 0U)

Rising Edge.

◆ APP_DCTRL_EDGE_POL_FALLING

#define APP_DCTRL_EDGE_POL_FALLING ((uint32_t) 1U)

Falling Edge.

◆ APP_DCTRL_EDGE_POL_MAX

#define APP_DCTRL_EDGE_POL_MAX ((uint32_t) 2U)

Used by driver for validating the input parameters.

◆ APP_DCTRL_HVSYNC_ALIGN_OFF

#define APP_DCTRL_HVSYNC_ALIGN_OFF ((uint32_t) 0U)

HS/VS not aligned.

◆ APP_DCTRL_HVSYNC_ALIGN_ON

#define APP_DCTRL_HVSYNC_ALIGN_ON ((uint32_t) 1U)

HS/VS aligned.

◆ APP_DCTRL_HVSYNC_ALIGN_MAX

#define APP_DCTRL_HVSYNC_ALIGN_MAX ((uint32_t) 2U)

Used by driver for validating the input parameters.

◆ APP_DCTRL_HVCLK_CTRL_OFF

#define APP_DCTRL_HVCLK_CTRL_OFF ((uint32_t) 0U)

HSYNC and VSYNC are driven on opposite edges of the pixel clock than pixel data.

◆ APP_DCTRL_HVCLK_CTRL_ON

#define APP_DCTRL_HVCLK_CTRL_ON ((uint32_t) 1U)

HSYNC and VSYNC are driven according to hVClkRiseFall value.

◆ APP_DCTRL_HVCLK_CTRL_MAX

#define APP_DCTRL_HVCLK_CTRL_MAX ((uint32_t) 2U)

Used by driver for validating the input parameters.

◆ APP_DCTRL_OVERLAY_TRANS_COLOR_DEST

#define APP_DCTRL_OVERLAY_TRANS_COLOR_DEST ((uint32_t) 0U)

Destination transparency color key selected.

◆ APP_DCTRL_OVERLAY_TRANS_COLOR_SRC

#define APP_DCTRL_OVERLAY_TRANS_COLOR_SRC ((uint32_t) 1U)

Source transparency color key selected.

◆ APP_DCTRL_OVERLAY_LAYER_NUM_0

#define APP_DCTRL_OVERLAY_LAYER_NUM_0 ((uint32_t) 0x0U)

Overlay Layer 0.

◆ APP_DCTRL_OVERLAY_LAYER_NUM_1

#define APP_DCTRL_OVERLAY_LAYER_NUM_1 ((uint32_t) 0x1U)

Overlay Layer 1.

◆ APP_DCTRL_OVERLAY_LAYER_NUM_2

#define APP_DCTRL_OVERLAY_LAYER_NUM_2 ((uint32_t) 0x2U)

Overlay Layer 2.

◆ APP_DCTRL_OVERLAY_LAYER_NUM_3

#define APP_DCTRL_OVERLAY_LAYER_NUM_3 ((uint32_t) 0x3U)

Overlay Layer 3.

◆ APP_DCTRL_OVERLAY_LAYER_NUM_4

#define APP_DCTRL_OVERLAY_LAYER_NUM_4 ((uint32_t) 0x4U)

Overlay Layer 3.

◆ APP_DCTRL_OVERLAY_LAYER_MAX

#define APP_DCTRL_OVERLAY_LAYER_MAX ((uint32_t) 0x5U)

Maximum overlay layers.

◆ APP_DCTRL_OVERLAY_LAYER_INVALID

#define APP_DCTRL_OVERLAY_LAYER_INVALID ((uint32_t) 0xFFU)

Invalid Overlay Layer.

◆ APP_DCTRL_CMD_BASE

#define APP_DCTRL_CMD_BASE ((uint32_t) 0x0U)

Base address for the display controller commands.

◆ APP_DCTRL_CMD_REGISTER_HANDLE

#define APP_DCTRL_CMD_REGISTER_HANDLE (APP_DCTRL_CMD_BASE + 0x1U)

Command to register the FVID2 Handle for display controller.

◆ APP_DCTRL_CMD_DELETE_HANDLE

#define APP_DCTRL_CMD_DELETE_HANDLE (APP_DCTRL_CMD_BASE + 0x2U)

Command to unregister the FVID2 Handle for display controller.

◆ APP_DCTRL_CMD_SET_PATH

#define APP_DCTRL_CMD_SET_PATH (APP_DCTRL_CMD_BASE + 0x3U)

Command to set the DSS display path configuration.

◆ APP_DCTRL_CMD_CLEAR_PATH

#define APP_DCTRL_CMD_CLEAR_PATH (APP_DCTRL_CMD_BASE + 0x4U)

Command to clear the DSS display path configuration.

◆ APP_DCTRL_CMD_SET_VP_PARAMS

#define APP_DCTRL_CMD_SET_VP_PARAMS (APP_DCTRL_CMD_BASE + 0x5U)

Command to set Video Port configuration.

◆ APP_DCTRL_CMD_SET_OVERLAY_PARAMS

#define APP_DCTRL_CMD_SET_OVERLAY_PARAMS (APP_DCTRL_CMD_BASE + 0x6U)

Command to set configuration of the given overlay.

◆ APP_DCTRL_CMD_SET_LAYER_PARAMS

#define APP_DCTRL_CMD_SET_LAYER_PARAMS (APP_DCTRL_CMD_BASE + 0x7U)

Command to set layer/Z-order configuration of the given overlay.

◆ APP_DCTRL_CMD_STOP_VP

#define APP_DCTRL_CMD_STOP_VP (APP_DCTRL_CMD_BASE + 0x8U)

Command to disable Video Port.

◆ APP_DCTRL_CMD_SET_ADV_VP_PARAMS

#define APP_DCTRL_CMD_SET_ADV_VP_PARAMS (APP_DCTRL_CMD_BASE + 0x9U)

Command to to set advance Video Port configuration.

◆ APP_DCTRL_CMD_SET_DSI_PARAMS

#define APP_DCTRL_CMD_SET_DSI_PARAMS (APP_DCTRL_CMD_BASE + 0xAU)

Command to to set DSI parameters/configuration.

◆ APP_DCTRL_CMD_IS_DP_CONNECTED

#define APP_DCTRL_CMD_IS_DP_CONNECTED (APP_DCTRL_CMD_BASE + 0xBU)

Command to query whether DP is connected.

◆ APP_DSS_DEFAULT_DISPLAY_TYPE_EDP

#define APP_DSS_DEFAULT_DISPLAY_TYPE_EDP (0u)

On-chip eDP/DP display.

◆ APP_DSS_DEFAULT_DISPLAY_TYPE_DPI_HDMI

#define APP_DSS_DEFAULT_DISPLAY_TYPE_DPI_HDMI (1u)

Off-chip HDMI display using DPI output from SoC.

◆ APP_DSS_DEFAULT_DISPLAY_TYPE_DSI

Parameters

prms	[IN] Pointer to app_dctrl_dsi_params_t structure.

Returns: None

◆ appDctrlInit()

int32_t appDctrlInit ( void )

DCTRL initialization function.

◆ appDctrlDeInit()

int32_t appDctrlDeInit ( void )

DCTRL de-initialization function.

◆ appDssDefaultSetDefaultPrm()

void appDssDefaultSetDefaultPrm ( app_dss_default_prm_t * prm )

Set default parameters to use for appDssDefaultInit()

◆ appDssDefaultInit()

int32_t appDssDefaultInit ( app_dss_default_prm_t * prm )

DSS initialization wrapper function.

◆ appDssDefaultDeInit()

int32_t appDssDefaultDeInit ( void )

DSS de-initialization wrapper function.

◆ appDssDualDisplayDefaultSetDefaultPrm()

void appDssDualDisplayDefaultSetDefaultPrm ( app_dss_dual_display_default_prm_t * prm )

Set default parameters to use for appDssDualDisplayDefaultInit()

◆ appDssDualDisplayDefaultInit()

int32_t appDssDualDisplayDefaultInit ( app_dss_dual_display_default_prm_t * prm )

DSS initialization wrapper function for dual display mode.

◆ appDssDualDisplayDefaultDeInit()

int32_t appDssDualDisplayDefaultDeInit ( void )

DSS de-initialization wrapper function for dual display mode.

Introduction

Data Structures

Functions

Macros

DCTRL Node Id

Video standards

Digital Video Format

Digital video interface width

Polarity type

Edge Polarity type

HS/VS alignment types

HS/VS pixel clock control types

Overlay Transparency Color Key Selection

Overlay Layer Number

Display contorller CMD IDs to pass to appRemoteServiceRun()

Macro Definition Documentation

◆ APP_DCTRL_REMOTE_SERVICE_NAME

◆ APP_DCTRL_NODE_INVALID

◆ APP_DCTRL_NODE_VID1

◆ APP_DCTRL_NODE_VIDL1

◆ APP_DCTRL_NODE_VID2

◆ APP_DCTRL_NODE_VIDL2

◆ APP_DCTRL_NODE_OVERLAY1

◆ APP_DCTRL_NODE_OVERLAY2

◆ APP_DCTRL_NODE_OVERLAY3

◆ APP_DCTRL_NODE_OVERLAY4

◆ APP_DCTRL_NODE_VP1

◆ APP_DCTRL_NODE_VP2

◆ APP_DCTRL_NODE_VP3

◆ APP_DCTRL_NODE_VP4

◆ APP_DCTRL_NODE_DPI_DPI0

◆ APP_DCTRL_NODE_DPI_DPI1

◆ APP_DCTRL_NODE_EDP_DPI0

◆ APP_DCTRL_NODE_EDP_DPI1

◆ APP_DCTRL_NODE_EDP_DPI2

◆ APP_DCTRL_NODE_EDP_DPI3

◆ APP_DCTRL_NODE_DSI_DPI2

◆ APP_DCTRL_MAX_EDGES

◆ APP_DCTRL_VID_STD_NTSC

◆ APP_DCTRL_VID_STD_PAL

◆ APP_DCTRL_VID_STD_480I

◆ APP_DCTRL_VID_STD_576I

◆ APP_DCTRL_VID_STD_CIF

◆ APP_DCTRL_VID_STD_HALF_D1

◆ APP_DCTRL_VID_STD_D1

◆ APP_DCTRL_VID_STD_480P

◆ APP_DCTRL_VID_STD_576P

◆ APP_DCTRL_VID_STD_720P_60

◆ APP_DCTRL_VID_STD_720P_50

◆ APP_DCTRL_VID_STD_1080I_60

◆ APP_DCTRL_VID_STD_1080I_50

◆ APP_DCTRL_VID_STD_1080P_60

◆ APP_DCTRL_VID_STD_1080P_50

◆ APP_DCTRL_VID_STD_1080P_24

◆ APP_DCTRL_VID_STD_1080P_30

◆ APP_DCTRL_VID_STD_VGA_60

◆ APP_DCTRL_VID_STD_VGA_72

◆ APP_DCTRL_VID_STD_VGA_75

◆ APP_DCTRL_VID_STD_VGA_85

◆ APP_DCTRL_VID_STD_WVGA_60

◆ APP_DCTRL_VID_STD_SVGA_60

◆ APP_DCTRL_VID_STD_SVGA_72

◆ APP_DCTRL_VID_STD_SVGA_75

◆ APP_DCTRL_VID_STD_SVGA_85

◆ APP_DCTRL_VID_STD_WSVGA_70

◆ APP_DCTRL_VID_STD_XGA_60

◆ APP_DCTRL_VID_STD_XGA_DSS_TDM_60

◆ APP_DCTRL_VID_STD_XGA_70

◆ APP_DCTRL_VID_STD_XGA_75

◆ APP_DCTRL_VID_STD_XGA_85

◆ APP_DCTRL_VID_STD_1368_768_60

◆ APP_DCTRL_VID_STD_1366_768_60

◆ APP_DCTRL_VID_STD_1360_768_60

◆ APP_DCTRL_VID_STD_WXGA_30

◆ APP_DCTRL_VID_STD_WXGA_60

◆ APP_DCTRL_VID_STD_WXGA_75

◆ APP_DCTRL_VID_STD_WXGA_85

◆ APP_DCTRL_VID_STD_1440_900_60

◆ APP_DCTRL_VID_STD_SXGA_60

◆ APP_DCTRL_VID_STD_SXGA_75