 |
J722S MCU+ SDK
10.00.00
|
|
|
J722S MCU+ SDK
10.00.00
|
|
DMSC controls the power management, security and resource management of the device.
| #define TISCI_DEV_DBGSUSPENDROUTER0 2U |
This file contains:
WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!
Data version: 240122_143513
| #define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3U |
| #define TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5U |
| #define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0 6U |
| #define TISCI_DEV_MCU_R5FSS0 7U |
| #define TISCI_DEV_MCU_R5FSS0_CORE0 9U |
| #define TISCI_DEV_CPSW0 13U |
| #define TISCI_DEV_STM0 15U |
| #define TISCI_DEV_DCC0 16U |
| #define TISCI_DEV_DCC1 17U |
| #define TISCI_DEV_DCC2 18U |
| #define TISCI_DEV_DCC3 19U |
| #define TISCI_DEV_DCC4 20U |
| #define TISCI_DEV_DCC5 21U |
| #define TISCI_DEV_SMS0 22U |
| #define TISCI_DEV_MCU_DCC0 23U |
| #define TISCI_DEV_DEBUGSS_WRAP0 24U |
| #define TISCI_DEV_DMASS0 25U |
| #define TISCI_DEV_DMASS0_BCDMA_0 26U |
| #define TISCI_DEV_DMASS0_CBASS_0 27U |
| #define TISCI_DEV_DMASS0_INTAGGR_0 28U |
| #define TISCI_DEV_DMASS0_IPCSS_0 29U |
| #define TISCI_DEV_DMASS0_PKTDMA_0 30U |
| #define TISCI_DEV_DMASS0_RINGACC_0 33U |
| #define TISCI_DEV_MCU_TIMER0 35U |
| #define TISCI_DEV_TIMER0 36U |
| #define TISCI_DEV_TIMER1 37U |
| #define TISCI_DEV_TIMER2 38U |
| #define TISCI_DEV_TIMER3 39U |
| #define TISCI_DEV_TIMER4 40U |
| #define TISCI_DEV_TIMER5 41U |
| #define TISCI_DEV_TIMER6 42U |
| #define TISCI_DEV_TIMER7 43U |
| #define TISCI_DEV_MCU_TIMER1 48U |
| #define TISCI_DEV_MCU_TIMER2 49U |
| #define TISCI_DEV_MCU_TIMER3 50U |
| #define TISCI_DEV_ECAP0 51U |
| #define TISCI_DEV_ECAP1 52U |
| #define TISCI_DEV_ECAP2 53U |
| #define TISCI_DEV_ELM0 54U |
| #define TISCI_DEV_MAIN_EMIF_DATA_ISO_VD 55U |
| #define TISCI_DEV_MMCSD0 57U |
| #define TISCI_DEV_MMCSD1 58U |
| #define TISCI_DEV_EQEP0 59U |
| #define TISCI_DEV_EQEP1 60U |
| #define TISCI_DEV_WKUP_GTC0 61U |
| #define TISCI_DEV_EQEP2 62U |
| #define TISCI_DEV_ESM0 63U |
| #define TISCI_DEV_WKUP_ESM0 64U |
| #define TISCI_DEV_FSS0 73U |
| #define TISCI_DEV_FSS0_FSAS_0 74U |
| #define TISCI_DEV_FSS0_OSPI_0 75U |
| #define TISCI_DEV_GICSS0 76U |
| #define TISCI_DEV_GPIO0 77U |
| #define TISCI_DEV_GPIO1 78U |
| #define TISCI_DEV_MCU_GPIO0 79U |
| #define TISCI_DEV_GPMC0 80U |
| #define TISCI_DEV_LED0 83U |
| #define TISCI_DEV_DDPA0 85U |
| #define TISCI_DEV_EPWM0 86U |
| #define TISCI_DEV_EPWM1 87U |
| #define TISCI_DEV_EPWM2 88U |
| #define TISCI_DEV_WKUP_VTM0 95U |
| #define TISCI_DEV_MAILBOX0 96U |
| #define TISCI_DEV_MAIN2MCU_VD 97U |
| #define TISCI_DEV_MCAN0 98U |
| #define TISCI_DEV_MCAN1 99U |
| #define TISCI_DEV_MCU_MCRC64_0 100U |
| #define TISCI_DEV_I2C0 102U |
| #define TISCI_DEV_I2C1 103U |
| #define TISCI_DEV_I2C2 104U |
| #define TISCI_DEV_I2C3 105U |
| #define TISCI_DEV_MCU_I2C0 106U |
| #define TISCI_DEV_WKUP_I2C0 107U |
| #define TISCI_DEV_WKUP_TIMER0 110U |
| #define TISCI_DEV_WKUP_TIMER1 111U |
| #define TISCI_DEV_WKUP_UART0 114U |
| #define TISCI_DEV_MCRC64_0 116U |
| #define TISCI_DEV_WKUP_RTCSS0 117U |
| #define TISCI_DEV_WKUP_R5FSS0_SS0 118U |
| #define TISCI_DEV_WKUP_R5FSS0 119U |
| #define TISCI_DEV_WKUP_R5FSS0_CORE0 121U |
| #define TISCI_DEV_RTI0 125U |
| #define TISCI_DEV_RTI1 126U |
| #define TISCI_DEV_RTI2 127U |
| #define TISCI_DEV_RTI3 128U |
| #define TISCI_DEV_RTI15 130U |
| #define TISCI_DEV_MCU_RTI0 131U |
| #define TISCI_DEV_WKUP_RTI0 132U |
| #define TISCI_DEV_COMPUTE_CLUSTER0 134U |
| #define TISCI_DEV_A53SS0_CORE_0 135U |
| #define TISCI_DEV_A53SS0_CORE_1 136U |
| #define TISCI_DEV_A53SS0_CORE_2 137U |
| #define TISCI_DEV_A53SS0_CORE_3 138U |
| #define TISCI_DEV_PSCSS0 139U |
| #define TISCI_DEV_WKUP_PSC0 140U |
| #define TISCI_DEV_MCSPI0 141U |
| #define TISCI_DEV_MCSPI1 142U |
| #define TISCI_DEV_MCSPI2 143U |
| #define TISCI_DEV_UART0 146U |
| #define TISCI_DEV_MCU_MCSPI0 147U |
| #define TISCI_DEV_MCU_MCSPI1 148U |
| #define TISCI_DEV_MCU_UART0 149U |
| #define TISCI_DEV_SPINLOCK0 150U |
| #define TISCI_DEV_UART1 152U |
| #define TISCI_DEV_UART2 153U |
| #define TISCI_DEV_UART3 154U |
| #define TISCI_DEV_UART4 155U |
| #define TISCI_DEV_UART5 156U |
| #define TISCI_DEV_BOARD0 157U |
| #define TISCI_DEV_UART6 158U |
| #define TISCI_DEV_USB0 161U |
| #define TISCI_DEV_PBIST0 163U |
| #define TISCI_DEV_WKUP_PBIST0 165U |
| #define TISCI_DEV_A53SS0 166U |
| #define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0 167U |
| #define TISCI_DEV_PSC0_FW_0 168U |
| #define TISCI_DEV_PSC0 169U |
| #define TISCI_DEV_DDR32SS0 170U |
| #define TISCI_DEV_DEBUGSS0 171U |
| #define TISCI_DEV_A53_RS_BW_LIMITER0 172U |
| #define TISCI_DEV_A53_WS_BW_LIMITER1 173U |
| #define TISCI_DEV_GPU_RS_BW_LIMITER9 174U |
| #define TISCI_DEV_GPU_WS_BW_LIMITER10 175U |
| #define TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0 176U |
| #define TISCI_DEV_MAIN_EMIF_CFG_ISO_VD 177U |
| #define TISCI_DEV_MAIN_USB0_ISO_VD 178U |
| #define TISCI_DEV_MAIN_USB2_ISO_VD 179U |
| #define TISCI_DEV_MCU_MCU_16FF0 180U |
| #define TISCI_DEV_CSI_RX_IF0 182U |
| #define TISCI_DEV_DCC6 183U |
| #define TISCI_DEV_MMCSD2 184U |
| #define TISCI_DEV_DPHY_RX0 185U |
| #define TISCI_DEV_DSS0 186U |
| #define TISCI_DEV_MCU_MCAN0 188U |
| #define TISCI_DEV_MCU_MCAN1 189U |
| #define TISCI_DEV_MCASP0 190U |
| #define TISCI_DEV_MCASP1 191U |
| #define TISCI_DEV_MCASP2 192U |
| #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD 193U |
| #define TISCI_DEV_CPT2_AGGR1 194U |
| #define TISCI_DEV_CPT2_AGGR0 195U |
| #define TISCI_DEV_MCU_CPT2_AGGR0 196U |
| #define TISCI_DEV_MCU_DCC1 197U |
| #define TISCI_DEV_DMASS1 198U |
| #define TISCI_DEV_DMASS1_BCDMA_0 199U |
| #define TISCI_DEV_DMASS1_INTAGGR_0 200U |
| #define TISCI_DEV_JPGENC0 201U |
| #define TISCI_DEV_WKUP_PBIST1 202U |
| #define TISCI_DEV_MCU_PBIST0 203U |
| #define TISCI_DEV_CODEC0 204U |
| #define TISCI_DEV_RTI4 205U |
| #define TISCI_DEV_C7XV_RSWS_BS_LIMITER6 206U |
| #define TISCI_DEV_C7X256V0 207U |
| #define TISCI_DEV_C7X256V0_C7XV_CORE_0 208U |
| #define TISCI_DEV_C7X256V0_CORE0 209U |
| #define TISCI_DEV_C7X256V0_CLEC 210U |
| #define TISCI_DEV_C7X256V0_CLK 211U |
| #define TISCI_DEV_C7X256V0_DEBUG 212U |
| #define TISCI_DEV_C7X256V0_GICSS 213U |
| #define TISCI_DEV_C7X256V0_PBIST 214U |
| #define TISCI_DEV_JPGENC_RS_BW_LIMITER4 215U |
| #define TISCI_DEV_JPGENC_WS_BW_LIMITER5 216U |
| #define TISCI_DEV_VPAC_RSWS_BW_LIMITER8 217U |
| #define TISCI_DEV_VPAC_RSWS_BW_LIMITER7 218U |
| #define TISCI_DEV_VPAC0 219U |
| #define TISCI_DEV_PBIST3 220U |
| #define TISCI_DEV_CODEC_RS_BW_LIMITER2 221U |
| #define TISCI_DEV_CODEC_WS_BW_LIMITER3 222U |
| #define TISCI_DEV_HSM0 225U |
| #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD 226U |
| #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD 227U |
| #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD 228U |
| #define TISCI_DEV_DCC7 229U |
| #define TISCI_DEV_DCC8 230U |
| #define TISCI_DEV_DSS_DSI0 231U |
| #define TISCI_DEV_DSS1 232U |
| #define TISCI_DEV_PBIST1 233U |
| #define TISCI_DEV_OLDI_TX_CORE0 234U |
| #define TISCI_DEV_OLDI_TX_CORE1 235U |
| #define TISCI_DEV_GPU0 237U |
| #define TISCI_DEV_DPHY_TX0 238U |
| #define TISCI_DEV_DSS1_DPI1_PLLSEL_DEV_VD 240U |
| #define TISCI_DEV_DSS1_DPI0_PLLSEL_DEV_VD 241U |
| #define TISCI_DEV_GPU0_CORE_VD 242U |
| #define TISCI_DEV_OLDI0_VD 243U |
| #define TISCI_DEV_OLDI1_VD 244U |
| #define TISCI_DEV_DPI0_OUT_SEL_DEV_VD 245U |
| #define TISCI_DEV_ATL0 246U |
| #define TISCI_DEV_CSI_RX_IF1 247U |
| #define TISCI_DEV_CSI_RX_IF2 248U |
| #define TISCI_DEV_CSI_RX_IF3 249U |
| #define TISCI_DEV_CSI_TX_IF0 250U |
| #define TISCI_DEV_DPHY_RX1 251U |
| #define TISCI_DEV_DPHY_RX2 252U |
| #define TISCI_DEV_DPHY_RX3 253U |
| #define TISCI_DEV_PBIST2 254U |
| #define TISCI_DEV_MCASP3 255U |
| #define TISCI_DEV_MCASP4 256U |
| #define TISCI_DEV_I2C4 257U |
| #define TISCI_DEV_MSRAM8KX256E0 258U |
| #define TISCI_DEV_PCIE0 259U |
| #define TISCI_DEV_R5FSS0_SS0 260U |
| #define TISCI_DEV_R5FSS0 261U |
| #define TISCI_DEV_R5FSS0_CORE0 262U |
| #define TISCI_DEV_RTI5 263U |
| #define TISCI_DEV_RTI8 264U |
| #define TISCI_DEV_COMPUTE_CLUSTER0_CLKDIV_0 265U |
| #define TISCI_DEV_C7XV_RSWS_BS_LIMITER11 266U |
| #define TISCI_DEV_C7X256V1 267U |
| #define TISCI_DEV_C7X256V1_C7XV_CORE_0 268U |
| #define TISCI_DEV_C7X256V1_CORE0 269U |
| #define TISCI_DEV_C7X256V1_CLEC 270U |
| #define TISCI_DEV_C7X256V1_CLK 271U |
| #define TISCI_DEV_C7X256V1_DEBUG 272U |
| #define TISCI_DEV_C7X256V1_GICSS 273U |
| #define TISCI_DEV_C7X256V1_PBIST 274U |
| #define TISCI_DEV_CTI0 275U |
| #define TISCI_DEV_CTI1 276U |
| #define TISCI_DEV_DMPAC0 277U |
| #define TISCI_DEV_USB1 278U |
| #define TISCI_DEV_SERDES_10G0 279U |
| #define TISCI_DEV_SERDES_10G1 280U |
| #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD 281U |
| #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD 282U |
| #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD 283U |
| #define TISCI_DEV_TIMER1_CLKSEL_VD 284U |
| #define TISCI_DEV_TIMER3_CLKSEL_VD 285U |
| #define TISCI_DEV_TIMER5_CLKSEL_VD 286U |
| #define TISCI_DEV_TIMER7_CLKSEL_VD 287U |
1.8.20